From 24dffa39d556e98c7bdd8e168fbcd9ee59c78af2 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 7 Mar 2024 12:48:52 -0600 Subject: [PATCH 1/4] Yay. David and I got our first Quad load/store instructions working! --- testbench/testbench.sv | 1 + testbench/tests.vh | 4 ++++ tests/riscof/spike/spike_rv64gc_isa.yaml | 4 ++-- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index d52c0baf8..1a72d4f0f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -124,6 +124,7 @@ module testbench; "imperas64f": if (P.F_SUPPORTED) tests = imperas64f; "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; + "wally64q": if (P.Q_SUPPORTED) tests = wally64q; "wally64a": if (P.A_SUPPORTED) tests = wally64a; "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; diff --git a/testbench/tests.vh b/testbench/tests.vh index 95ebb74b3..afde1f2e6 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -869,6 +869,10 @@ string imperas32f[] = '{ "rv32i_m/I/XORI-01" }; + string wally64q[] = '{ + `WALLYTEST, + "rv64i_m/Q/src/WALLY-q-01.S" + }; string wally64a[] = '{ `WALLYTEST, diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 4374ad07c..7bbcaf9e5 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -2,12 +2,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb + ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000014112D + reset-val: 0x800000000015112D rv32: accessible: false rv64: From 1872966b0b6bb1f9a07b1d7e9e42f37a4539cb49 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 7 Mar 2024 13:02:24 -0600 Subject: [PATCH 2/4] Progress. --- .../Q/references/WALLY-q-01.reference_output | 8 ++ .../rv64i_m/Q/src/WALLY-q-01.S | 117 ++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output new file mode 100644 index 000000000..ccd487ddd --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output @@ -0,0 +1,8 @@ +00000000 # fsq of 1 +00000000 +00000000 +3fff0000 +00003f00 # fsh of 1 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S new file mode 100644 index 000000000..79e856a95 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S @@ -0,0 +1,117 @@ +/////////////////////////////////////////// +// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S +// David_Harris@hmc.edu & Rose Thompson +// Created 07 March 2024 +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDQ_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*Q.*);def TEST_CASE_1=True;def NO_SAIL=True",flq-align) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +#endif + + # turn on the floating point unit + li x7, 1 + slli x7, x7, 13 + csrw mstatus, x7 + +li x4, 1 # 3fff 0000 0000 0000 0000 0000 0000 0000 +li x2, 2 # 4000 0000 0000 0000 0000 0000 0000 0000 +fcvt.q.w f2, x2 +fcvt.q.w f4, x4 + +fcvt.h.w f5, x2 + +# test quad load/store +fsq f4, 0(x3) +flq f7, 0(x3) +fsq f7, 0(x1) + +# test half load/store +fsh f5, 16(x3) +flh f6, 16(x3) +fsh f6, 16(x1) + +# 1 + 2 = 3 # 4000 1000 0000 0000 0000 0000 0000 0000 +fadd.q f8, f2, f4 +fsq f8, 32(x3) + +# 1 - 2 = -1 +fsub.q f9, f2, f4 # bfff 0000000000000000000000000000 +fsq f9, 48(x3) + +# 2 * 3 = 6 +fsub.q f10, f4, f8 # 4001 1000000000000000000000000000 +fsq f10, 64(x3) + +# 6 * (-1) + 2 = -4 +fmadd.q f11, f10, f9, f4 # C001 0000000000000000000000000000 +fsq f11, 80(x3) + +# -4 / 2 = -2 +fdiv.q f12, f11, f4 # C000 0000000000000000000000000000 +fsq f12, 96(x3) + +# sign injection -4 = 4 +fsgnj.q f13, f12, f4 # 4001 0000000000000000000000000000 +fsq f13, 112(x3) + +# sqrt(4) = 2 +fsqrt.q f14, f13 # 4000 0000000000000000000000000000 +fsq f14, 128(x3) + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xecafebab +test_dataset_0: +test_dataset_1: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: + + + + +signature_x1_1: + .fill 8,8,0xdeadbeefdeadbeef + .fill 8,8,0xdeadbeefdeadbeef + +rvtest_sig_end: +RVMODEL_DATA_END From a85ace87c72683c1285571deb9748ee899667456 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 7 Mar 2024 15:01:48 -0600 Subject: [PATCH 3/4] Sold progress towards a decent q test. --- .../Q/references/WALLY-q-01.reference_output | 30 ++++++- .../rv64i_m/Q/src/WALLY-q-01.S | 81 ++++++++++++++----- 2 files changed, 88 insertions(+), 23 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output index ccd487ddd..6f8523bbf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output @@ -2,7 +2,35 @@ 00000000 00000000 3fff0000 -00003f00 # fsh of 1 +dead4000 # fsh of 1 +deadbeef +deadbeef +deadbeef +00000000 # fsq of 3 00000000 00000000 +40008000 +00000000 # fsq of -1 00000000 +00000000 +bfff0000 +00000000 # fsq of 6 +00000000 +00000000 +40018000 +00000000 # fsq of -4 +00000000 +00000000 +C0010000 +00000000 # fsq of -2 +00000000 +00000000 +C0000000 +00000000 # fsq of 4 +00000000 +00000000 +40010000 +00000000 # fsq of 2 +00000000 +00000000 +40000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S index 79e856a95..791d41a8a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S @@ -19,7 +19,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64IFDQ_Zicsr") +RVTEST_ISA("RV64IFDQZfh_Zicsr") .section .text.init .globl rvtest_entry_point @@ -37,17 +37,17 @@ RVTEST_SIGBASE(x1,signature_x1_1) #endif - # turn on the floating point unit - li x7, 1 - slli x7, x7, 13 - csrw mstatus, x7 +# turn on the floating point unit +li x7, 1 +slli x7, x7, 13 +csrw mstatus, x7 li x4, 1 # 3fff 0000 0000 0000 0000 0000 0000 0000 li x2, 2 # 4000 0000 0000 0000 0000 0000 0000 0000 fcvt.q.w f2, x2 fcvt.q.w f4, x4 -fcvt.h.w f5, x2 +fcvt.h.w f5, x2 # 4000 # test quad load/store fsq f4, 0(x3) @@ -59,33 +59,33 @@ fsh f5, 16(x3) flh f6, 16(x3) fsh f6, 16(x1) -# 1 + 2 = 3 # 4000 1000 0000 0000 0000 0000 0000 0000 +# 1 + 2 = 3 # 4000 8000 0000 0000 0000 0000 0000 0000 fadd.q f8, f2, f4 -fsq f8, 32(x3) +fsq f8, 32(x1) # 1 - 2 = -1 -fsub.q f9, f2, f4 # bfff 0000000000000000000000000000 -fsq f9, 48(x3) +fsub.q f9, f4, f2 # bfff 0000000000000000000000000000 +fsq f9, 48(x1) # 2 * 3 = 6 -fsub.q f10, f4, f8 # 4001 1000000000000000000000000000 -fsq f10, 64(x3) +fmul.q f10, f2, f8 # 4001 8000000000000000000000000000 +fsq f10, 64(x1) # 6 * (-1) + 2 = -4 -fmadd.q f11, f10, f9, f4 # C001 0000000000000000000000000000 -fsq f11, 80(x3) +fmadd.q f11, f10, f9, f2 # C001 0000000000000000000000000000 +fsq f11, 80(x1) # -4 / 2 = -2 -fdiv.q f12, f11, f4 # C000 0000000000000000000000000000 -fsq f12, 96(x3) +fdiv.q f12, f11, f2 # C000 0000000000000000000000000000 +fsq f12, 96(x1) # sign injection -4 = 4 fsgnj.q f13, f12, f4 # 4001 0000000000000000000000000000 -fsq f13, 112(x3) +fsq f13, 112(x1) # sqrt(4) = 2 fsqrt.q f14, f13 # 4000 0000000000000000000000000000 -fsq f14, 128(x3) +fsq f14, 128(x1) RVTEST_CODE_END @@ -94,12 +94,43 @@ RVMODEL_HALT RVTEST_DATA_BEGIN .align 4 rvtest_data: +test_dataset_0: .word 0xbabecafe .word 0xabecafeb .word 0xbecafeba .word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba .word 0xecafebab -test_dataset_0: test_dataset_1: RVTEST_DATA_END @@ -110,8 +141,14 @@ rvtest_sig_begin: signature_x1_1: - .fill 8,8,0xdeadbeefdeadbeef - .fill 8,8,0xdeadbeefdeadbeef - + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef + .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef rvtest_sig_end: RVMODEL_DATA_END From 402d71e5f481857f2411d5c55d86fee1a4074dd1 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 7 Mar 2024 15:19:53 -0600 Subject: [PATCH 4/4] Added basic Quad testing. --- sim/regression-wally | 2 +- .../riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index ea855b358..26543d067 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -278,7 +278,7 @@ if (nightly): ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma"]], - ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "wally64q"]], ] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S index 791d41a8a..ea8bd15d5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S @@ -79,8 +79,8 @@ fsq f11, 80(x1) fdiv.q f12, f11, f2 # C000 0000000000000000000000000000 fsq f12, 96(x1) -# sign injection -4 = 4 -fsgnj.q f13, f12, f4 # 4001 0000000000000000000000000000 +# sign injection (-4, 1) = 4 +fsgnj.q f13, f11, f4 # 4001 0000000000000000000000000000 fsq f13, 112(x1) # sqrt(4) = 2