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https://github.com/openhwgroup/cvw
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atomic cleanup.
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parent
257015a2df
commit
7f0c5cc847
@ -41,7 +41,6 @@ module atomic (
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input logic [1:0] LSUAtomicM,
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input logic [1:0] LSUAtomicM,
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input logic [1:0] PreLSURWM,
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input logic [1:0] PreLSURWM,
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input logic IgnoreRequest,
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input logic IgnoreRequest,
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input logic DTLBMissM,
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output logic [`XLEN-1:0] FinalAMOWriteDataM,
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output logic [`XLEN-1:0] FinalAMOWriteDataM,
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output logic SquashSCW,
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output logic SquashSCW,
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output logic [1:0] LSURWM);
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output logic [1:0] LSURWM);
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@ -52,7 +51,7 @@ module atomic (
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amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
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amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
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.result(AMOResult));
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
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mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
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assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; // *** is DTLBMiss needed; might be par tof ignorerequest
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assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
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lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
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lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
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.SquashSCW, .LSURWM);
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.SquashSCW, .LSURWM);
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@ -56,7 +56,7 @@ module interlockfsm(
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logic AnyCPUReqM;
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logic AnyCPUReqM;
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typedef enum logic[2:0] {STATE_T0_READY,
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typedef enum logic[2:0] {STATE_T0_READY,
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STATE_T0_REPLAY,
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STATE_T1_REPLAY,
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STATE_T3_DTLB_MISS,
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STATE_T3_DTLB_MISS,
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STATE_T4_ITLB_MISS,
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STATE_T4_ITLB_MISS,
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STATE_T5_ITLB_MISS,
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STATE_T5_ITLB_MISS,
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@ -82,13 +82,13 @@ module interlockfsm(
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else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
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else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
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else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
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else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
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else InterlockNextState = STATE_T0_READY;
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else InterlockNextState = STATE_T0_READY;
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STATE_T0_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T0_REPLAY;
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STATE_T1_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T1_REPLAY;
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else InterlockNextState = STATE_T0_READY;
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else InterlockNextState = STATE_T0_READY;
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STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
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STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T1_REPLAY;
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else InterlockNextState = STATE_T3_DTLB_MISS;
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else InterlockNextState = STATE_T3_DTLB_MISS;
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STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
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STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
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else InterlockNextState = STATE_T4_ITLB_MISS;
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else InterlockNextState = STATE_T4_ITLB_MISS;
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STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY;
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STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T1_REPLAY;
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else InterlockNextState = STATE_T5_ITLB_MISS;
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else InterlockNextState = STATE_T5_ITLB_MISS;
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STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
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STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
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else InterlockNextState = STATE_T7_DITLB_MISS;
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else InterlockNextState = STATE_T7_DITLB_MISS;
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@ -122,12 +122,12 @@ module interlockfsm(
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endcase
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endcase
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end
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end
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assign SelReplayMemE = (InterlockCurrState == STATE_T0_REPLAY & DCacheStallM) |
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assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY & DCacheStallM) |
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(InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) |
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(InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) |
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(InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF);
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(InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF);
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assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
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assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
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(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
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(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
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assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM));
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assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & (ITLBMissOrDAFaultF | DTLBMissOrDAFaultM));
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assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) |
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assign IgnoreRequestTrapM = (InterlockCurrState == STATE_T0_READY & (TrapM)) |
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((InterlockCurrState == STATE_T0_REPLAY) & (TrapM));
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((InterlockCurrState == STATE_T1_REPLAY) & (TrapM));
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endmodule
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endmodule
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@ -259,12 +259,10 @@ module lsu (
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// *** why does this need DTLBMissM?
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if (`A_SUPPORTED) begin:atomic
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if (`A_SUPPORTED) begin:atomic
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atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
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atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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.DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
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.FinalAMOWriteDataM, .SquashSCW, .LSURWM);
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end else begin:lrsc
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end else begin:lrsc
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assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
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assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
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end
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end
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