diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index a9ce97371..8ba10b292 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -174,7 +174,9 @@ module testbench;
         "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
         "arch64zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch64zicboz;
         "arch64zcb":     if (P.ZCB_SUPPORTED)     tests = arch64zcb;
-        "arch64zfh":     if (P.ZFH_SUPPORTED)     tests = arch64zfh;
+        "arch64zfh":     if (P.ZFH_SUPPORTED)     
+                           if (P.D_SUPPORTED)     tests = {arch64zfh, arch64zfh_d};
+                           else                   tests = arch64zfh;
         "arch64zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch64zfh_fma;
         "arch64zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch64zfh_divsqrt;
         "arch64zfaf":    if (P.ZFA_SUPPORTED)     tests = arch64zfaf;
@@ -222,7 +224,9 @@ module testbench;
         "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
         "arch32zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch32zicboz;
         "arch32zcb":     if (P.ZCB_SUPPORTED)     tests = arch32zcb;
-        "arch32zfh":     if (P.ZFH_SUPPORTED)     tests = arch32zfh;
+        "arch32zfh":     if (P.ZFH_SUPPORTED)     
+                           if (P.D_SUPPORTED)     tests = {arch32zfh, arch32zfh_d};
+                           else                   tests = arch32zfh;
         "arch32zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch32zfh_fma;
         "arch32zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch32zfh_divsqrt;
         "arch32zfaf":    if (P.ZFA_SUPPORTED)     tests = arch32zfaf;
diff --git a/testbench/tests.vh b/testbench/tests.vh
index a5704095e..817b8d6d5 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -1017,20 +1017,6 @@ string arch64zfh[] = '{
   "rv64i_m/Zfh/src/fadd_b7-01.S",
   "rv64i_m/Zfh/src/fadd_b8-01.S",
   "rv64i_m/Zfh/src/fclass_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S",
   "rv64i_m/Zfh/src/fcvt.h.s_b1-01.S",
   "rv64i_m/Zfh/src/fcvt.h.s_b22-01.S",
   "rv64i_m/Zfh/src/fcvt.h.s_b23-01.S",
@@ -1174,7 +1160,23 @@ string arch64zfh[] = '{
   "rv64i_m/Zfh/src/fnmsub_b8-01.S"
 };
 
-
+string arch64zfh_d[] = '{
+  // `RISCVARCHTEST,
+  "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S",
+  "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S",
+  "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S",
+  "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S",
+  "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S",
+  "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S",
+  "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S",
+  "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S"
+};
 
 string arch64d_fma[] = '{
   `RISCVARCHTEST,
@@ -2457,20 +2459,6 @@ string arch32zfh[] = '{
   "rv32i_m/Zfh/src/fadd_b7-01.S",
   "rv32i_m/Zfh/src/fadd_b8-01.S",
   "rv32i_m/Zfh/src/fclass_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S",
   "rv32i_m/Zfh/src/fcvt.h.s_b1-01.S",
   "rv32i_m/Zfh/src/fcvt.h.s_b22-01.S",
   "rv32i_m/Zfh/src/fcvt.h.s_b23-01.S",
@@ -2596,6 +2584,24 @@ string arch32zfh[] = '{
   "rv32i_m/Zfh/src/fnmsub_b8-01.S"
 };
 
+string arch32zfh_d[] = '{
+  // `RISCVARCHTEST,
+  "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S",
+  "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S",
+  "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S",
+  "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S",
+  "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S",
+  "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S",
+  "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S",
+  "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S"
+};
+
 string arch32zfaf[] = '{
   `RISCVARCHTEST,
   "rv32i_m/F_Zfa/src/fround_b1-01.S",