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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Renamed BTB misprediction to BTA.
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bdab2c8506
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@ -64,7 +64,7 @@ module bpred (
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output logic BPWrongE, // Prediction is wrong
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output logic BPWrongE, // Prediction is wrong
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output logic BPWrongM, // Prediction is wrong
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output logic BPWrongM, // Prediction is wrong
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output logic BPDirPredWrongM, // Prediction direction is wrong
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output logic BPDirPredWrongM, // Prediction direction is wrong
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output logic BTBPredPCWrongM, // Prediction target wrong
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output logic BTAWrongM, // Prediction target wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic IClassWrongM // Class prediction is wrong
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output logic IClassWrongM // Class prediction is wrong
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);
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);
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@ -215,10 +215,10 @@ module bpred (
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flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
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flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
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flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
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flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
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{BPDirPredWrongE, BTBPredPCWrongE, RASPredPCWrongE},
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{BPDirPredWrongE, BTBPredPCWrongE, RASPredPCWrongE},
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{BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM});
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{BPDirPredWrongM, BTAWrongM, RASPredPCWrongM});
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end else begin
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end else begin
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assign {BTBPredPCWrongM, RASPredPCWrongM} = '0;
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assign {BTAWrongM, RASPredPCWrongM} = '0;
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end
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end
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// **** Fix me
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// **** Fix me
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@ -66,7 +66,7 @@ module ifu (
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// branch predictor
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// branch predictor
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output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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output logic BPDirPredWrongM, // Prediction direction is wrong
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output logic BPDirPredWrongM, // Prediction direction is wrong
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output logic BTBPredPCWrongM, // Prediction target wrong
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output logic BTAWrongM, // Prediction target wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic RASPredPCWrongM, // RAS prediction is wrong
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output logic IClassWrongM, // Class prediction is wrong
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output logic IClassWrongM, // Class prediction is wrong
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output logic ICacheStallF, // I$ busy with multicycle operation
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output logic ICacheStallF, // I$ busy with multicycle operation
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@ -331,12 +331,12 @@ module ifu (
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.BranchD, .BranchE, .JumpD, .JumpE,
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.BranchD, .BranchE, .JumpD, .JumpE,
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.InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
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.InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
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.PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
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.PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
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.BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM);
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
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end else begin : bpred
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end else begin : bpred
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mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));
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mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));
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assign BPWrongE = PCSrcE;
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assign BPWrongE = PCSrcE;
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assign {InstrClassM, BPDirPredWrongM, BTBPredPCWrongM, RASPredPCWrongM, IClassWrongM} = '0;
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assign {InstrClassM, BPDirPredWrongM, BTAWrongM, RASPredPCWrongM, IClassWrongM} = '0;
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assign NextValidPCE = PCE;
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assign NextValidPCE = PCE;
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end
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end
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@ -62,7 +62,7 @@ module csr #(parameter
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input logic ICacheStallF,
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input logic ICacheStallF,
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input logic DCacheStallM,
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input logic DCacheStallM,
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input logic BPDirPredWrongM,
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input logic BPDirPredWrongM,
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input logic BTBPredPCWrongM,
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input logic BTAWrongM,
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input logic RASPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic IClassWrongM,
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input logic IClassWrongM,
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input logic BPWrongM, // branch predictor is wrong
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input logic BPWrongM, // branch predictor is wrong
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@ -266,7 +266,7 @@ module csr #(parameter
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
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.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
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.BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
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.InterruptM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
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.InterruptM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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@ -46,7 +46,7 @@ module csrc #(parameter
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input logic InstrValidNotFlushedM, LoadStallD, StoreStallD,
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input logic InstrValidNotFlushedM, LoadStallD, StoreStallD,
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input logic CSRMWriteM, CSRWriteM,
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input logic CSRMWriteM, CSRWriteM,
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input logic BPDirPredWrongM,
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input logic BPDirPredWrongM,
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input logic BTBPredPCWrongM,
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input logic BTAWrongM,
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input logic RASPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic IClassWrongM,
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input logic IClassWrongM,
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input logic BPWrongM, // branch predictor is wrong
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input logic BPWrongM, // branch predictor is wrong
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@ -99,7 +99,7 @@ module csrc #(parameter
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assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
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assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
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assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
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assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
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assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
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assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
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assign CounterEvent[8] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target
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assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target
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assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
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assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
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assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
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assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
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assign CounterEvent[11] = LoadStallM & InstrValidNotFlushedM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[11] = LoadStallM & InstrValidNotFlushedM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
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@ -50,7 +50,7 @@ module privileged (
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input logic ICacheStallF, // I cache stalled
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input logic ICacheStallF, // I cache stalled
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input logic DCacheStallM, // D cache stalled
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input logic DCacheStallM, // D cache stalled
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input logic BPDirPredWrongM, // branch predictor guessed wrong direction
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input logic BPDirPredWrongM, // branch predictor guessed wrong direction
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input logic BTBPredPCWrongM, // branch predictor guessed wrong target
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input logic BTAWrongM, // branch predictor guessed wrong target
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input logic RASPredPCWrongM, // return adddress stack guessed wrong target
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input logic RASPredPCWrongM, // return adddress stack guessed wrong target
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input logic IClassWrongM, // branch predictor guessed wrong instruction class
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input logic IClassWrongM, // branch predictor guessed wrong instruction class
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input logic BPWrongM, // branch predictor is wrong
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input logic BPWrongM, // branch predictor is wrong
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@ -130,7 +130,7 @@ module privileged (
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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.BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
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.sfencevmaM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
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.sfencevmaM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
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.IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
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.NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
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@ -142,7 +142,7 @@ module wallypipelinedcore (
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logic BPWrongE, BPWrongM;
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logic BPWrongE, BPWrongM;
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logic BPDirPredWrongM;
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logic BPDirPredWrongM;
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logic BTBPredPCWrongM;
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logic BTAWrongM;
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logic RASPredPCWrongM;
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logic RASPredPCWrongM;
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logic IClassWrongM;
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logic IClassWrongM;
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logic [3:0] InstrClassM;
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logic [3:0] InstrClassM;
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@ -178,7 +178,7 @@ module wallypipelinedcore (
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// Mem
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// Mem
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.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
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.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
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.InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM,
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.InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM,
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.BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM,
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.BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
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// Faults out
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// Faults out
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.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
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.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
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// mmu management
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// mmu management
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@ -291,7 +291,7 @@ module wallypipelinedcore (
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.RetM, .TrapM, .sfencevmaM, .FenceM, .DCacheStallM, .ICacheStallF,
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.RetM, .TrapM, .sfencevmaM, .FenceM, .DCacheStallM, .ICacheStallF,
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.InstrValidM, .CommittedM, .CommittedF,
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.InstrValidM, .CommittedM, .CommittedF,
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.FRegWriteM, .LoadStallD, .StoreStallD,
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.FRegWriteM, .LoadStallD, .StoreStallD,
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.BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM,
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.BPDirPredWrongM, .BTAWrongM, .BPWrongM,
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.RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
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.RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
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.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
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.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
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