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more TLB name touchups

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This commit is contained in:
David Harris 2021-07-06 18:39:30 -04:00
parent 2e2aa2a972
commit 7d857cf4bd
3 changed files with 7 additions and 17 deletions
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13
wally-pipelined/src/mmu/tlb.sv
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@ -89,10 +89,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
output logic TLBPageFault output logic TLBPageFault
); );
// Store current virtual memory mode (SV32, SV39, SV48, ect...)
//logic [`SVMODE_BITS-1:0] SvMode;
logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex
// Sections of the virtual and physical addresses // Sections of the virtual and physical addresses
@ -113,19 +109,14 @@ module tlb #(parameter TLB_ENTRIES = 8,
tlbcontrol tlbcontrol(.SATP_REGW, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, tlbcontrol tlbcontrol(.SATP_REGW, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
.PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, .EffectivePrivilegeMode, .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault,
.SV39Mode, .Translate); .SV39Mode, .Translate);
// TLB entries are evicted according to the LRU algorithm
tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .ReadLines, .CAMHit, .WriteEnables); tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .ReadLines, .CAMHit, .WriteEnables);
// tlbram #(TLB_ENTRIES) tlbram(.*);
tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .ReadLines, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G);
// tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam(.*);
tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS)
tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G, tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_G,
.ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .ReadLines, .HitPageType, .CAMHit); .ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .ReadLines, .HitPageType, .CAMHit);
tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .ReadLines, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_G);
// Replace segments of the virtual page number with segments of the physical // Replace segments of the virtual page number with segments of the physical
// page number. For 4 KB pages, the entire virtual page number is replaced. // page number. For 4 KB pages, the entire virtual page number is replaced.

7
wally-pipelined/src/mmu/tlbcam.sv
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@ -54,11 +54,10 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
// page number segments. // page number segments.
tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0]( tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
.WriteEnable(WriteEnables), .clk, .reset, .VirtualPageNumber, .ASID, .SV39Mode, .PTE_G, .PageTypeWriteVal, .TLBFlush,
.PageTypeRead, // *** change name to agree .WriteEnable(WriteEnables), .PageTypeRead, .Match(ReadLines));
.Match(ReadLines), // *** change name to agree
.*);
assign CAMHit = |ReadLines & ~TLBFlush; assign CAMHit = |ReadLines & ~TLBFlush;
assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result
endmodule endmodule

2
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -48,7 +48,6 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
output logic TLBMiss, output logic TLBMiss,
output logic TLBHit, output logic TLBHit,
output logic TLBPageFault, output logic TLBPageFault,
output logic [1:0] EffectivePrivilegeMode,
output logic SV39Mode, output logic SV39Mode,
output logic Translate output logic Translate
); );
@ -56,6 +55,7 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
// Sections of the page table entry // Sections of the page table entry
logic [11:0] PageOffset; logic [11:0] PageOffset;
logic [`SVMODE_BITS-1:0] SVMode; logic [`SVMODE_BITS-1:0] SVMode;
logic [1:0] EffectivePrivilegeMode;
logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
logic UpperBitsUnequalPageFault; logic UpperBitsUnequalPageFault;