Merge pull request #442 from kipmacsaigoren/divremsqrt

divremsqrt add synthesis script, fix fp-testbench

src/fpu/divremsqrt/divremsqrtshiftcorrection.sv

@@ -58,7 +58,7 @@ module divremsqrtshiftcorrection import cvw::*;  #(parameter cvw_t P) (
   // correct the shifting error caused by the LZA
   //  - the only possible mantissa for a plus two is all zeroes 
   //      - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
-  mux2 #(P.NORMSHIFTSZ-2) lzacorrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
+  //mux2 #(P.NORMSHIFTSZ-2) lzacorrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
 
   // correct the shifting of the divsqrt caused by producing a result in (2, .5] range
   //    condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
@@ -70,7 +70,8 @@ module divremsqrtshiftcorrection import cvw::*;  #(parameter cvw_t P) (
   // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
   always_comb
     //if(FmaOp)                       Mf = {CorrSumShifted, {P.CORRSHIFTSZ-(3*P.NF+4){1'b0}}};
-    if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
+    //if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
+    if (~DivResSubnorm)  Mf = CorrQmShifted;
     else                       Mf = Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.CORRSHIFTSZ];
     
   // Determine sum's exponent

src/wrappers/wallypipelinedcorewrapper.sv

@@ -1,56 +0,0 @@
-///////////////////////////////////////////
-// wallypipelinedcorewrapper.sv
-//
-// Written: Kevin Kim kekim@hmc.edu 21 August 2023
-// Modified: 
-//
-// Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,
-//          not system verilog.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-//`include "BranchPredictorType.vh"
-`include "config.vh"
-
-import cvw::*;
-
-module wallypipelinedcorewrapper (
-   input  logic                  clk, reset,
-   // Privileged
-   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
-   input  logic [63:0]           MTIME_CLINT, 
-   // Bus Interface
-   input  logic [AHBW-1:0]     HRDATA,
-   input  logic                  HREADY, HRESP,
-   output logic                  HCLK, HRESETn,
-   output logic [PA_BITS-1:0]  HADDR,
-   output logic [AHBW-1:0]     HWDATA,
-   output logic [XLEN/8-1:0]   HWSTRB,
-   output logic                  HWRITE,
-   output logic [2:0]            HSIZE,
-   output logic [2:0]            HBURST,
-   output logic [3:0]            HPROT,
-   output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
-);
-  `include "parameter-defs.vh"
-
-  wallypipelinedcore  #(P) core(.*); 
-
-endmodule

synthDC/scripts/fp-synth.sh

@@ -0,0 +1,207 @@
+#!/bin/bash
+
+# RADIX 2
+setRADIXeq2 () {
+n64=$(grep -n "RADIX" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "RADIX" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/RADIX.*/RADIX = 32\'h2;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/RADIX.*/RADIX = 32\'h2;/" $WALLY/config/rv32gc/config.vh
+}
+
+# RADIX 4
+setRADIXeq4 () {
+n64=$(grep -n "RADIX" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "RADIX" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/RADIX.*/RADIX = 32\'h4;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/RADIX.*/RADIX = 32\'h4;/" $WALLY/config/rv32gc/config.vh
+}
+
+# K = 1
+setKeq1 () {
+n64=$(grep -n "DIVCOPIES" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "DIVCOPIES" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/DIVCOPIES.*/DIVCOPIES = 32\'h1;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/DIVCOPIES.*/DIVCOPIES = 32\'h1;/" $WALLY/config/rv32gc/config.vh
+}
+
+# K = 2
+setKeq2 () {
+n64=$(grep -n "DIVCOPIES" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "DIVCOPIES" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/DIVCOPIES.*/DIVCOPIES = 32\'h2;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/DIVCOPIES.*/DIVCOPIES = 32\'h2;/" $WALLY/config/rv32gc/config.vh
+}
+
+# K = 4
+setKeq4 () {
+n64=$(grep -n "DIVCOPIES" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "DIVCOPIES" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/DIVCOPIES.*/DIVCOPIES = 32\'h4;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/DIVCOPIES.*/DIVCOPIES = 32\'h4;/" $WALLY/config/rv32gc/config.vh
+}
+
+# IDIVBITS = 1
+setIDIVBITSeq1 () {
+n64=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d1;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d1;/" $WALLY/config/rv32gc/config.vh
+}
+
+# IDIVBITS = 2
+setIDIVBITSeq2 () {
+n64=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d2;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d2;/" $WALLY/config/rv32gc/config.vh
+}
+
+# IDIVBITS = 4
+setIDIVBITSeq4 () {
+n64=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d4;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d4;/" $WALLY/config/rv32gc/config.vh
+}
+
+# IDIV ON FPU
+setIDIVeq1 () {
+n64=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 1;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 1;/" $WALLY/config/rv32gc/config.vh
+}
+
+# IDIV NOT ON FPU
+setIDIVeq0 () {
+n64=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
+n32=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
+sed -i "${n64}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 0;/" $WALLY/config/rv64gc/config.vh
+sed -i "${n32}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 0;/" $WALLY/config/rv32gc/config.vh
+}
+
+# Synthesize Integer Divider
+synthIntDiv () {
+make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
+make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
+make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
+make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
+wait
+}
+
+# Synthesize FP Divider Unit
+
+synthFPDiv () {
+make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
+make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
+make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
+make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
+wait
+}
+
+synthAll () {
+    synthIntDiv &
+    wait
+    synthFPDiv &
+    wait
+
+}
+
+
+# Synthesize DivSqrt Preprocessor
+
+synthFPDivsqrtpreproc () {
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
+}
+
+synthFPDiviter () {
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
+make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
+}
+
+# forms title for synthesis
+
+getTitle () {
+RADIX=$(sed -n "157p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
+K=$(sed -n "158p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
+IDIV=$(sed -n "81p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
+IDIVBITS=$(sed -n "80p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
+title="RADIX_${RADIX}_K_${K}_INTDIV_${IDIV}_IDIVBITS_${IDIVBITS}"
+echo $title
+}
+
+# writes area delay of runs to csv
+writeCSV () {
+    echo "design,area,timing" > $WALLY/synthDC/fp-synth.csv
+    # iterate over all files in runs/
+    for FILE in $WALLY/synthDC/runs/*;
+    do
+        design="${FILE##*/}"
+
+        # grab area
+        areaString=($(grep "Total cell area" $FILE/reports/area.rep))
+        area=${areaString[3]}
+
+        # grab timing
+        timingString=($(grep "data arrival time" $FILE/reports/timing.rep))
+        timing=${timingString[3]}
+
+        # write to csv
+        echo $design,$area,$timing >> $WALLY/synthDC/fp-synth.csv
+        
+    done;
+}
+
+go() {
+
+<< comment
+setIDIVeq1
+setKeq1
+setRADIXeq4
+synthFPDiv
+wait
+setKeq2
+setRADIXeq2
+synthFPDiv
+wait
+comment
+setIDIVBITSeq1
+synthIntDiv
+setIDIVBITSeq2
+synthIntDiv
+setIDIVBITSeq4
+synthIntDiv
+<< comment
+setIDIVeq0
+setKeq1
+setRADIXeq4
+synthFPDiv
+wait
+setKeq2
+setRADIXeq2
+synthFPDiv
+comment
+
+
+
+
+}
+
+go2() {
+
+setIDIVeq1
+setRADIXeq4
+setKeq2
+synthFPDiv
+wait
+setRADIXeq2
+setKeq4
+synthFPDiv
+wait
+
+}

synthDC/scripts/synth.tcl

@@ -36,15 +36,13 @@ if {$wrapper ==1 } {
 }
 
 
-# Only for FMA class project; comment out when done
-# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
-
 # Enables name mapping
 if { $saifpower == 1 } {
     saif_map -start
 }
 
 # Verilog files
+#set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv $outputDir/config/*.vh]
 set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
 
 # Set toplevel

synthDC/scripts/wrapperGen.py

@@ -43,7 +43,7 @@ index=0
 
 # string copy logic
 for l in lines:
-    if l.find("module") == 0:
+    if l.lstrip().find("module") == 0:
         lineModuleStart = index
         moduleName = l.split()[1]
         writeBuf = True
@@ -51,7 +51,7 @@ for l in lines:
         continue
     if (writeBuf):
         buf += l
-    if l.find (");") == 0:
+    if l.lstrip().find (");") == 0:
         lineModuleEnd = index
         break
     index+=1

synthDC/wrappers/drsuwrapper.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// drsu.sv
+// drsuwrapper.sv
 //
 // Written: kekim@hmc.edu
 // Modified:19 May 2023
@@ -29,6 +29,7 @@
 
 import cvw::*;
 
+`include "parameter-defs.vh"
 module drsuwrapper (
   input  logic                clk, 
   input  logic                reset, 
@@ -57,7 +58,7 @@ module drsuwrapper(
 );
 //`include "parameter-defs.vh"
 
-drsu #(P) d(.*);
+  drsu #(P) drsucore(.*);
 
 
 endmodule

testbench/testbench-fp.sv

@@ -1128,7 +1128,7 @@ module testbenchfp;
 endmodule
 
 
-module readvectors (
+module readvectors import cvw::*;  #(parameter cvw_t P) (
 		    input logic 	        clk,
 		    input logic [P.FLEN*4+7:0]  TestVector,
 		    input logic [P.FMTBITS-1:0] ModFmt,
@@ -1159,7 +1159,7 @@ module readvectors (
 		    );
 
    localparam Q_LEN = 32'd128;
-  `include "parameter-defs.vh"   
+  //`include "parameter-defs.vh"   
    
    logic 					XEn;
    logic 					YEn;