mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #442 from kipmacsaigoren/divremsqrt
divremsqrt add synthesis script, fix fp-testbench
This commit is contained in:
David Harris
GitHub
commit
7d6076892a
@ -58,7 +58,7 @@ module divremsqrtshiftcorrection import cvw::*; #(parameter cvw_t P) (
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// correct the shifting error caused by the LZA
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// - the only possible mantissa for a plus two is all zeroes
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// - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
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mux2 #(P.NORMSHIFTSZ-2) lzacorrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
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//mux2 #(P.NORMSHIFTSZ-2) lzacorrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
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// correct the shifting of the divsqrt caused by producing a result in (2, .5] range
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// condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
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@ -70,7 +70,8 @@ module divremsqrtshiftcorrection import cvw::*; #(parameter cvw_t P) (
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// if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
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always_comb
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//if(FmaOp) Mf = {CorrSumShifted, {P.CORRSHIFTSZ-(3*P.NF+4){1'b0}}};
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if (DivOp&~DivResSubnorm) Mf = CorrQmShifted;
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//if (DivOp&~DivResSubnorm) Mf = CorrQmShifted;
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if (~DivResSubnorm) Mf = CorrQmShifted;
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else Mf = Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.CORRSHIFTSZ];
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// Determine sum's exponent
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@ -1,56 +0,0 @@
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///////////////////////////////////////////
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// wallypipelinedcorewrapper.sv
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//
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// Written: Kevin Kim kekim@hmc.edu 21 August 2023
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// Modified:
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//
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// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,
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// not system verilog.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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//`include "BranchPredictorType.vh"
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`include "config.vh"
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import cvw::*;
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module wallypipelinedcorewrapper (
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input logic clk, reset,
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// Privileged
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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// Bus Interface
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input logic [AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [PA_BITS-1:0] HADDR,
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output logic [AHBW-1:0] HWDATA,
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output logic [XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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);
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`include "parameter-defs.vh"
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wallypipelinedcore #(P) core(.*);
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endmodule
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207
synthDC/scripts/fp-synth.sh
Executable file
207
synthDC/scripts/fp-synth.sh
Executable file
@ -0,0 +1,207 @@
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#!/bin/bash
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# RADIX 2
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setRADIXeq2 () {
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n64=$(grep -n "RADIX" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "RADIX" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/RADIX.*/RADIX = 32\'h2;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/RADIX.*/RADIX = 32\'h2;/" $WALLY/config/rv32gc/config.vh
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}
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# RADIX 4
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setRADIXeq4 () {
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n64=$(grep -n "RADIX" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "RADIX" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/RADIX.*/RADIX = 32\'h4;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/RADIX.*/RADIX = 32\'h4;/" $WALLY/config/rv32gc/config.vh
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}
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# K = 1
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setKeq1 () {
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n64=$(grep -n "DIVCOPIES" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "DIVCOPIES" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/DIVCOPIES.*/DIVCOPIES = 32\'h1;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/DIVCOPIES.*/DIVCOPIES = 32\'h1;/" $WALLY/config/rv32gc/config.vh
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}
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# K = 2
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setKeq2 () {
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n64=$(grep -n "DIVCOPIES" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "DIVCOPIES" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/DIVCOPIES.*/DIVCOPIES = 32\'h2;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/DIVCOPIES.*/DIVCOPIES = 32\'h2;/" $WALLY/config/rv32gc/config.vh
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}
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# K = 4
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setKeq4 () {
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n64=$(grep -n "DIVCOPIES" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "DIVCOPIES" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/DIVCOPIES.*/DIVCOPIES = 32\'h4;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/DIVCOPIES.*/DIVCOPIES = 32\'h4;/" $WALLY/config/rv32gc/config.vh
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}
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# IDIVBITS = 1
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setIDIVBITSeq1 () {
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n64=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d1;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d1;/" $WALLY/config/rv32gc/config.vh
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}
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# IDIVBITS = 2
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setIDIVBITSeq2 () {
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n64=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d2;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d2;/" $WALLY/config/rv32gc/config.vh
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}
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# IDIVBITS = 4
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setIDIVBITSeq4 () {
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n64=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "IDIV_BITSPERCYCLE =" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d4;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/IDIV_BITSPERCYCLE.*/IDIV_BITSPERCYCLE = 32\'d4;/" $WALLY/config/rv32gc/config.vh
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}
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# IDIV ON FPU
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setIDIVeq1 () {
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n64=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 1;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 1;/" $WALLY/config/rv32gc/config.vh
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}
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# IDIV NOT ON FPU
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setIDIVeq0 () {
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n64=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv64gc/config.vh | cut -d: -f1)
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n32=$(grep -n "IDIV_ON_FPU" $WALLY/config/rv32gc/config.vh | cut -d: -f1)
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sed -i "${n64}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 0;/" $WALLY/config/rv64gc/config.vh
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sed -i "${n32}s/IDIV_ON_FPU.*/IDIV_ON_FPU = 0;/" $WALLY/config/rv32gc/config.vh
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}
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# Synthesize Integer Divider
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synthIntDiv () {
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make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
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make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
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make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
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make -C $WALLY/synthDC synth DESIGN=div TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
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wait
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}
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# Synthesize FP Divider Unit
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synthFPDiv () {
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make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
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make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle) &
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make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
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make -C $WALLY/synthDC synth DESIGN=drsu TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle) &
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wait
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}
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synthAll () {
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synthIntDiv &
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wait
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synthFPDiv &
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wait
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}
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# Synthesize DivSqrt Preprocessor
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synthFPDivsqrtpreproc () {
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtpreproc TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
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}
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synthFPDiviter () {
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv32gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv64gc FREQ=3000 WRAPPER=1 TITLE=$(getTitle)
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv32gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
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make -C $WALLY/synthDC synth DESIGN=fdivsqrtiter TECH=tsmc28 CONFIG=rv64gc FREQ=100 WRAPPER=1 TITLE=$(getTitle)
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}
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# forms title for synthesis
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getTitle () {
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RADIX=$(sed -n "157p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
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K=$(sed -n "158p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
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IDIV=$(sed -n "81p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
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IDIVBITS=$(sed -n "80p" $WALLY/config/rv64gc/config.vh | tail -c 3 | head -c 1)
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title="RADIX_${RADIX}_K_${K}_INTDIV_${IDIV}_IDIVBITS_${IDIVBITS}"
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echo $title
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}
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# writes area delay of runs to csv
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writeCSV () {
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echo "design,area,timing" > $WALLY/synthDC/fp-synth.csv
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# iterate over all files in runs/
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for FILE in $WALLY/synthDC/runs/*;
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do
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design="${FILE##*/}"
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# grab area
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areaString=($(grep "Total cell area" $FILE/reports/area.rep))
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area=${areaString[3]}
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# grab timing
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timingString=($(grep "data arrival time" $FILE/reports/timing.rep))
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timing=${timingString[3]}
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# write to csv
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echo $design,$area,$timing >> $WALLY/synthDC/fp-synth.csv
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done;
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}
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go() {
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<< comment
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setIDIVeq1
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setKeq1
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setRADIXeq4
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synthFPDiv
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wait
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setKeq2
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setRADIXeq2
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synthFPDiv
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wait
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comment
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setIDIVBITSeq1
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synthIntDiv
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setIDIVBITSeq2
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synthIntDiv
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setIDIVBITSeq4
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synthIntDiv
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<< comment
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setIDIVeq0
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setKeq1
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setRADIXeq4
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synthFPDiv
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wait
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setKeq2
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setRADIXeq2
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synthFPDiv
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comment
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}
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go2() {
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setIDIVeq1
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setRADIXeq4
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setKeq2
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synthFPDiv
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wait
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setRADIXeq2
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setKeq4
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synthFPDiv
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wait
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}
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@ -36,15 +36,13 @@ if {$wrapper ==1 } {
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}
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# Only for FMA class project; comment out when done
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# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
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# Enables name mapping
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if { $saifpower == 1 } {
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saif_map -start
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}
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# Verilog files
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#set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv $outputDir/config/*.vh]
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set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
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# Set toplevel
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@ -43,7 +43,7 @@ index=0
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# string copy logic
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for l in lines:
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if l.find("module") == 0:
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if l.lstrip().find("module") == 0:
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lineModuleStart = index
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moduleName = l.split()[1]
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writeBuf = True
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@ -51,7 +51,7 @@ for l in lines:
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continue
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if (writeBuf):
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buf += l
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if l.find (");") == 0:
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if l.lstrip().find (");") == 0:
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lineModuleEnd = index
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break
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index+=1
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// drsu.sv
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// drsuwrapper.sv
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//
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// Written: kekim@hmc.edu
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// Modified:19 May 2023
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@ -29,7 +29,8 @@
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import cvw::*;
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module drsuwrapper(
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`include "parameter-defs.vh"
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module drsuwrapper (
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input logic clk,
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input logic reset,
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input logic [1:0] FmtE,
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@ -57,7 +58,7 @@ module drsuwrapper(
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);
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//`include "parameter-defs.vh"
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drsu #(P) d(.*);
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drsu #(P) drsucore(.*);
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endmodule
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@ -1128,7 +1128,7 @@ module testbenchfp;
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endmodule
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module readvectors (
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module readvectors import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic [P.FLEN*4+7:0] TestVector,
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input logic [P.FMTBITS-1:0] ModFmt,
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@ -1159,7 +1159,7 @@ module readvectors (
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);
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localparam Q_LEN = 32'd128;
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`include "parameter-defs.vh"
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//`include "parameter-defs.vh"
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logic XEn;
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logic YEn;
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