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Merge branch 'openhwgroup:main' into main

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Rose Thompson 2024-12-23 11:01:34 -06:00 committed by GitHub
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42 changed files with 1620 additions and 349 deletions
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2
.gitignore vendored
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@ -12,6 +12,7 @@
*.map
*.elf*
*.list
*.memfile
# General directories to ignore
.vscode/
@ -33,6 +34,7 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv
tests/custom/*/*/
tests/custom/*/*/*.memfile
sim/tests/riscvdv
testbench/trek_files/uvm_output
# Linux
linux/buildroot

5
Makefile
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@ -39,6 +39,11 @@ coverage:
cvw-arch-verif:
$(MAKE) -C ${WALLY}/addins/cvw-arch-verif
# Requires a license for the Breker tool. See tests/breker/README.md for details
breker:
$(MAKE) -C ${WALLY}/testbench/trek_files
$(MAKE) -C ${WALLY}/tests/breker
clean:
$(MAKE) clean -C sim
$(MAKE) clean -C ${WALLY}/tests/fp

46
README.md
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@ -59,7 +59,19 @@ Then fork and clone the repo, source setup, make the tests and run regression
fi
```
9. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while.
9. Try compiling the HelloWally program and simulating it on the SystemVerilog with Verilator and on the Spike simulator.
```
$ cd examples/C/hello
$ make
$ wsim --sim verilator rv64gc --elf hello
Hello Wally!
0 1 2 3 4 5 6 7 8 9
$ spike hello
Hello Wally!
0 1 2 3 4 5 6 7 8 9
```
10. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while.
```bash
$ make --jobs
@ -215,26 +227,28 @@ This utility will take up approximately 100 GB on your hard drive. You can also
wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
The general syntax is
`wsim <config> <suite or elf file or directory> [--options]`
`wsim <config> <suite or elf file> [--options]`
Parameters and options:
```
-h, --help show this help message and exit
--elf ELF, -e ELF ELF File name; use if name does not end in .elf
--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator
--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench
--gui, -g Simulate with GUI
--coverage, -c Code & Functional Coverage
--fcov, -f Code & Functional Coverage
--ccov, -c Code Coverage
--fcov, -f Functional Coverage with cvw-arch-verif, implies lockstep
--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs
--params PARAMS, -p PARAMS Optional top-level parameter overrides of the form param=value
--define DEFINE, -d DEFINE Optional define macros passed to simulator
--vcd, -v Generate testbench.vcd
--lockstep, -l Run ImperasDV lock, step, and compare.
--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging.
--covlog COVLOG, -d COVLOG Log coverage after n instructions.
--elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension
--lockstepverbose, -lv Run ImperasDV lock, step, and compare with tracing enabled
--rvvi, -r Simulate rvvi hardware interface and ethernet.
```
Run basic test with questa
Run basic test with Questa
```bash
wsim rv64gc arch64i
@ -246,26 +260,26 @@ Run Questa with gui
wsim rv64gc wally64priv --gui
```
Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf.
Run basic test with Verilator
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
wsim rv32i arch32i --sim verilator
```
Run lockstep against ImperasDV with a single elf file. Compute coverage.
Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf.
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage
wsim rv64gc $WALLY/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
```
Run lockstep against ImperasDV with directory file.
Run lockstep against ImperasDV with a single elf file. Collect functional coverage.
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep
wsim rv64gc $WALLY/addins/cvw-arch-verif/tests/rv64/Zicsr/WALLY-COV-ALL.elf --fcov
```
Run lockstep against ImperasDV with directory file and specify specific extension.
Run Linux boot simulation in lock step between Wally and ImperasDV
```bash
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf
wsim buildroot buildroot --args +INSTR_LIMIT=600000000 --lockstep
```

2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit b37edba7f625cc3bc2b161d03bc1cd90df0fa2e3
Subproject commit efd70ce71a352eb8c4ca3d3b63d06a7b076078cb

16
bin/regression-wally
View File

@ -291,7 +291,7 @@ def addTests(tests, sim):
configs.append(tc)
def addTestsByDir(dir, config, sim, lockstepMode=0):
def addTestsByDir(dir, config, sim, lockstepMode=0, brekerMode=0):
if os.path.isdir(dir):
sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
if coverStr == "--fcov": # use --fcov in place of --lockstep
@ -312,6 +312,10 @@ def addTestsByDir(dir, config, sim, lockstepMode=0):
cmdPrefix="wsim --lockstep --sim " + sim + " " + config
gs="Mismatches : 0"
fileEnd = ".elf"
elif brekerMode:
cmdPrefix="wsim --sim " + sim + " " + config
gs="# trek: info: summary: Test PASSED"
fileEnd = ".elf"
else:
cmdPrefix="wsim --sim " + sim + " " + config
gs="Single Elf file tests are not signatured verified."
@ -397,6 +401,7 @@ parser.add_argument("--nightly", help="Run large nightly regression", action="st
parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details
parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
args = parser.parse_args()
@ -441,7 +446,8 @@ elif (args.fcov): # run tests in lockstep in functional coverage mode
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim)
addTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim)
elif (args.breker):
addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", brekerMode=1)
else:
for sim in sims:
if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one
@ -452,9 +458,9 @@ else:
# run derivative configurations and lockstep tests in nightly regression
if (args.nightly):
addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 1)
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 1)
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 1)
addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, lockstepMode=1)
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, lockstepMode=1)
addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, lockstepMode=1)
addTests(derivconfigtests, defaultsim)
# addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.

22
bin/wally-distro-check.sh
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@ -76,10 +76,28 @@ if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then
elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then
export FAMILY=ubuntu
if [ "$ID" != ubuntu ]; then
printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script has only been tested on standard Ubuntu. Your distro " \
printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script is only tested on standard Ubuntu. Your distro " \
"is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues."
# Ubuntu derivates may use different version numbers. Attempt to derive version from Ubuntu codename
case "$UBUNTU_CODENAME" in
noble)
export UBUNTU_VERSION=24
;;
jammy)
export UBUNTU_VERSION=22
;;
focal)
export UBUNTU_VERSION=20
;;
*)
printf "${FAIL_COLOR}%s\n${ENDC}" "Unable to determine which base Ubuntu version you are using."
exit 1
;;
esac
echo "Detected Ubuntu derivative baesd on Ubuntu $UBUNTU_VERSION.04."
else
export UBUNTU_VERSION="${VERSION_ID:0:2}"
fi
export UBUNTU_VERSION="${VERSION_ID:0:2}"
if (( UBUNTU_VERSION < 20 )); then
printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION."
exit 1

181
bin/wsim
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@ -13,6 +13,7 @@
import argparse
import os
import sys
# Global variable
WALLY = os.environ.get('WALLY')
@ -29,152 +30,160 @@ def parseArgs():
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
return parser.parse_args()
def validateArgs(args):
if not args.testsuite and not args.elf:
print("Error: Missing test suite or ELF file")
exit(1)
if args.lockstep and not args.testsuite.endswith('.elf') and args.testsuite != "buildroot" :
print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
exit(1)
elif (args.gui or args.ccov or args.fcov or args.lockstep or args.lockstepverbose) and args.sim not in ["questa", "vcs"]:
sys.exit(1)
if any([args.lockstep, args.lockstepverbose, args.fcov]) and not (args.testsuite.endswith('.elf') or args.elf) and args.testsuite != "buildroot":
print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep or fcov. Must run a single elf or buildroot.")
sys.exit(1)
elif any([args.gui, args.ccov, args.fcov, args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]:
print("Option only supported for Questa and VCS")
exit(1)
sys.exit(1)
elif (args.tb == "testbench_fp" and args.sim != "questa"):
print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench")
exit(1)
sys.exit(1)
elif (args.config == "breker" and args.sim != "questa"):
print("Error: Breker tests currently only supported by Questa")
sys.exit(1)
def elfFileCheck(args):
ElfFile = ""
if os.path.isfile(args.elf):
ElfFile = f"+ElfFile={os.path.abspath(args.elf)}"
elif args.elf != "":
ElfFile = os.path.abspath(args.elf)
elif args.elf:
print(f"ELF file not found: {args.elf}")
exit(1)
sys.exit(1)
elif args.testsuite.endswith('.elf'): # No --elf argument; check if testsuite has a .elf extension and use that instead
if os.path.isfile(args.testsuite):
ElfFile = f"+ElfFile={os.path.abspath(args.testsuite)}"
ElfFile = os.path.abspath(args.testsuite)
# extract the elf name from the path to be the test suite
fields = args.testsuite.rsplit('/', 3)
# if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
if (len(fields) > 3):
if (fields[2] == "ref"):
if "breker" in args.testsuite:
args.testsuite = fields[-1]
elif len(fields) > 3:
if fields[2] == "ref":
args.testsuite = f"{fields[1]}_{fields[3]}"
else:
args.testsuite = f"{fields[2]}_{fields[3]}"
elif ('/' in args.testsuite):
elif '/' in args.testsuite:
args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present
else:
print(f"ELF file not found: {args.testsuite}")
exit(1)
sys.exit(1)
return ElfFile
def prepSim(args, ElfFile):
flags = ""
prefix = ""
paramsList = []
argsList = []
flagsList = []
defineList = []
if args.vcd:
args.args += " -DMAKEVCD=1"
paramsList.append("MAKE_VCD=1")
if args.rvvi:
args.params += " RVVI_SYNTH_SUPPORTED=1 "
paramsList.append("RVVI_SYNTH_SUPPORTED=1")
if args.tb == "testbench_fp":
args.params += f' TEST="{args.testsuite}" '
if ElfFile != "":
args.args += f" {ElfFile}"
paramsList.append(f'TEST="{args.testsuite}"')
if ElfFile:
argsList.append(f"+ElfFile={ElfFile}")
if args.gui and args.tb == "testbench":
paramsList.append("DEBUG=1")
if args.ccov:
flags += " --ccov"
flagsList.append("--ccov")
if args.fcov:
flags += " --fcov"
prefix, suffix = lockstepSetup(args)
flags += suffix
flagsList.append("--fcov")
defineList.extend(["+define+INCLUDE_TRACE2COV", "+define+IDV_INCLUDE_TRACE2COV", "+define+COVER_BASE_RV32I"]) # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but does not affect tests
argsList.extend(["+TRACE2COV_ENABLE=1", "+IDV_TRACE2COV=1"])
if args.gui:
flagsList.append("--gui")
if args.lockstep or args.lockstepverbose:
flagsList.append("--lockstep")
if args.lockstep or args.lockstepverbose or args.fcov:
prefix = lockstepSetup(args)
defineList.append("+define+USE_IMPERAS_DV")
if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details
ElfFileNoExtension = os.path.splitext(ElfFile)[0]
flagsList.append("--breker")
defineList.append("+define+USE_TREK_DV")
argsList.append(f"+TREK_TBX_FILE={ElfFileNoExtension}.tbx")
# Combine into a single string
args.args += " ".join(argsList)
args.params += " ".join(paramsList)
args.define += " ".join(defineList)
flags = " ".join(flagsList)
return flags, prefix
def lockstepSetup(args):
prefix = ""
suffix = ""
ImperasPlusArgs = ""
imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic")
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath):
print("Error: imperas.ic not found")
sys.exit(1)
prefix = f"IMPERAS_TOOLS={imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
return prefix
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
if (args.lockstep or args.lockstepverbose or args.fcov):
imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
if not os.path.isfile(imperasicPath):
print("Error: imperas.ic not found")
exit(1)
prefix += f"IMPERAS_TOOLS={imperasicPath}"
if (args.lockstep or args.lockstepverbose):
if(args.locksteplog != 0): ImperasPlusArgs = f" +IDV_TRACE2LOG={EnableLog} +IDV_TRACE2LOG_AFTER={args.locksteplog}"
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0"
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = f" +IDV_TRACE2COV={EnableLog} +TRACE2LOG_AFTER={args.covlog} +TRACE2COV_ENABLE={CovEnableStr}"
else:
suffix = "--lockstep"
if(args.lockstepverbose):
prefix += f":{WALLY}/sim/imperas-verbose.ic"
args.args += ImperasPlusArgs
return prefix, suffix
def createDirs(args):
def createDirs(sim):
for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
os.makedirs(os.path.join(WALLY, "sim", args.sim, d), exist_ok=True)
os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True)
def runSim(args, flags, prefix):
if (args.sim == "questa"):
if args.sim == "questa":
runQuesta(args, flags, prefix)
elif (args.sim == "verilator"):
runVerilator(args, flags, prefix)
elif (args.sim == "vcs"):
elif args.sim == "verilator":
runVerilator(args)
elif args.sim == "vcs":
runVCS(args, flags, prefix)
def runQuesta(args, flags, prefix):
# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
prefix = "MTI_VCO_MODE=64 " + prefix
if (args.gui) and (args.tb == "testbench"):
args.params += "DEBUG=1"
if (args.args != ""):
args.args = f' --args \\"{args.args}\\"'
if (args.params != ""):
args.params = f' --params \\"{args.params}\\"'
if args.args:
args.args = fr'--args \"{args.args}\"'
if args.params:
args.params = fr'--params \"{args.params}\"'
if args.define:
args.define = fr'--define \"{args.define}\"'
# Questa cannot accept more than 9 arguments. fcov implies lockstep
cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {flags}"
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
cmd = f'cd $WALLY/sim/questa; {prefix} vsim -do "{cmd} +acc"'
else: # launch Questa in batch mode
cmd = f'cd $WALLY/sim/questa; {prefix} vsim -c -do "{cmd}"'
cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}"
cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
print(f"Running Questa with command: {cmd}")
os.system(cmd)
def runVerilator(args, flags, prefix):
def runVerilator(args):
print(f"Running Verilator on {args.config} {args.testsuite}")
os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}"')
os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}" DEFINE_ARGS="{args.define}"')
def runVCS(args, flags, prefix):
print(f"Running VCS on {args.config} {args.testsuite}")
# if (args.gui):
# flags += " --gui"
if (args.args != ""):
args.args = f' --args "{args.args}" '
if (args.params != ""):
args.params = f' --params "{args.params}" '
cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {flags}"
if args.args:
args.args = f'--args "{args.args}"'
if args.params:
args.params = f'--params "{args.params}"'
if args.define:
args.define = f'--define "{args.define}"'
cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {args.define} {flags}"
print(cmd)
os.system(cmd)
if __name__ == "__main__":
args = parseArgs()
def main(args):
validateArgs(args)
print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}'")
print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}' define='{args.define}'")
ElfFile = elfFileCheck(args)
flags, prefix = prepSim(args, ElfFile)
createDirs(args)
exit(runSim(args, flags, prefix))
createDirs(args.sim)
sys.exit(runSim(args, flags, prefix))
if __name__ == "__main__":
args = parseArgs()
main(args)

7
config/derivlist.txt
View File

@ -1432,5 +1432,8 @@ UART_SUPPORTED 0
PLIC_SUPPORTED 0
SPI_SUPPORTED 0
# Breker tests require a different memory configuration
# See tests/breker/README.md for details on the testsuite
derive breker rv64gc
EXT_MEM_SUPPORTED 1
EXT_MEM_BASE 64'h90000000

6
config/rv32e/config.vh
View File

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;

6
config/rv32gc/config.vh
View File

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;

52
config/rv32gc/coverage.svh
View File

@ -13,27 +13,37 @@
`define CLINT_BASE 64'h02000000
// Unprivileged extensions
`include "RV32I_coverage.svh"
`include "RV32M_coverage.svh"
`include "RV32F_coverage.svh"
`include "RV32D_coverage.svh"
`include "RV32Zba_coverage.svh"
`include "RV32Zbb_coverage.svh"
`include "RV32Zbc_coverage.svh"
`include "RV32Zbs_coverage.svh"
`include "RV32ZfaF_coverage.svh"
`include "RV32ZfaD_coverage.svh"
`include "RV32ZfaZfh_coverage.svh"
`include "RV32ZfhD_coverage.svh"
`include "RV32Zfh_coverage.svh"
`include "RV32Zicond_coverage.svh"
`include "RV32Zca_coverage.svh"
`include "RV32Zcb_coverage.svh"
`include "RV32ZcbM_coverage.svh"
`include "RV32ZcbZbb_coverage.svh"
`include "RV32Zcf_coverage.svh"
`include "RV32Zcd_coverage.svh"
`include "RV32Zicsr_coverage.svh"
`include "I_coverage.svh"
`include "M_coverage.svh"
`include "F_coverage.svh"
`include "D_coverage.svh"
`include "Zba_coverage.svh"
`include "Zbb_coverage.svh"
`include "Zbc_coverage.svh"
`include "Zbs_coverage.svh"
`include "ZfaF_coverage.svh"
`include "ZfaD_coverage.svh"
`include "ZfaZfh_coverage.svh"
`include "Zfh_coverage.svh"
`include "ZfhD_coverage.svh"
// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled
`include "Zfhmin_coverage.svh"
`include "Zicond_coverage.svh"
`include "Zca_coverage.svh"
`include "Zcb_coverage.svh"
`include "ZcbM_coverage.svh"
`include "ZcbZbb_coverage.svh"
`include "Zcf_coverage.svh"
`include "Zcd_coverage.svh"
`include "Zicsr_coverage.svh"
`include "Zbkb_coverage.svh"
`include "Zbkc_coverage.svh"
`include "Zbkx_coverage.svh"
`include "Zknd_coverage.svh"
`include "Zkne_coverage.svh"
`include "Zknh_coverage.svh"
`include "Zaamo_coverage.svh"
`include "Zalrsc_coverage.svh"
// Privileged extensions
`include "ZicsrM_coverage.svh"

6
config/rv32i/config.vh
View File

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 0;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;

6
config/rv32imc/config.vh
View File

@ -31,7 +31,7 @@
localparam XLEN = 32'd32;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 0;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;

6
config/rv64gc/config.vh
View File

@ -31,7 +31,7 @@
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 1;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;

52
config/rv64gc/coverage.svh
View File

@ -13,27 +13,37 @@
`define CLINT_BASE 64'h02000000
// Unprivileged extensions
`include "RV64I_coverage.svh"
`include "RV64M_coverage.svh"
`include "RV64F_coverage.svh"
`include "RV64D_coverage.svh"
`include "RV64Zba_coverage.svh"
`include "RV64Zbb_coverage.svh"
`include "RV64Zbc_coverage.svh"
`include "RV64Zbs_coverage.svh"
`include "RV64ZfaF_coverage.svh"
`include "RV64ZfaD_coverage.svh"
`include "RV64ZfaZfh_coverage.svh"
`include "RV64ZfhD_coverage.svh"
`include "RV64Zfh_coverage.svh"
`include "RV64Zicond_coverage.svh"
`include "RV64Zca_coverage.svh"
`include "RV64Zcb_coverage.svh"
`include "RV64ZcbM_coverage.svh"
`include "RV64ZcbZbb_coverage.svh"
`include "RV64ZcbZba_coverage.svh"
`include "RV64Zcd_coverage.svh"
`include "RV64Zicsr_coverage.svh"
`include "I_coverage.svh"
`include "M_coverage.svh"
`include "F_coverage.svh"
`include "D_coverage.svh"
`include "Zba_coverage.svh"
`include "Zbb_coverage.svh"
`include "Zbc_coverage.svh"
`include "Zbs_coverage.svh"
`include "ZfaF_coverage.svh"
`include "ZfaD_coverage.svh"
`include "ZfaZfh_coverage.svh"
`include "ZfhD_coverage.svh"
`include "Zfh_coverage.svh"
// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled
`include "Zfhmin_coverage.svh"
`include "Zicond_coverage.svh"
`include "Zca_coverage.svh"
`include "Zcb_coverage.svh"
`include "ZcbM_coverage.svh"
`include "ZcbZbb_coverage.svh"
`include "ZcbZba_coverage.svh"
`include "Zcd_coverage.svh"
`include "Zicsr_coverage.svh"
`include "Zbkb_coverage.svh"
`include "Zbkc_coverage.svh"
`include "Zbkx_coverage.svh"
`include "Zknd_coverage.svh"
`include "Zkne_coverage.svh"
`include "Zknh_coverage.svh"
`include "Zaamo_coverage.svh"
`include "Zalrsc_coverage.svh"
// Privileged extensions
`include "RV64VM_coverage.svh"

6
config/rv64i/config.vh
View File

@ -31,7 +31,7 @@
localparam XLEN = 32'd64;
// IEEE 754 compliance
localparam IEEE754 = 0;
localparam logic IEEE754 = 0;
// RISC-V configuration per specification
// Base instruction set (defaults to I if E is not supported)
@ -156,11 +156,11 @@ localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;
localparam logic BOOTROM_SUPPORTED = 0;
localparam logic [63:0] BOOTROM_BASE = 64'h00001000;
localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam logic BOOTROM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_SUPPORTED = 0;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam logic UNCORE_RAM_PRELOAD = 1'b0;
localparam logic EXT_MEM_SUPPORTED = 0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;
localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;

86
sim/questa/wally.do
View File

@ -3,12 +3,12 @@
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021
# James Stine, 2008; David Harris 2021; Jordan Carlin 2024
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [+acc] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"]
# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] [--define "any number of +define+VAR=VAL"]
# Example: do wally.do rv64gc arch64i testbench
# Use this wally.do file to run this example.
@ -40,7 +40,6 @@ set TESTSUITE ${2}
set TESTBENCH ${3}
set WKDIR wkdir/${CFG}_${TESTSUITE}
set WALLY $::env(WALLY)
set IMPERAS_HOME $::env(IMPERAS_HOME)
set CONFIG ${WALLY}/config
set SRC ${WALLY}/src
set TB ${WALLY}/testbench
@ -55,6 +54,7 @@ vlib ${WKDIR}
set PlusArgs ""
set ParamArgs ""
set ExpandedParamArgs {}
set DefineArgs ""
set ccov 0
set CoverageVoptArg ""
@ -62,11 +62,14 @@ set CoverageVsimArg ""
set FunctCoverage 0
set FCvlog ""
set FCvopt ""
set FCdefineCOVER_EXTS {}
set breker 0
set brekervlog ""
set brekervopt ""
set lockstep 0
set lockstepvlog ""
set SVLib ""
set GUI 0
@ -74,24 +77,27 @@ set accFlag ""
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
# it takes on different values if vsim and the do file are called from the command line or
# if the do file is called from questa sim directly. This chunk of code uses the $4 through $n
# variables and compacts into a single list for passing to vopt.
set from 4
set step 1
# if the do file is called from questa sim directly. This chunk of code uses the $n variables
# and compacts them into a single list for passing to vopt. Shift is used to move the arguments
# through the list.
set lst {}
echo "number of args = $argc"
for {set i 0} true {incr i} {
set x [expr {$i*$step + $from}]
if {$x > $argc} break
set arg [expr "$$x"]
lappend lst $arg
# Shift off the first three arguments (config, testcases, testbench)
shift
shift
shift
# Copy the remaining arguments into a list
while {$argc > 0} {
lappend lst [expr "\$1"]
shift
}
echo "number of args = $argc"
echo "lst = $lst"
# if +acc found set flag and remove from list
if {[lcheck lst "+acc"]} {
if {[lcheck lst "--gui"]} {
set GUI 1
set accFlag "+acc"
}
@ -106,25 +112,32 @@ if {[lcheck lst "--ccov"]} {
# if --fcov found set flag and remove from list
if {[lcheck lst "--fcov"]} {
set FunctCoverage 1
# COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests
set FCvlog "+define+INCLUDE_TRACE2COV \
+define+IDV_INCLUDE_TRACE2COV \
+define+COVER_BASE_RV32I \
+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source \
"
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
set FCvlog "+incdir+${FCRVVI}/unpriv \
+incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/rv32_priv \
+incdir+${FCRVVI}/common +incdir+${FCRVVI} \
+incdir+$env(WALLY)/addins/cvw-arch-verif/riscvISACOV/source"
}
# if --lockstep or --fcov found set flag and remove from list
if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} {
set IMPERAS_HOME $::env(IMPERAS_HOME)
set lockstep 1
set lockstepvlog "+define+USE_IMPERAS_DV \
+incdir+${IMPERAS_HOME}/ImpPublic/include/host \
set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \
+incdir+${IMPERAS_HOME}/ImpProprietary/include/host \
${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \
${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv"
set SVLib "-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model "
}
# if --breker found set flag and remove from list
# Requires a license for the breker tool. See tests/breker/README.md for details
if {[lcheck lst "--breker"]} {
set breker 1
set BREKER_HOME $::env(BREKER_HOME)
set brekervlog "+incdir+${WALLY}/testbench/trek_files \
${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv"
set brekervopt "${WKDIR}.trek_uvm"
append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek "
}
# Set PlusArgs passed using the --args flag
@ -145,30 +158,39 @@ if {$ParamArgsIndex >= 0} {
set lst [lreplace $lst $ParamArgsIndex [expr {$ParamArgsIndex + 1}]]
}
# Set +define macros passed using the --define flag
set DefineArgsIndex [lsearch -exact $lst "--define"]
if {$DefineArgsIndex >= 0} {
set DefineArgs [lindex $lst [expr {$DefineArgsIndex + 1}]]
set lst [lreplace $lst $DefineArgsIndex [expr {$DefineArgsIndex + 1}]]
}
# Debug print statements
if {$DEBUG > 0} {
echo "GUI = $GUI"
echo "ccov = $ccov"
echo "lockstep = $lockstep"
echo "FunctCoverage = $FunctCoverage"
echo "Breker = $breker"
echo "remaining list = $lst"
echo "Extra +args = $PlusArgs"
echo "Extra -args = $ExpandedParamArgs"
echo "Extra params = $ExpandedParamArgs"
echo "Extra defines = $DefineArgs"
}
# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/rv32_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared"
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg}
vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg}
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} {*}${FCvopt} -suppress 3829 ${CoverageVsimArg}
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg}
# power add generates the logging necessary for saif generation.
# power add -r /dut/core/*

165
sim/vcs/run_vcs
View File

@ -2,97 +2,118 @@
# run_vcs
# David_Harris@hmc.edu 2 July 2024
# Modified Jordan Carlin jcarlin@hmc.edu Dec 9 2024
# Run VCS on a given file, passing appropriate flags
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
import argparse
import os
import subprocess
import sys
# Global variables
WALLY = os.environ.get('WALLY')
simdir = f"{WALLY}/sim/vcs"
cfgdir = f"{WALLY}/config"
srcdir = f"{WALLY}/src"
tbdir = f"{WALLY}/testbench"
logdir = f"{simdir}/logs"
# run a Linux command and return the result as a string in a form that VCS can use
def runfindcmd(cmd):
# print("Executing: " + str(cmd) )
res = subprocess.check_output(cmd, shell=True)
def runFindCommand(cmd):
res = subprocess.check_output(cmd, shell=True, )
res = str(res)
res = res.replace("\\n", " ") # replace newline with space
res = res.replace("\'", "") # strip off quotation marks
res = res[1:] # strip off leading b from byte string
return res
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
# GUI not yet implemented
#parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
args = parser.parse_args()
print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " lockstep=" + str(args.lockstep) + " args='" + args.args + "' params='" + args.params + "'")
def parseArgs():
parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file")
parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
#parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") # GUI not yet implemented
return parser.parse_args()
cfgdir = "$WALLY/config"
srcdir = "$WALLY/src"
tbdir = "$WALLY/testbench"
wkdir = "$WALLY/sim/vcs/wkdir/" + args.config + "_" + args.testsuite
covdir = "$WALLY/sim/vcs/cov/" + args.config + "_" + args.testsuite
logdir = "$WALLY/sim/vcs/logs"
def createDirs(args):
wkdir = f"{simdir}/wkdir/{args.config}_{args.testsuite}"
covdir = f"{simdir}/cov/{args.config}_{args.testsuite}"
os.makedirs(wkdir, exist_ok=True)
os.makedirs(covdir, exist_ok=True)
os.makedirs(logdir, exist_ok=True)
return wkdir, covdir
os.system("mkdir -p " + wkdir)
os.system("mkdir -p " + covdir)
os.system("mkdir -p " + logdir)
def generateFileList():
rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"'
rtlsrc_files = runFindCommand(rtlsrc_cmd)
tbcommon_cmd = f'find {tbdir}/common -name "*.sv"'
tbcommon_files = runFindCommand(tbcommon_cmd)
tb_file = f'{tbdir}/{args.tb}.sv'
return f"{tb_file} {rtlsrc_files} {tbcommon_files}"
# Find RTL source files
rtlsrc_cmd = "find " + srcdir + ' -name "*.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x64.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x32.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_2048x64.sv"'
rtlsrc_files = runfindcmd(rtlsrc_cmd)
tbcommon_cmd = 'find ' + tbdir+'/common -name "*.sv" ! -path "' + tbdir+'/common/wallyTracer.sv"'
tbcommon_files = runfindcmd(tbcommon_cmd)
tb_file = tbdir + "/" + args.tb + ".sv"
RTL_FILES = tb_file + ' ' + str(rtlsrc_files) + ' ' + str(tbcommon_files)
def processArgs(wkdir, args):
compileOptions = []
simvOptions = []
if args.lockstep:
compileOptions.extend(["+incdir+$IMPERAS_HOME/ImpPublic/include/host",
"+incdir+$IMPERAS_HOME/ImpProprietary/include/host",
"$IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv",
"$IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv"])
simvOptions.append("-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model")
if args.ccov:
compileOptions.extend(["-cm line+cond+branch+fsm+tgl", f"-cm_log {wkdir}/coverage.log", f"-cm_dir {wkdir}/coverage"])
if args.params:
compileOptions.append(setupParamOverrides(wkdir, args))
if args.define:
compileOptions.append(args.define)
# if args.gui:
# compileOptions.append("-debug_access+all+reverse -kdb +vcs+vcdpluson")
compileOptions = " ".join(compileOptions)
simvOptions = " ".join(simvOptions)
return compileOptions, simvOptions
# Include directories
INCLUDE_PATH="+incdir+" + cfgdir + "/" + args.config + " +incdir+" + cfgdir + "/deriv/" + args.config + " +incdir+" + cfgdir + "/shared +incdir+$WALLY/tests +incdir+" + tbdir + " +incdir+" + srcdir
def setupParamOverrides(wkdir, args):
paramOverrideFile = os.path.join(wkdir, "param_overrides.txt")
with open(paramOverrideFile, "w") as f:
for param in args.params.split():
[param, value] = param.split("=")
if fr"\'" in value: # for bit values
value = value.replace(fr"\'", "'")
else: # for strings
value = f'"{value}"'
f.write(f"assign {value} {args.tb}/{param}\n")
return f" -parameters {wkdir}/param_overrides.txt "
# lockstep mode
if (args.lockstep):
LOCKSTEP_OPTIONS = " +define+USE_IMPERAS_DV +incdir+$IMPERAS_HOME/ImpPublic/include/host +incdir+$IMPERAS_HOME/ImpProprietary/include/host $IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv $IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv " + tbdir + "/common/wallyTracer.sv"
LOCKSTEP_SIMV = "-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
else:
LOCKSTEP_OPTIONS = ""
LOCKSTEP_SIMV = ""
def setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args):
includePath=f"+incdir+{cfgdir}/{args.config} +incdir+{cfgdir}/deriv/{args.config} +incdir+{cfgdir}/shared +incdir+$WALLY/tests +incdir+{tbdir} +incdir+{srcdir}"
vcsStandardFlags = "+lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn"
vcsCMD = f"vcs {vcsStandardFlags} -top {args.tb} {compileOptions} -Mdir={wkdir} {includePath} {srcdir}/cvw.sv {rtlFiles} -o {wkdir}/sim_out -work {wkdir} -Mlib={wkdir} -l {logdir}/{args.config}_{args.testsuite}.log"
simvCMD = f"{wkdir}/sim_out +TEST={args.testsuite} {args.args} -no_save {simvOptions}"
return vcsCMD, simvCMD
# coverage mode
if (args.coverage):
COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage"
else:
COV_OPTIONS = ""
def runVCS(wkdir, vcsCMD, simvCMD):
print(f"Executing: {vcsCMD}")
subprocess.run(vcsCMD, shell=True)
subprocess.run(simvCMD, shell=True)
if (args.ccov):
COV_RUN = f"urg -dir {wkdir}/coverage.vdb -format text -report IndividualCovReport/{args.config}_{args.testsuite}"
subprocess.run(COV_RUN, shell=True)
# Write parameter overrides to a file
f = open(os.path.expandvars(wkdir) + "/param_overrides.txt", "w")
for param in args.params.split():
[param, value] = param.split("=")
if "\\'" in value: # for bit values
value = value.replace("\\'", "'")
else: # for strings
value = "\"" + value + "\""
# print("param=" + param + " value=" + value)
f.write("assign " + value + " " + args.tb + "/" + param + "\n")
f.close()
PARAM_OVERRIDES=" -parameters " + wkdir + "/param_overrides.txt "
def main(args):
print(f"run_vcs Config={args.config} tests={args.testsuite} lockstep={args.lockstep} args='{args.args}' params='{args.params}' define='{args.define}'")
wkdir, covdir = createDirs(args)
rtlFiles = generateFileList()
compileOptions, simvOptions = processArgs(wkdir, args)
vcsCMD, simvCMD = setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args)
runVCS(wkdir, vcsCMD, simvCMD)
# Simulation commands
OUTPUT="sim_out"
VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + "-top " + args.tb + PARAM_OVERRIDES + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson
VCS = VCS_CMD + " -Mdir=" + wkdir + " " + srcdir + "/cvw.sv " + LOCKSTEP_OPTIONS + " " + COV_OPTIONS + " " + RTL_FILES + " -o " + wkdir + "/" + OUTPUT + " -work " + wkdir + " -Mlib=" + wkdir + " -l " + logdir + "/" + args.config + "_" + args.testsuite + ".log"
SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.args + " -no_save " + LOCKSTEP_SIMV
# Run simulation
print("Executing: " + str(VCS) )
subprocess.run(VCS, shell=True)
subprocess.run(SIMV_CMD, shell=True)
if (args.coverage):
COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite
subprocess.run(COV_RUN, shell=True)
if __name__ == "__main__":
args = parseArgs()
sys.exit(main(args))

19
sim/verilator/Makefile
View File

@ -13,16 +13,15 @@ VERILATOR_DIR=${WALLY}/sim/verilator
SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
PLUS_ARGS=
PARAM_ARGS=
DEFINE_ARGS=
EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS))
WALLYCONF?=rv64gc
TEST?=arch64i
TESTBENCH?=testbench
TESTBENCH?=testbench
# constants
# assume WALLY variable is correctly configured in the shell environment
WORKING_DIR=${WALLY}/sim/verilator
TARGET=$(WORKING_DIR)/target
# INCLUDE_PATH are pathes that Verilator should search for files it needs
INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
# SOURCES are source files
@ -30,6 +29,8 @@ SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbenc
# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
WORKDIR = $(VERILATOR_DIR)/wkdir/$(WALLYCONF)_$(TEST)
# regular testbench requires a wrapper defining getenvval
ifeq ($(TESTBENCH), testbench)
WRAPPER=${WALLY}/sim/verilator/wrapper.c
@ -41,9 +42,9 @@ endif
default: run
run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
run: $(WORKDIR)/V${TESTBENCH}
mkdir -p $(VERILATOR_DIR)/logs
wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
$(WORKDIR)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
@ -54,15 +55,16 @@ profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES)
mkdir -p wkdir/$(WALLYCONF)_$(TEST)
$(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES)
mkdir -p $(WORKDIR)
verilator \
--Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \
--Mdir $(WORKDIR) -o V${TESTBENCH} \
--binary --trace \
$(OPT) $(PARAMS) $(NONPROF) \
--top-module ${TESTBENCH} --relative-includes \
$(INCLUDE_PATH) \
${WRAPPER} \
${DEFINE_ARGS} \
${EXPANDED_PARAM_ARGS} \
$(SOURCES)
@ -75,6 +77,7 @@ obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES)
--top-module ${TESTBENCH} --relative-includes \
$(INCLUDE_PATH) \
${WRAPPER} \
${DEFINE_ARGS} \
${EXPANDED_PARAM_ARGS} \
$(SOURCES)

1
site-setup.sh
View File

@ -15,6 +15,7 @@ export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change thi
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin
export BREKER_HOME=/cad/breker/trek5-2.1.10b-GCC6_el7 # Change this for your path to Breker Trek
# Tools
# Questa and Synopsys

2
src/mmu/tlb/tlbram.sv
View File

@ -51,6 +51,6 @@ module tlbram import cvw::*; #(parameter cvw_t P,
or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
// Rename the bits read from the TLB RAM
assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bitss
assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits
assign PPN = PageTableEntry[P.PPN_BITS+9:10];
endmodule

8
src/uncore/spi_apb.sv
View File

@ -174,16 +174,12 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
SPI_CSMODE: ChipSelectMode <= Din[1:0];
SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]};
SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_FMT: Format <= {Din[19:16], Din[2]};
SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
SPI_TXMARK: TransmitWatermark <= Din[2:0];
SPI_RXMARK: ReceiveWatermark <= Din[2:0];
SPI_IE: InterruptEnable <= Din[1:0];
endcase
if (Memwrite)
case(Entry)
SPI_TXDATA: if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
endcase
/* verilator lint_on CASEINCOMPLETE */
// According to FU540 spec: Once interrupt is pending, it will remain set until number

41
src/uncore/spi_controller.sv
View File

@ -75,6 +75,7 @@ module spi_controller (
logic ShiftEdgePulse;
logic SampleEdgePulse;
logic EndOfFramePulse;
logic InvertClock;
// Frame stuff
logic [3:0] BitNum;
@ -107,8 +108,8 @@ module spi_controller (
logic [7:0] DelayCounter;
logic DelayIsNext;
logic DelayState;
logic DelayState;
// Convenient Delay Reg Names
assign cssck = Delay0[7:0];
assign sckcs = Delay0[15:8];
@ -130,10 +131,6 @@ module spi_controller (
assign EndOfDelay = EndOfCSSCK | EndOfSCKCS | EndOfINTERCS | EndOfINTERXFR;
// Clock Signal Stuff -----------------------------------------------
// I'm going to handle all clock stuff here, including ShiftEdge and
// SampleEdge. This makes sure that SPICLK is an output of a register
// and it properly synchronizes signals.
// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
@ -166,12 +163,14 @@ module spi_controller (
end
// SPICLK Logic
// We only want to trigger the clock during Transmission.
// If Phase == 1, then we want to trigger as soon as NextState == TRANSMIT
// Otherwise, only trigger the clock when the CurrState is TRANSMIT.
// We never want to trigger the clock if the NextState is NOT TRANSMIT
if (TransmitStart & ~DelayState) begin
SPICLK <= SckMode[1];
end else if (SCLKenable) begin
if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
end else if (SCLKenable) begin
SPICLK <= (NextState == TRANSMIT) & (~Phase & Transmitting | Phase) ? ~SPICLK : SckMode[1];
end
// Reset divider
@ -201,32 +200,25 @@ module spi_controller (
// Possible pulses for all edge types. Combined with SPICLK to get
// edges for different phase and polarity modes.
assign ShiftEdgePulse = EdgePulse & ~LastBit;
assign SampleEdgePulse = EdgePulse & ~DelayIsNext;
assign SampleEdgePulse = EdgePulse & (NextState == TRANSMIT);
assign EndOfFramePulse = EdgePulse & LastBit;
// Delay ShiftEdge and SampleEdge by a half PCLK period
// Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
// Sweeeeeeeeeet...
assign InvertClock = ^SckMode;
always_ff @(posedge ~PCLK) begin
if (~PRESETn | TransmitStart) begin
ShiftEdge <= 0;
SampleEdge <= 0;
EndOfFrame <= 0;
end else if (^SckMode) begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse;
SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse;
end else begin
ShiftEdge <= SPICLK & ShiftEdgePulse;
SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse;
end
end else begin
ShiftEdge <= (InvertClock ^ SPICLK) & ShiftEdgePulse;
SampleEdge <= (InvertClock ^ ~SPICLK) & SampleEdgePulse;
EndOfFrame <= (InvertClock ^ SPICLK) & EndOfFramePulse;
end
end
// Logic for continuing to transmit through Delay states after end of frame
assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
assign CurrentEndDelay = CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR;
always_ff @(posedge PCLK) begin
if (~PRESETn) begin
CurrState <= INACTIVE;
@ -305,7 +297,6 @@ module spi_controller (
end
assign Transmitting = CurrState == TRANSMIT;
assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
assign DelayState = (CurrState == CSSCK | CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR);
assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS;

83
testbench/common/wallyTracer.sv
View File

@ -45,6 +45,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic InstrValidM, InstrValidW;
logic StallE, StallM, StallW;
logic GatedStallW;
logic SelHPTW;
logic FlushD, FlushE, FlushM, FlushW;
logic TrapM, TrapW;
logic HaltM, HaltW;
@ -66,10 +67,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic InterruptM, InterruptW;
//For VM Verification
logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW;
logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW;
logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW;
logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW;
logic [(P.XLEN-1):0] IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW;
logic [(P.XLEN-1):0] IPTEF,IPTED,IPTEE,IPTEM,IPTEW,DPTEM,DPTEW;
logic [(P.PA_BITS-1):0] IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW;
logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW;
logic [1:0] IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW;
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
@ -90,7 +92,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign StallE = testbench.dut.core.StallE;
assign StallM = testbench.dut.core.StallM;
assign StallW = testbench.dut.core.StallW;
assign GatedStallW = testbench.dut.core.lsu.GatedStallW;
assign GatedStallW = testbench.dut.core.lsu.GatedStallW;
assign SelHPTW = testbench.dut.core.lsu.hptw.hptw.SelHPTW;
assign FlushD = testbench.dut.core.FlushD;
assign FlushE = testbench.dut.core.FlushE;
assign FlushM = testbench.dut.core.FlushM;
@ -112,17 +115,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
end
//For VM Verification
assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
assign IVAdrF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
assign DVAdrM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
assign IPAF = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
assign DPAM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE;
assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE;
assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
logic valid;
@ -357,21 +362,43 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
//for VM Verification
flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW);
flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW);
flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW);
flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW);
flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW);
flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW);
flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW);
// *** what is this used for?
flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD);
flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);
flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM);
flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW);
flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU
flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU
flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU
flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU
flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU
flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU
flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU
flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU
flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU
flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU
flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU
flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU
flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU
flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU
flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU
flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU
flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) IPPNMReg (clk, reset, 1'b0, ~StallM, IPPNE, IPPNM); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) IPPNWReg (clk, reset, 1'b0, ~StallW, IPPNM, IPPNW); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) DPPNWReg (clk, reset, 1'b0, ~StallW, DPPNM, DPPNW); //Physical Page Number for DMMU
flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess
flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess
flopenrc #(1) ExecuteAccessDReg (clk, reset, 1'b0, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access
flopenrc #(1) ExecuteAccessEReg (clk, reset, 1'b0, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access
flopenrc #(1) ExecuteAccessMReg (clk, reset, 1'b0, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access
flopenrc #(1) ExecuteAccessWReg (clk, reset, 1'b0, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access
// Initially connecting the writeback stage signals, but may need to use M stage
// and gate on ~FlushW.

27
testbench/testbench.sv
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@ -44,6 +44,15 @@ module testbench;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
parameter RVVI_SYNTH_SUPPORTED=0;
parameter MAKE_VCD=0;
// TREK Requires a license for the Breker tool. See tests/breker/README.md for details
`ifdef USE_TREK_DV
event trek_start;
always @(testbench.trek_start) begin
trek_uvm_pkg::trek_uvm_events::do_backdoor_init();
end
`endif
`ifdef USE_IMPERAS_DV
import idvPkg::*;
@ -230,10 +239,10 @@ module testbench;
end
$finish;
end
`ifdef MAKEVCD
$dumpfile("testbench.vcd");
$dumpvars;
`endif
if (MAKE_VCD) begin
$dumpfile("testbench.vcd");
$dumpvars;
end
end // initial begin
// Model the testbench as an fsm.
@ -411,7 +420,11 @@ module testbench;
end else if (TEST == "coverage64gc") begin
$display("%s ran. Coverage tests don't get checked", tests[test]);
end else if (ElfFile != "none") begin
$display("Single Elf file tests are not signatured verified.");
`ifdef USE_TREK_DV
$display("Breker test is done.");
`else
$display("Single Elf file tests are not signatured verified.");
`endif
`ifdef QUESTA
$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
`else
@ -518,6 +531,10 @@ module testbench;
end else begin
$fclose(uncoreMemFile);
$readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM);
`ifdef USE_TREK_DV
-> trek_start;
$display("starting Trek....");
`endif
end
end
if (TEST == "embench") $display("Read memfile %s", memfilename);

14
testbench/trek_files/Makefile Normal file
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@ -0,0 +1,14 @@
SHELL := /bin/bash
TREKFILES := $(WALLY)/testbench/trek_files
PLATFORM_YAML := $(TREKFILES)/platform.yaml
TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml
TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation
TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS)
uvm_output: uvm_output/trek_uvm.sv
uvm_output/trek_uvm.sv: $(PLATFORM_YAML) $(TREKSVIP_YAML)
$(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output
clean:
rm -rf uvm_output

9
testbench/trek_files/README.md Normal file
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@ -0,0 +1,9 @@
Jordan Carlin, jcarlin@hmc.edu, December 2024
# Breker Trek Tests Support Files for CVW
[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users).
This directory contains the support files necessary to run Breker's Trek Tests on CVW. For additional details on the tests see [`$WALLY/tests/breker/README.md`](../../tests/breker/README.md)
To generate the Breker support files (with a license), run `make` in the `testbench/trek_files` directory (this one). Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. This Makefile only needs to be run once.

5
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@ -0,0 +1,5 @@
#!/bin/bash
export BREKER_ARCH=${BREKER_HOME}/linux64
export PATH=${BREKER_HOME}/bin:${BREKER_HOME}/examples/tutorials/apps/coherency/bin:${PATH}
export LD_LIBRARY_PATH=".:${BREKER_ARCH}/lib:${BREKER_HOME}/opensrc/gcc/lib:${BREKER_HOME}/opensrc/gcc/lib64":${LD_LIBRARY_PATH}
export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu/:$LIBRARY_PATH

27
testbench/trek_files/customer.yaml Normal file
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@ -0,0 +1,27 @@
trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 5
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
# uncomment the `weights:` line below if any entries under `weights:` need to be enabled
# weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0

263
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@ -0,0 +1,263 @@
trek:
platform_config:
doc: >-
Testbench platform specific configuration.
processors:
doc: >-
Information about available processors.
processor_count:
value: 1
doc: >-
How many processors can be used by the generated test case
sw_threads_per_processor:
value: 2
doc: >-
How many software threads to put on each processor
tlm_generic_ports:
doc: >-
Information about available tlm_generic_payload ports
port_count:
value: 0
doc: >-
How many tlm ports to use for memory operations
threads_per_port:
value: 4
doc: >-
How many threads to put on each tlm port
debug:
value: 1
doc: >-
Turn on for verbose tlm port messages
memories:
doc: >-
Information about memory regions that can be used by the generated test case.
defaults:
doc: >-
Default values for all memories
natural_alignment:
value: 1
doc: >-
Should all memory addresses be naturally aligned (up to 8 byte alignment)
init_type:
value: frontdoor
doc: >-
Strategy to use for memory initialization.
Options are:
- static
- backdoor
- frontdoor
memory:
doc: >-
Define a memory region.
Multiple memory regions may be defined in this section.
name:
value: ddr0
doc: >-
Name of the memory region
base:
value: 0x83000000
doc: >-
Base address of memory region.
Ignored for `static` initialized memory
size:
value: 0x100000
doc: >-
Size of memory region in bytes.
init_type:
value: backdoor #frontdoor
doc: >-
Strategy to use for memory initialization.
Options are:
- static
- backdoor
- frontdoor
caches:
doc: >-
parameters related to cache architecture
cache_line_size:
value: 64
doc: >-
Size of a cache line in bytes
llc_cache_size:
value: 0x200000
doc: >-
size of last level cache in bytes
llc_cache_ways:
value: 8
doc: >-
number of ways in the last level cache
mailbox:
doc: >-
Configure memory mailbox usage
type:
value: single
doc: >-
Configure mailbox type.
Options are:
- single: for use by TrekBox with backdoor access
- queue: for use in post-silicon post-process flow
single:
doc: >-
Detail settings when mailbox type is `single`
init_type:
value: backdoor #static
doc: >-
Strategy to use for mailbox memory initialization.
Options are:
- static
- backdoor
- frontdoor
c2t_base:
value: 0x82000000
doc: >-
Fixed base address of C to trekbox mailbox region.
Allow 64 bytes per processor.
Used for init_type of `backdoor` and `frontdoor` only.
t2c_base:
value: 0x82001000
doc: >-
Fixed base address of trekbox to C mailbox region.
Allow 64 bytes per processor.
Used for init_type of `backdoor` and `frontdoor` only.
cacheable:
value: 1
doc: >-
Set this parameter to 1 to do a cache flush after every mailbox
write.
queue:
doc: >-
Detail settings when mailbox type is `queue`
length:
value: 1000
doc: >-
Max number of messages that can be stored in the queue mailbox.
Longer tests may need a larger queue.
debug:
value: 0
doc: >-
If this flag is set to 1, messages will be printed directly to the
console instead of being queued in memory.
stdio:
doc: >-
Is the <stdio> standard library available for use by the generated test.
available:
value: 0
doc: >-
Set this value to 0 of the <stdio> library is not available in
your system.
use_lock:
value: 1
doc: >-
Calls to <stdio> console print messages will be mutex locked unless
this flag is set to 0.
header:
doc: >-
Verbatim code that will be put into the header section of the test.
value: |-
declaration:
doc: >-
Verbatim code that will be put into the declaration section of the test.
value: |-
extern void tohost_exit(int status);
#undef trek_exit
#define trek_exit(status) tohost_exit(status);
int main(void)
{
return trek_main();
}
mmu: # Trek can generate code to program page/translation tables
# that you MAY want to use with your SDV generated C files.
# Here, you have some control over that process.
va_bits: 39 # How many bits are used for virtual addresses
#
# For aarch64, the value here is used to determine the
# "initial lookup level" (as detailed in Table D5-13).
# This must correlate to TCR_EL3.T0SZ!
#
# For riscv64, only 39, 48, and 57 are supported
# corresponding to "Sv39", "Sv48", and "Sv57".
#
# default: 39 [from T0SZ=64-39=25(0x19)]
memory_map: # A *MAP* of all memory regions, excluding the
# memory_resources in your platformConfig.h file.
#
# Each map entry should be a unique name.
#
# Mandatory submap pairs:
# normal: *true*/false (false = "device"/"io" memory)
# begin: starting address
# end: ending address
#
# Optional submap pairs:
# readable: *true*/false
# writeable: *true*/false
# executable: true/*false*
# cacheable: *true*/false (*false* for device)
# share_type (aarch64 only): *inner-shareable*,
# outer-shareable, non-shareable
#
# Note that memory_resources will use all defaults.
#
# Note that "normal: false" (device-memory) change defaults
# to "cacheable = false", and on arch64 it implies
# share_type = non-shareable, and alloc_type = no-allocate
UART0:
type: device
begin: 0x10000000
end: 0x10000fff
code:
type: normal
begin: 0x80000000
end: 0x807fffff
executable: true
stack:
type: normal
begin: 0x87000000
end: 0x87ffffff
aarch64: # Customizations that are only valid for aarch64.
TCR_EL3: 0x80923519 # Should Trek to program the TCR_TL3 register? If
# so, put the value here. If not, comment out
# this option.
# NOTE: T0SZ should correlate to va_bits above!
# default: -no default-
allocate_type: read-write-allocate # Default allocate_type.
# read-allocate, write-allocate,
# *read-write-allocate*, no-allocate
cache_type: write-back-nontransient # non-cacheable,
# write-through-transient,
# write-back-transient,
# write-through-non-transient,
# *write-back-non-transient*
device_type: nGnRnE # *nGnRnE*, nGnRE, nGRE, GRE
share_type: inner-shareable # non-shareable
# inner-shareable
# outer-shareable
riscv64: # Customizations that are only valid for riscv64.
Svnapot: false # If standard extension "Svnapot" is implemented, and
# when you are using Sv39, you might set this to "true"
# to allow PTE bit[63] "N" to be set when appropriate.
# default: false
Svpbmt: true # If standard extension "Svpbmt" is implemented, and
# when you are using Sv39, you might set this to "true"
# to allow cacheable/device information to flow into
# bits[62:61] "PBMT" as appropriate.
# default: false

91
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@ -0,0 +1,91 @@
/// custom routines defined for the platform
// Design parameters, used in the code below and custom to this design!
//`define RAM_PATH soc_top.soc_instance.i_sram_subsystem.i_shared_ram
//sim:/testbench/dut/uncore/uncore/ram/ram/memory/RAM
//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory.RAM
//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory
`define RAM_PATH testbench.dut.uncoregen.uncore.ram.ram.memory.ram
//`define RAM_BASE_ADDR 32'h80000000
`define RAM_BASE_ADDR testbench.P.UNCORE_RAM_BASE
// These two routines are specific to a particular design. They are used
// to read and write to the "mailbox" locations, to synchronize behaviors
// between C code on the processors with activity performed in UVM (and
// among activities in UVM).
//
// Every design will be different. Here we just have a simple Verilog
// array that we can read and write.
//
function automatic void trek_backdoor_read64(
input longint unsigned address,
output longint unsigned data,
input int unsigned debug = 1);
//bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2;
bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8));
if (address[1:0] != 2'b00) begin: misaligned
$display("%t trek_backdoor_read64: Misaligned address", $time);
$finish();
end
//data[63:32] = `RAM_PATH[offset + 0];
//data[31: 0] = `RAM_PATH[offset + 1];
data[63:0] = `RAM_PATH.RAM[offset + 0];
if (data != 0)
$display("%t trek_backdoor_read64: Read 64'h%016h from address 64'h%016h",
$time, data, address);
endfunction: trek_backdoor_read64
function automatic void trek_backdoor_write64(
input longint unsigned address,
input longint unsigned data,
input int unsigned debug = 1);
//bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2;
bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8));
if (address[1:0] != 2'b00) begin: misaligned
$display("%t trek_backdoor_write64: Misaligned address", $time);
$finish();
end
//`RAM_PATH[offset + 0] = data[63:32];
//`RAM_PATH[offset + 1] = data[31: 0];
`RAM_PATH.RAM[offset + 0] = data[63:0];
//$display("%t trek_backdoor_write64: Wrote 64'h%016h to address 64'h%016h",
//$time, data, address);
endfunction: trek_backdoor_write64
// For performance, we want to read mailboxes ONLY when they're written to!
// (This is very important on emulators!)
//
// Here we trigger a signal when a memory write happens to the range of
// addresses where the mailboxes are.
//
// A clock later, we go poll all the mailboxes (using the "backdoor_read"
// method above.
//
// Each design will be different, depending on where you are able to snoop
// for writes and how long it takes a write to propagate from that point
// to the place where the backdoor read will find it.
bit trek_c2t_mbox_event;
bit trek_is_event_addr;
//assign trek_is_event_addr =
// ((((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) >= `TREK_C2T_MBOX_BASE) &&
// (((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) < `TREK_C2T_MBOX_LIMIT));
//
//always_ff @(posedge `RAM_PATH.clk) begin: trigger_reading_of_mailboxes
// trek_c2t_mbox_event <= (trek_is_event_addr &&
// (`RAM_PATH.n_cs == 1'b0) &&
// (`RAM_PATH.n_we == 1'b0));
//end
// Design specifc: one stage delayed so write has a time to settle
//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes
always @(posedge testbench.clk) begin: read_all_mailboxes
trek_poll_mbox();
end

53
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@ -0,0 +1,53 @@
SHELL := /bin/bash
# Breker/Trek paths and variables
TESTDIR := $(WALLY)/tests/breker/work
TREKFILES := $(WALLY)/testbench/trek_files
CONSTRAINTS_DIR := $(WALLY)/tests/breker/constraints
PLATFORM_YAML := $(TREKFILES)/platform.yaml
CUSTOMER_YAML := $(TREKFILES)/customer.yaml
TREKSVIP_YAML := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml
CONSTRAINT_FILES := $(shell find $(CONSTRAINTS_DIR) -type f)
TREKEXE_FLAGS += --seed 0x # free (0x) or lock (0x1) the seed used for test generation
TREKSVIP := source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS)
# Compilation paths and variables
START_LIB_DIR := $(WALLY)/examples/C/common
START_LIB := $(START_LIB_DIR)/crt.S $(START_LIB_DIR)/syscalls.c
MARCH :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval
MABI :=-mabi=lp64d
LINKER := $(START_LIB_DIR)/test.ld
LINK_FLAGS := -nostartfiles
CFLAGS := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU
WIDTH := 64
# Find all constraint files and generate tests for each one
TESTS = $(patsubst $(CONSTRAINTS_DIR)/%.yaml,$(TESTDIR)/%,$(CONSTRAINT_FILES))
.PHONY: all clean
all: $(TESTS)
# Generate c tests
$(TESTDIR)/%: $(CONSTRAINTS_DIR)/%.yaml | $(TESTDIR)
$(TREKSVIP) -p $< -p $(CUSTOMER_YAML) -o $@/$* -e pss_top.entry
$(MAKE) $@/$*.elf.memfile
# Compile c code
.PRECIOUS: %.elf
%.elf: %.c
riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -T$(LINKER) -I$(START_LIB_DIR) $(START_LIB) -g -o $@ $< > /dev/null
# Convert elf to hex
%.elf.memfile: %.elf
riscv64-unknown-elf-objdump -D $< > $<.objdump
riscv64-unknown-elf-elf2hex --bit-width $(WIDTH) --input $< --output $@
extractFunctionRadix.sh $<.objdump
# View the model graph TODO: What does this do? Move to another makefile?
%.view_graph: $(CONSTRAINTS_DIR)/%.yaml
$(TREKSVIP) -p $(CONSTRAINTS_DIR)/$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry
$(TESTDIR):
mkdir -p $(TESTDIR)
clean:
rm -rf $(TESTS)

18
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@ -0,0 +1,18 @@
Jordan Carlin, jcarlin@hmc.edu, December 2024
# Breker Tests for CVW
[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users).
To generate the Breker tests (with a license), run `make` in both the `tests/breker` and `testbench/trek_files` directories. Alternatively, running `make breker` from the top-level `$WALLY` directory will run both of these. Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. The `testbench/trek_files` Makefile only needs to be run once, but the tests that are generated can be different each time so rerunning the `tests/breker` Makefile is worthwhile.
This will generate a testsuite for each of the constraint yaml files in the `constraints` directory. These generated tests are produced in the `tests/breker/work` directory. To run a single test use `wsim` to run the elf. The `breker` configuration must be used. For example,
```bash
$ wsim breker $WALLY/tests/breker/riscv/riscv.elf
```
To run all of the generated Breker tests use
```bash
$ regression-wally --breker
```

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@ -0,0 +1,73 @@
trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
# pss_top.soc: 0
pss_top.dekker.dekkerTest: 0
# pss_top.atomics.atomicsTest: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off software interrupts
pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
pss_top.coherency: 0
# turn off coherency memory workload tests
# pss_top.workload.entry: 0
# turn of various coherency cache state tests
# pss_top.readOnly.entry: 0
# pss_top.writeOnly.entry: 0
# pss_top.writeRead.entry: 0
# pss_top.readWrite.entry: 0
# pss_top.moesiStates.entry: 0
# pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
# pss_top.microLoops.microLoopScn: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
# pss_top.soc: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off software interrupts
pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
# pss_top.coherency: 0
# turn off coherency memory workload tests
pss_top.workload.entry: 0
# turn of various coherency cache state tests
# pss_top.readOnly.entry: 0
# pss_top.writeOnly.entry: 0
# pss_top.writeRead.entry: 0
# pss_top.readWrite.entry: 0
# pss_top.moesiStates.entry: 0
# pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
pss_top.microLoops.microLoopScn: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
# pss_top.soc: 0
# pss_top.dekker.dekkerTest: 0
pss_top.atomics.atomicsTest: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off software interrupts
pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
pss_top.coherency: 0
# turn off coherency memory workload tests
# pss_top.workload.entry: 0
# turn of various coherency cache state tests
# pss_top.readOnly.entry: 0
# pss_top.writeOnly.entry: 0
# pss_top.writeRead.entry: 0
# pss_top.readWrite.entry: 0
# pss_top.moesiStates.entry: 0
# pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
# pss_top.microLoops.microLoopScn: 0

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# Constraint file to generate simple hello world test that checks the
# initialized values for a few memory locations.
# This constraint file disable all features other than the
trek:
svip:
global:
scenarios:
scenario_count:
# reduce number of scenarios
value: 2
memory_allocation:
memory_sets:
block_size:
# force 4 byte operation
min: 4
max: 4
block_count:
# force a single memory block
min: 1
max: 1
riscv:
extensions:
# disable hypervisor extension
# if your system does not support this feature
h_hypervisor:
value: 0
coherency:
cacheline_states:
scenario_length:
# minimize scenario length
min: 1
max: 1
weights:
# turn of SoC level Dekker and Atomics tests
pss_top.soc: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off memory workload tests
# pss_top.workload.entry: 0
# turn of various cache state tests
pss_top.readOnly.entry: 0
pss_top.writeOnly.entry: 0
pss_top.writeRead.entry: 0
pss_top.readWrite.entry: 0
pss_top.moesiStates.entry: 0
pss_top.tilelinkStates.entry: 0
# turn of micro loop feature
pss_top.microLoops.microLoopScn: 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
pss_top.soc: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off software interrupts
pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
# pss_top.coherency: 0
# turn off coherency memory workload tests
pss_top.workload.entry: 0
# turn of various coherency cache state tests
pss_top.readOnly.entry: 0
pss_top.writeOnly.entry: 0
pss_top.writeRead.entry: 0
pss_top.readWrite.entry: 0
pss_top.moesiStates.entry: 0
pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
# pss_top.microLoops.microLoopScn: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
# pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
pss_top.soc: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off software interrupts
pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
pss_top.coherency: 0
# turn off coherency memory workload tests
# pss_top.workload.entry: 0
# turn of various coherency cache state tests
# pss_top.readOnly.entry: 0
# pss_top.writeOnly.entry: 0
# pss_top.writeRead.entry: 0
# pss_top.readWrite.entry: 0
# pss_top.moesiStates.entry: 0
# pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
# pss_top.microLoops.microLoopScn: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
pss_top.soc: 0
# turn off RV64 opcode tests
# pss_top.rv64.rv64Ops: 0
# turn off software interrupts
# pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
pss_top.coherency: 0
# turn off coherency memory workload tests
# pss_top.workload.entry: 0
# turn of various coherency cache state tests
# pss_top.readOnly.entry: 0
# pss_top.writeOnly.entry: 0
# pss_top.writeRead.entry: 0
# pss_top.readWrite.entry: 0
# pss_top.moesiStates.entry: 0
# pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
# pss_top.microLoops.microLoopScn: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
# weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
# pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
# pss_top.soc: 0
# turn off RV64 opcode tests
# pss_top.rv64.rv64Ops: 0
# turn off software interrupts
# pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
# pss_top.coherency: 0
# turn off coherency memory workload tests
# pss_top.workload.entry: 0
# turn of various coherency cache state tests
# pss_top.readOnly.entry: 0
# pss_top.writeOnly.entry: 0
# pss_top.writeRead.entry: 0
# pss_top.readWrite.entry: 0
# pss_top.moesiStates.entry: 0
# pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
# pss_top.microLoops.microLoopScn: 0

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trek:
svip:
global:
scenarios:
scenario_count:
# primary control for length of test
value: 10
riscv:
extensions:
# disable hypervisor extension by setting value to 0
# if your system does not support this feature
h_hypervisor:
value: 0
weights:
# disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
# if your system does not support this feature
# pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
# qemu-riscv64 does not ignore writes to WARL bits in hgatp
# Comment out the next line unless your design has this issue
# pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
# turn off MMU Tests
pss_top.rvMmu.rvMmuOp: 0
# turn off rvMmu Self-modifying-code (SMC) scenarios
# pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
# turn off rvMmuOp page fault cases
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
# pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
# turn of SoC level Dekker and Atomics tests
pss_top.soc: 0
# turn off RV64 opcode tests
pss_top.rv64.rv64Ops: 0
# turn off software interrupts
pss_top.rvMswi.rvMswiOp: 0
# turn off all coherency tests
# pss_top.coherency: 0
# turn off coherency memory workload tests
# pss_top.workload.entry: 0
# turn of various coherency cache state tests
pss_top.readOnly.entry: 0
pss_top.writeOnly.entry: 0
pss_top.writeRead.entry: 0
pss_top.readWrite.entry: 0
pss_top.moesiStates.entry: 0
pss_top.tilelinkStates.entry: 0
# turn of coherency micro loop feature
# these scenarios take a while to run
pss_top.microLoops.microLoopScn: 0