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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2021-08-25 06:47:20 -04:00
commit 7d24ed3c51
12 changed files with 296 additions and 227 deletions
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18
wally-pipelined/linux-testgen/testvector-generation/CreateTrace.sh Executable file
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@ -0,0 +1,18 @@
#!/bin/bash
# Oftentimes this script runs so long you'll go to sleep.
# But you don't want the script to die when your computer goes to sleep.
# So consider invoking this with nohup (i.e. "nohup ./logAllBuildroot.sh")
# You can run "tail -f nohup.out" to see what would've
# outputted to the terminal if you didn't use nohup
#customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
customQemu="qemu-system-riscv64"
imageDir="../buildroot-image-output"
intermedDir="../linux-testvectors/intermediate-outputs"
outDir="../linux-testvectors"
# - Logs info needed by buildroot testbench
#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parseNew.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
#./fix_csrs.py "$outDir"
($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parseNew.py | ./remove_dup.awk > all.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog

9
wally-pipelined/linux-testgen/testvector-generation/parseNew.py
View File

@ -9,9 +9,10 @@ import sys, fileinput, re
InstrStartDelim = '=>' InstrStartDelim = '=>'
InstrEndDelim = '-----' InstrEndDelim = '-----'
InputFile = 'noparse.txt' #InputFile = 'noparse.txt'
#InputFile = sys.stdin
#InputFile = 'temp.txt' #InputFile = 'temp.txt'
OutputFile = 'parsedAll.txt' #OutputFile = 'parsedAll.txt'
HUMAN_READABLE = False HUMAN_READABLE = False
@ -134,7 +135,7 @@ RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't
# initial state # initial state
CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None] CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None]
with open (InputFile, 'r') as InputFileFP: #with open (InputFile, 'r') as InputFileFP:
#lines = InputFileFP.readlines() #lines = InputFileFP.readlines()
lineNum = 0 lineNum = 0
StartLine = 0 StartLine = 0
@ -142,7 +143,7 @@ with open (InputFile, 'r') as InputFileFP:
#instructions = [] #instructions = []
MemAdr = 0 MemAdr = 0
lines = [] lines = []
for line in InputFileFP: for line in fileinput.input('-'):
lines.insert(lineNum, line) lines.insert(lineNum, line)
if InstrStartDelim in line: if InstrStartDelim in line:
lineNum = 0 lineNum = 0

20
wally-pipelined/linux-testgen/testvector-generation/remove_dup.awk Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/awk -f
BEGIN{
old = "first"
}
{
if($1 != old){
if(old != "first"){
print oldAll
}
}
old=$1
oldAll=$0
}
END{
print oldAll
}

162
wally-pipelined/regression/linux-wave.do
View File

@ -13,41 +13,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@ -265,7 +265,6 @@ add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
@ -362,28 +361,26 @@ add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/du
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
add wave -noupdate -expand -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
add wave -noupdate -expand -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW add wave -noupdate -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@ -452,46 +449,35 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
add wave -noupdate -expand -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/dut/hart/PCM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/ExpectedPCM add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/line add wave -noupdate -group {debug trace} -expand -group mem /testbench/line
add wave -noupdate -expand -group {debug trace} -expand -group mem /testbench/textM add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
add wave -noupdate -expand -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/hart/hzu/TrapM
add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW add wave -noupdate -group {debug trace} -expand -group wb /testbench/dut/hart/ieu/c/InstrValidW
add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/checkInstrW add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/ExpectedPCW add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/TrapW add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
add wave -noupdate -expand -group {debug trace} -expand -group wb /testbench/textW add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
add wave -noupdate /testbench/dut/hart/priv/csr/CSRReadValW add wave -noupdate /testbench/FunctionName/FunctionAddr
add wave -noupdate /testbench/dut/hart/priv/csr/CSRReadValM add wave -noupdate /testbench/FunctionName/FunctionName
add wave -noupdate /testbench/dut/hart/priv/TimerIntM add wave -noupdate /testbench/FunctionName/ProgramAddrMapFile
add wave -noupdate /testbench/dut/hart/priv/ExtIntM add wave -noupdate /testbench/FunctionName/ProgramLabelMapFile
add wave -noupdate /testbench/dut/hart/priv/SwIntM
add wave -noupdate /testbench/ExpectedIntType
add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/csri/IntInM
add wave -noupdate /testbench/dut/hart/priv/trap/PendingIntsM
add wave -noupdate /testbench/NumCSRM
add wave -noupdate /testbench/NumCSRW
add wave -noupdate /testbench/NumCSRPostWIndex
add wave -noupdate /testbench/ExpectedCSRArrayM
add wave -noupdate /testbench/ExpectedCSRArrayW
add wave -noupdate /testbench/ExpectedCSRArrayValueM
add wave -noupdate /testbench/ExpectedCSRArrayValueW
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 6} {161370956 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {39985218 ns} 0} {{Cursor 23} {8229603 ns} 0} WaveRestoreCursors {{Cursor 6} {161370956 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {39985218 ns} 0} {{Cursor 23} {8750281 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 4
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 297 configure wave -valuecolwidth 354
configure wave -justifyvalue left configure wave -justifyvalue left
configure wave -signalnamewidth 1 configure wave -signalnamewidth 1
configure wave -snapdistance 10 configure wave -snapdistance 10
@ -504,4 +490,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {161370843 ns} {161371387 ns} WaveRestoreZoom {0 ns} {9232357 ns}

5
wally-pipelined/src/hazard/hazard.sv
View File

@ -34,6 +34,7 @@ module hazard(
input logic LSUStall, ICacheStallF, input logic LSUStall, ICacheStallF,
input logic FPUStallD, FStallD, input logic FPUStallD, FStallD,
input logic DivBusyE,FDivBusyE, input logic DivBusyE,FDivBusyE,
input logic EcallFaultM, BreakpointFaultM,
// Stall & flush outputs // Stall & flush outputs
output logic StallF, StallD, StallE, StallM, StallW, output logic StallF, StallD, StallE, StallM, StallW,
output logic FlushF, FlushD, FlushE, FlushM, FlushW output logic FlushF, FlushD, FlushE, FlushM, FlushW
@ -79,5 +80,7 @@ module hazard(
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE;
assign FlushM = FirstUnstalledM | TrapM | RetM; assign FlushM = FirstUnstalledM | TrapM | RetM;
assign FlushW = FirstUnstalledW | TrapM; // on Trap the memory stage should be flushed going into the W stage,
// except if the instruction causing the Trap is an ecall or ebreak.
assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));
endmodule endmodule

3
wally-pipelined/src/privileged/csr.sv
View File

@ -33,7 +33,8 @@ module csr #(parameter
UIE_REGW = 12'b0 UIE_REGW = 12'b0
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic FlushW, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW,
input logic StallD, StallE, StallM, StallW,
input logic [31:0] InstrD,InstrE,InstrM, input logic [31:0] InstrD,InstrE,InstrM,
input logic [`XLEN-1:0] PCF, PCD, PCE, PCM, SrcAM, input logic [`XLEN-1:0] PCF, PCD, PCE, PCM, SrcAM,
input logic InterruptM, input logic InterruptM,

35
wally-pipelined/src/privileged/csrc.sv
View File

@ -72,6 +72,7 @@ module csrc #(parameter
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic StallD, StallE, StallM, StallW, input logic StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
input logic InstrValidM, LoadStallD, CSRMWriteM, input logic InstrValidM, LoadStallD, CSRMWriteM,
input logic BPPredDirWrongM, input logic BPPredDirWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,
@ -103,6 +104,10 @@ module csrc #(parameter
logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M; logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M;
logic [4:0] CounterNumM; logic [4:0] CounterNumM;
logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW; logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTER_REGW, HPMCOUNTERH_REGW;
logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
//logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTERH_REGW; //logic [`COUNTERS-1:3][`XLEN-1:0] HPMCOUNTERH_REGW;
// Write enables // Write enables
@ -116,7 +121,7 @@ module csrc #(parameter
// Counter adders with inhibits for power savings // Counter adders with inhibits for power savings
assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]}; assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
//assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited //assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidM & ~StallW & ~MCOUNTINHIBIT_REGW[2]}; assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidNotFlushedM & ~MCOUNTINHIBIT_REGW[2]};
//assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls //assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
//assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals //assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0]; assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
@ -139,17 +144,23 @@ module csrc #(parameter
if(`QEMU) begin if(`QEMU) begin
assign CounterEvent[`COUNTERS-1:2] = 0; assign CounterEvent[`COUNTERS-1:2] = 0;
end else begin end else begin
assign CounterEvent[2] = InstrValidM & ~StallW;
assign CounterEvent[3] = LoadStallD & ~StallD; logic LoadStallE, LoadStallM;
assign CounterEvent[4] = BPPredDirWrongM & ~StallM;
assign CounterEvent[5] = InstrClassM[0] & ~StallM; flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(FlushE), .en(~StallE), .d(LoadStallD), .q(LoadStallE));
assign CounterEvent[6] = BTBPredPCWrongM & ~StallM; flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & ~StallM;
assign CounterEvent[8] = RASPredPCWrongM & ~StallM; assign CounterEvent[2] = InstrValidNotFlushedM;
assign CounterEvent[9] = InstrClassM[3] & ~StallM; assign CounterEvent[3] = LoadStallM & InstrValidNotFlushedM;
assign CounterEvent[10] = BPPredClassNonCFIWrongM & ~StallM; assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM;
assign CounterEvent[11] = DCacheAccess & ~StallM; assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
assign CounterEvent[12] = DCacheMiss & ~StallM; assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;
assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & InstrValidNotFlushedM;
assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM;
assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM;
assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM;
assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end end

11
wally-pipelined/src/privileged/csri.sv
View File

@ -52,17 +52,12 @@ module csri #(parameter
always_comb begin always_comb begin
IntInM = 0; IntInM = 0;
IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP IntInM[11] = ExtIntM;; // MEIP
IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
IntInM[3] = SwIntM & ~MIDELEG_REGW[1]; // MSIP
IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
/* maybe only machine mode interrupts should be directly triggered:
IntInM[11] = ExtIntM; // MEIP
IntInM[7] = TimerIntM; // MTIP IntInM[7] = TimerIntM; // MTIP
IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
IntInM[3] = SwIntM; // MSIP IntInM[3] = SwIntM; // MSIP
*/ IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
end end
// Interrupt Write Enables // Interrupt Write Enables

5
wally-pipelined/src/privileged/privileged.sv
View File

@ -75,7 +75,9 @@ module privileged (
output logic [1:0] STATUS_MPP, output logic [1:0] STATUS_MPP,
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
output logic [2:0] FRM_REGW output logic [2:0] FRM_REGW,
output logic BreakpointFaultM, EcallFaultM
); );
logic [1:0] NextPrivilegeModeM; logic [1:0] NextPrivilegeModeM;
@ -94,7 +96,6 @@ module privileged (
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic IllegalInstrFaultM, TrappedSRETM; logic IllegalInstrFaultM, TrappedSRETM;
logic BreakpointFaultM, EcallFaultM;
logic MTrapM, STrapM, UTrapM; logic MTrapM, STrapM, UTrapM;
logic InterruptM; logic InterruptM;

1
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -167,6 +167,7 @@ module wallypipelinedhart
logic PendingInterruptM; logic PendingInterruptM;
logic DCacheMiss; logic DCacheMiss;
logic DCacheAccess; logic DCacheAccess;
logic BreakpointFaultM, EcallFaultM;
ifu ifu(.InstrInF(InstrRData), ifu ifu(.InstrInF(InstrRData),

2
wally-pipelined/testbench/common/function_radix.sv
View File

@ -85,7 +85,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
end else if( array[mid] > pc) begin end else if( array[mid] > pc) begin
right = mid -1; right = mid -1;
end else begin end else begin
$display("Critical Error in FunctionName. PC, %x not found.", pc); //$display("Critical Error in FunctionName. PC, %x not found.", pc);
return; return;
//$stop(); //$stop();
end end

116
wally-pipelined/testbench/testbench-linux.sv
View File

@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
`define DEBUG_TRACE 1 `define DEBUG_TRACE 0
`define DontHaltOnCSRMisMatch 1 `define DontHaltOnCSRMisMatch 1
module testbench(); module testbench();
@ -33,6 +33,8 @@ module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can) parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
string ProgramAddrMapFile, ProgramLabelMapFile;
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// DUT ///////////////////////////////////// ///////////////////////////////////// DUT /////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@ -128,7 +130,8 @@ module testbench();
integer NumCSRMIndex; integer NumCSRMIndex;
integer NumCSRWIndex; integer NumCSRWIndex;
integer NumCSRPostWIndex; integer NumCSRPostWIndex;
logic CurrentInterruptForce; // logic CurrentInterruptForce;
logic [`XLEN-1:0] InstrCountW;
// ----------- // -----------
// Error Macro // Error Macro
@ -139,13 +142,16 @@ module testbench();
initial begin initial begin
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
InstrCountW = '0;
end end
/* -----\/----- EXCLUDED -----\/-----
initial begin initial begin
CurrentInterruptForce = 1'b0; CurrentInterruptForce = 1'b0;
end end
-----/\----- EXCLUDED -----/\----- */
assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.StallM; assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
// trapW will already be invalid in there was an InstrPageFault in the previous instruction. // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW; assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW;
@ -228,6 +234,29 @@ module testbench();
MarkerIndex += 2; MarkerIndex += 2;
// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
// are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
// the msb of xcause will be set.
// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin
//what type?
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
if(ExpectedIntType == 0) begin
force dut.hart.priv.SwIntM = 1'b1;
$display("Force SwIntM");
end
else if(ExpectedIntType == 4) begin
force dut.hart.priv.TimerIntM = 1'b1;
$display("Force TimeIntM");
end
else if(ExpectedIntType == 8) begin
force dut.hart.priv.ExtIntM = 1'b1;
$display("Force ExtIntM");
end
end
NumCSRM++; NumCSRM++;
end end
end end
@ -306,6 +335,17 @@ module testbench();
release dut.hart.ieu.dp.ReadDataM; release dut.hart.ieu.dp.ReadDataM;
end end
// remove forces on interrupts
for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
//what type?
$display("%t: Releasing all forces on interrupts", $time);
release dut.hart.priv.SwIntM;
release dut.hart.priv.TimerIntM;
release dut.hart.priv.ExtIntM;
end
end
end end
end end
end end
@ -314,6 +354,7 @@ module testbench();
always @(negedge clk) begin always @(negedge clk) begin
// always check PC, instruction bits // always check PC, instruction bits
if (checkInstrW) begin if (checkInstrW) begin
InstrCountW += 1;
// check PCW // check PCW
fault = 0; fault = 0;
if(PCW != ExpectedPCW) begin if(PCW != ExpectedPCW) begin
@ -327,6 +368,11 @@ module testbench();
fault = 1; fault = 1;
end end
// check the number of instructions
if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin
$display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
if(!`DontHaltOnCSRMisMatch) fault = 1;
end
#2; // delay 2 ns. #2; // delay 2 ns.
@ -391,7 +437,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -400,7 +446,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) != (ExpectedCSRArrayValueW[NumCSRPostWIndex])) begin if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) != (ExpectedCSRArrayValueW[NumCSRPostWIndex])) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -409,7 +455,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -418,7 +464,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MIP_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MIP_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -427,7 +473,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MIE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MIE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -436,7 +482,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -445,7 +491,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -454,7 +500,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -464,7 +510,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -474,7 +520,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrs.SEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrs.SEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -483,7 +529,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -492,7 +538,7 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrs.STVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrs.STVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
@ -501,12 +547,13 @@ module testbench();
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
if (dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin if (dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, CSR: %s = %016x, does not equal expected value %016x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex]) endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex])
/* -----\/----- EXCLUDED -----\/-----
if(CurrentInterruptForce) begin if(CurrentInterruptForce) begin
CurrentInterruptForce = 1'b0; CurrentInterruptForce = 1'b0;
// remove forces on interrupts // remove forces on interrupts
@ -516,32 +563,8 @@ module testbench();
release dut.hart.priv.TimerIntM; release dut.hart.priv.TimerIntM;
release dut.hart.priv.ExtIntM; release dut.hart.priv.ExtIntM;
end end
-----/\----- EXCLUDED -----/\----- */
// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
// are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
// the msb of xcause will be set.
// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
if(ExpectedCSRArrayW[NumCSRPostWIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueW[NumCSRPostWIndex][`XLEN-1] == 1'b1)) begin
//what type?
ExpectedIntType = ExpectedCSRArrayValueW[NumCSRPostWIndex] & 64'h0000_000C;
$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]);
CurrentInterruptForce = 1'b1;
if(ExpectedIntType == 0) begin
force dut.hart.priv.SwIntM = 1'b1;
$display("Force SwIntM");
end
else if(ExpectedIntType == 4) begin
force dut.hart.priv.TimerIntM = 1'b1;
$display("Force TimeIntM");
end
else if(ExpectedIntType == 8) begin
force dut.hart.priv.ExtIntM = 1'b1;
$display("Force ExtIntM");
end
end
end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++)
if (fault == 1) begin if (fault == 1) begin
`ERROR `ERROR
@ -550,9 +573,17 @@ module testbench();
end // always @ (negedge clk) end // always @ (negedge clk)
// track the current function
FunctionName FunctionName(.reset(reset),
.clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile));
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
//////////////////////////////// Testbench Core /////////////////////////////// //////////////////////////////// Testbench Core ///////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// -------------- // --------------
// Initialization // Initialization
// -------------- // --------------
@ -567,6 +598,8 @@ module testbench();
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
end end
// ------- // -------
@ -578,7 +611,6 @@ module testbench();
end end
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Miscellaneous /////////////////////////////// ///////////////////////////////// Miscellaneous ///////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////