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Mixed C and assembly language test cases; SRT initial version passing tests

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This commit is contained in:
David Harris 2022-01-13 21:45:54 +00:00
parent 4b7ee9815e
commit 7d13740a11
27 changed files with 597 additions and 11770 deletions
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32
examples/C/inline/Makefile Normal file
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TARGET = inline
$(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \
$(TARGET).c ../common/crt.S ../common/syscalls.c
# Compiler flags:
# -o $(TARGET) defines the name of the output file
# -g generates debugging symbols for gdb
# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
# -static forces static linking (no dynamic shared libraries on bare metal)
# -lm links the math library if necessary (when #include math.h)
# -nostdlib avoids inserting standard startup files and default libraries
# because we are using crt.s on bare metal
# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library
# -T specifies the linker file
# -I specifies the include path (e.g. for util.h)
# The last line defines the C files to compile.
# crt.S is needed as our startup file to initialize the processor
# syscalls.c implements printf through the HTIF for Spike
# other flags from riscv-tests makefiles that don't seem to be important
# -ffast-math -DPREALLOCATE=1 -std=gnu99 \
# -fno-common -fno-builtin-printf -nostartfiles -lgcc \
clean:
rm -f $(TARGET) $(TARGET).objdump

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examples/C/inline/inline.c Normal file
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// inline.c
// David_Harris@hmc.edu 12 January 2022
// Illustrates inline assembly language
#include <stdio.h>
int main(void) {
long cycles;
asm volatile("csrr %0, 0xB00" : "=r"(cycles)); // read mcycle register
printf ("mcycle = %ld\n", cycles);
}

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examples/C/mm/Makefile
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TARGET = mm
$(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64d -mcmodel=medany \
-DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common \
-fno-builtin-printf -fno-tree-loop-distribute-patterns \
-static -nostdlib -nostartfiles -lm -lgcc -T../common/test.ld \
-I../common \
-O *.c \
../common/crt.S ../common/syscalls.c
clean:
rm -f $(TARGET) $(TARGET).objdump

36
examples/C/mm/common.h
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// See LICENSE for license details.
#ifndef _MM_H
#define _MM_H
#include <string.h>
#include <stdint.h>
#include <math.h>
#ifdef SP
typedef float t;
#define fma fmaf
#else
typedef double t;
#endif
#define inline inline __attribute__((always_inline))
#define alloca_aligned(s, a) ((void*)(((uintptr_t)alloca((s)+(a)-1)+(a)-1)&~((a)-1)))
#include "rb.h"
#ifdef __cplusplus
extern "C" {
#endif
void mm(size_t m, size_t n, size_t p,
t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc);
#ifdef __cplusplus
}
#endif
//void rb(t* a, t* b, t* c, size_t lda, size_t ldb, size_t ldc);
#endif

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examples/C/mm/mm
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examples/C/mm/mm.c
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// See LICENSE for license details.
#include "common.h"
#include <assert.h>
#include <math.h>
#include <stdint.h>
#include <alloca.h>
#define MIN(a, b) ((a) < (b) ? (a) : (b))
static void mm_naive(size_t m, size_t n, size_t p,
t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
{
for (size_t i = 0; i < m; i++)
{
for (size_t j = 0; j < n; j++)
{
t s0 = c[i*ldc+j], s1 = 0, s2 = 0, s3 = 0;
for (size_t k = 0; k < p/4*4; k+=4)
{
s0 = fma(a[i*lda+k+0], b[(k+0)*ldb+j], s0);
s1 = fma(a[i*lda+k+1], b[(k+1)*ldb+j], s1);
s2 = fma(a[i*lda+k+2], b[(k+2)*ldb+j], s2);
s3 = fma(a[i*lda+k+3], b[(k+3)*ldb+j], s3);
}
for (size_t k = p/4*4; k < p; k++)
s0 = fma(a[i*lda+k], b[k*ldb+j], s0);
c[i*ldc+j] = (s0 + s1) + (s2 + s3);
}
}
}
static inline void mm_rb(size_t m, size_t n, size_t p,
t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
{
size_t mb = m/RBM*RBM, nb = n/RBN*RBN;
for (size_t i = 0; i < mb; i += RBM)
{
for (size_t j = 0; j < nb; j += RBN)
kloop(p, a+i*lda, lda, b+j, ldb, c+i*ldc+j, ldc);
mm_naive(RBM, n - nb, p, a+i*lda, lda, b+nb, ldb, c+i*ldc+nb, ldc);
}
mm_naive(m - mb, n, p, a+mb*lda, lda, b, ldb, c+mb*ldc, ldc);
}
static inline void repack(t* a, size_t lda, const t* a0, size_t lda0, size_t m, size_t p)
{
for (size_t i = 0; i < m; i++)
{
for (size_t j = 0; j < p/8*8; j+=8)
{
t t0 = a0[i*lda0+j+0];
t t1 = a0[i*lda0+j+1];
t t2 = a0[i*lda0+j+2];
t t3 = a0[i*lda0+j+3];
t t4 = a0[i*lda0+j+4];
t t5 = a0[i*lda0+j+5];
t t6 = a0[i*lda0+j+6];
t t7 = a0[i*lda0+j+7];
a[i*lda+j+0] = t0;
a[i*lda+j+1] = t1;
a[i*lda+j+2] = t2;
a[i*lda+j+3] = t3;
a[i*lda+j+4] = t4;
a[i*lda+j+5] = t5;
a[i*lda+j+6] = t6;
a[i*lda+j+7] = t7;
}
for (size_t j = p/8*8; j < p; j++)
a[i*lda+j] = a0[i*lda0+j];
}
}
static void mm_cb(size_t m, size_t n, size_t p,
t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
{
size_t nmb = m/CBM, nnb = n/CBN, npb = p/CBK;
size_t mb = nmb*CBM, nb = nnb*CBN, pb = npb*CBK;
//t a1[mb*pb], b1[pb*nb], c1[mb*nb];
t* a1 = (t*)alloca_aligned(sizeof(t)*mb*pb, 8192);
t* b1 = (t*)alloca_aligned(sizeof(t)*pb*nb, 8192);
t* c1 = (t*)alloca_aligned(sizeof(t)*mb*nb, 8192);
for (size_t i = 0; i < mb; i += CBM)
for (size_t j = 0; j < pb; j += CBK)
repack(a1 + (npb*(i/CBM) + j/CBK)*(CBM*CBK), CBK, a + i*lda + j, lda, CBM, CBK);
for (size_t i = 0; i < pb; i += CBK)
for (size_t j = 0; j < nb; j += CBN)
repack(b1 + (nnb*(i/CBK) + j/CBN)*(CBK*CBN), CBN, b + i*ldb + j, ldb, CBK, CBN);
for (size_t i = 0; i < mb; i += CBM)
for (size_t j = 0; j < nb; j += CBN)
repack(c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN, c + i*ldc + j, ldc, CBM, CBN);
for (size_t i = 0; i < mb; i += CBM)
{
for (size_t j = 0; j < nb; j += CBN)
{
for (size_t k = 0; k < pb; k += CBK)
{
mm_rb(CBM, CBN, CBK,
a1 + (npb*(i/CBM) + k/CBK)*(CBM*CBK), CBK,
b1 + (nnb*(k/CBK) + j/CBN)*(CBK*CBN), CBN,
c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN);
}
if (pb < p)
{
mm_rb(CBM, CBN, p - pb,
a + i*lda + pb, lda,
b + pb*ldb + j, ldb,
c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN);
}
}
if (nb < n)
{
for (size_t k = 0; k < p; k += CBK)
{
mm_rb(CBM, n - nb, MIN(p - k, CBK),
a + i*lda + k, lda,
b + k*ldb + nb, ldb,
c + i*ldc + nb, ldc);
}
}
}
if (mb < m)
{
for (size_t j = 0; j < n; j += CBN)
{
for (size_t k = 0; k < p; k += CBK)
{
mm_rb(m - mb, MIN(n - j, CBN), MIN(p - k, CBK),
a + mb*lda + k, lda,
b + k*ldb + j, ldb,
c + mb*ldc + j, ldc);
}
}
}
for (size_t i = 0; i < mb; i += CBM)
for (size_t j = 0; j < nb; j += CBN)
repack(c + i*ldc + j, ldc, c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN, CBM, CBN);
}
void mm(size_t m, size_t n, size_t p,
t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
{
if (__builtin_expect(m <= 2*CBM && n <= 2*CBN && p <= 2*CBK, 1))
mm_rb(m, n, p, a, lda, b, ldb, c, ldc);
else
mm_cb(m, n, p, a, lda, b, ldb, c, ldc);
}

76
examples/C/mm/mm_main.c
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// See LICENSE for license details.
#include "common.h"
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include "util.h"
#pragma GCC optimize ("unroll-loops")
int main(int argc, char** argv)
//void thread_entry(int cid, int nc)
{
const int R = 8;
int m, n, p;
uint64_t s = 0xdeadbeefU;
int cid = 0;
int nc = 0;
m = CBM;
n = CBN;
p = CBK;
t a[m*p];
t b[p*n];
t c[m*n];
for (size_t i = 0; i < m; i++)
for (size_t j = 0; j < p; j++)
a[i*p+j] = (t)(s = lfsr(s));
for (size_t i = 0; i < p; i++)
for (size_t j = 0; j < n; j++)
b[i*n+j] = (t)(s = lfsr(s));
memset(c, 0, m*n*sizeof(c[0]));
size_t instret, cycles;
for (int i = 0; i < R; i++)
{
instret = -read_csr(minstret);
cycles = -read_csr(mcycle);
mm(m, n, p, a, p, b, n, c, n);
instret += read_csr(minstret);
cycles += read_csr(mcycle);
}
asm volatile("fence");
printf("C%d: reg block %dx%dx%d, cache block %dx%dx%d\n",
cid, RBM, RBN, RBK, CBM, CBN, CBK);
printf("C%d: %d instructions\n", cid, (int)(instret));
printf("C%d: %d cycles\n", cid, (int)(cycles));
printf("C%d: %d flops\n", cid, 2*m*n*p);
printf("C%d: %d Mflops @ 1 GHz\n", cid, 2000*m*n*p/(cycles));
#if 1
for (size_t i = 0; i < m; i++)
{
for (size_t j = 0; j < n; j++)
{
t s = 0;
for (size_t k = 0; k < p; k++)
s += a[i*p+k] * b[k*n+j];
s *= R;
if (fabs(c[i*n+j]-s) > fabs(1e-6*s))
{
printf("C%d: c[%lu][%lu] %f != %f\n", cid, i, j, c[i*n+j], s);
exit(1);
}
}
}
#endif
//barrier(nc);
exit(0);
}

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examples/C/mm/old.gen.scala
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import scala.sys.process._
object MMGen {
implicit def i2s(i: Int) = i.toString
def writeFile(name: String, contents: String) = {
val f = new java.io.FileWriter(name)
f.write(contents)
f.close
}
var indent = 0
def spacing = " " * indent
def assign(lhs: String, rhs: String) =
spacing + lhs + " = " + rhs + ";\n"
def init(t: String, n: String, v: String) =
assign(t+" "+n, v)
def open_block(s: String = "") = {
val result = (if (s != "") spacing + s else "") + spacing + "{\n"
indent = indent + 1
result
}
def close_block = {
indent = indent - 1
spacing + "}\n"
}
def ar(m: String, i: String) = m+"["+i+"]"
def r(a: String, b: String*) = (a :: b.toList).reduceLeft(_+"_"+_)
def rb(m: Int, n: Int, p: Int) = {
var s = open_block("static inline void kloop(size_t p, t* a0, size_t lda, t* b0, size_t ldb, t* c, size_t ldc)\n")
for (i <- 0 until m)
s += init("t*", r("c", i), "&"+ar("c", "ldc*"+i))
for (i <- 0 until m; j <- 0 until n)
s += init("t", r("c", i, j), ar(r("c", i), j))
def doit(m: Int, n: Int, p: Int) = {
for (i <- 0 until m)
s += init("t*", r("a", i), "&"+ar("a", "lda*"+i))
for (k <- 0 until p)
s += init("t*", r("b", k), "&"+ar("b", "ldb*"+k))
for (k <- 0 until p; i <- 0 until m; j <- 0 until n)
s += assign(r("c", i, j), "fma(" + ar(r("a", i), k) + ", " + ar(r("b", k), j) + ", " + r("c", i, j) + ")")
}
s += open_block("for (t *a = a0, *b = b0; a < a0 + p/RBK*RBK; a += RBK, b += RBK*ldb)\n")
doit(m, n, p)
s += close_block
s += open_block("for (t *a = a0 + p/RBK*RBK, *b = b0 + p/RBK*RBK*ldb; a < a0 + p; a++, b += ldb)\n")
doit(m, n, 1)
s += close_block
for (i <- 0 until m; j <- 0 until n)
s += assign(ar(r("c", i), j), r("c", i, j))
s += close_block
s
}
def gcd(a: Int, b: Int): Int = if (b == 0) a else gcd(b, a%b)
def lcm(a: Int, b: Int): Int = a*b/gcd(a, b)
def lcm(a: Seq[Int]): Int = {
if (a.tail.isEmpty) a.head
else lcm(a.head, lcm(a.tail))
}
def test1(m: Int, n: Int, p: Int, m1: Int, n1: Int, p1: Int) = {
val decl = "static const int RBM = "+m+", RBN = "+n+", RBK = "+p+";\n" +
"static const int CBM = "+m1+", CBN = "+n1+", CBK = "+p1+";\n"
writeFile("rb.h", decl + rb(m, n, p))
//"make"!!
"make run"!
("cp a.out " + Seq("b", m, n, p, m1, n1, p1, "run").reduce(_+"."+_))!
}
def main(args: Array[String]): Unit = {
test1(4, 5, 6, 24, 25, 24)
//for (i <- 4 to 6; j <- 4 to 6; k <- 4 to 6)
// test1(i, j, k, if (i == 5) 35 else 36, if (j == 5) 35 else 36, if (k == 5) 35 else 36)
}
}

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examples/C/mm/rb.h
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static const int RBM = 4, RBN = 5, RBK = 6;
static const int CBM = 24, CBN = 25, CBK = 24;
static inline void kloop(size_t p, t* a0, size_t lda, t* b0, size_t ldb, t* c, size_t ldc)
{
t* c_0 = &c[ldc*0];
t* c_1 = &c[ldc*1];
t* c_2 = &c[ldc*2];
t* c_3 = &c[ldc*3];
t c_0_0 = c_0[0];
t c_0_1 = c_0[1];
t c_0_2 = c_0[2];
t c_0_3 = c_0[3];
t c_0_4 = c_0[4];
t c_1_0 = c_1[0];
t c_1_1 = c_1[1];
t c_1_2 = c_1[2];
t c_1_3 = c_1[3];
t c_1_4 = c_1[4];
t c_2_0 = c_2[0];
t c_2_1 = c_2[1];
t c_2_2 = c_2[2];
t c_2_3 = c_2[3];
t c_2_4 = c_2[4];
t c_3_0 = c_3[0];
t c_3_1 = c_3[1];
t c_3_2 = c_3[2];
t c_3_3 = c_3[3];
t c_3_4 = c_3[4];
for (t *a = a0, *b = b0; a < a0 + p/RBK*RBK; a += RBK, b += RBK*ldb)
{
t* a_0 = &a[lda*0];
t* a_1 = &a[lda*1];
t* a_2 = &a[lda*2];
t* a_3 = &a[lda*3];
t* b_0 = &b[ldb*0];
t* b_1 = &b[ldb*1];
t* b_2 = &b[ldb*2];
t* b_3 = &b[ldb*3];
t* b_4 = &b[ldb*4];
t* b_5 = &b[ldb*5];
c_0_0 = fma(a_0[0], b_0[0], c_0_0);
c_0_1 = fma(a_0[0], b_0[1], c_0_1);
c_0_2 = fma(a_0[0], b_0[2], c_0_2);
c_0_3 = fma(a_0[0], b_0[3], c_0_3);
c_0_4 = fma(a_0[0], b_0[4], c_0_4);
c_1_0 = fma(a_1[0], b_0[0], c_1_0);
c_1_1 = fma(a_1[0], b_0[1], c_1_1);
c_1_2 = fma(a_1[0], b_0[2], c_1_2);
c_1_3 = fma(a_1[0], b_0[3], c_1_3);
c_1_4 = fma(a_1[0], b_0[4], c_1_4);
c_2_0 = fma(a_2[0], b_0[0], c_2_0);
c_2_1 = fma(a_2[0], b_0[1], c_2_1);
c_2_2 = fma(a_2[0], b_0[2], c_2_2);
c_2_3 = fma(a_2[0], b_0[3], c_2_3);
c_2_4 = fma(a_2[0], b_0[4], c_2_4);
c_3_0 = fma(a_3[0], b_0[0], c_3_0);
c_3_1 = fma(a_3[0], b_0[1], c_3_1);
c_3_2 = fma(a_3[0], b_0[2], c_3_2);
c_3_3 = fma(a_3[0], b_0[3], c_3_3);
c_3_4 = fma(a_3[0], b_0[4], c_3_4);
c_0_0 = fma(a_0[1], b_1[0], c_0_0);
c_0_1 = fma(a_0[1], b_1[1], c_0_1);
c_0_2 = fma(a_0[1], b_1[2], c_0_2);
c_0_3 = fma(a_0[1], b_1[3], c_0_3);
c_0_4 = fma(a_0[1], b_1[4], c_0_4);
c_1_0 = fma(a_1[1], b_1[0], c_1_0);
c_1_1 = fma(a_1[1], b_1[1], c_1_1);
c_1_2 = fma(a_1[1], b_1[2], c_1_2);
c_1_3 = fma(a_1[1], b_1[3], c_1_3);
c_1_4 = fma(a_1[1], b_1[4], c_1_4);
c_2_0 = fma(a_2[1], b_1[0], c_2_0);
c_2_1 = fma(a_2[1], b_1[1], c_2_1);
c_2_2 = fma(a_2[1], b_1[2], c_2_2);
c_2_3 = fma(a_2[1], b_1[3], c_2_3);
c_2_4 = fma(a_2[1], b_1[4], c_2_4);
c_3_0 = fma(a_3[1], b_1[0], c_3_0);
c_3_1 = fma(a_3[1], b_1[1], c_3_1);
c_3_2 = fma(a_3[1], b_1[2], c_3_2);
c_3_3 = fma(a_3[1], b_1[3], c_3_3);
c_3_4 = fma(a_3[1], b_1[4], c_3_4);
c_0_0 = fma(a_0[2], b_2[0], c_0_0);
c_0_1 = fma(a_0[2], b_2[1], c_0_1);
c_0_2 = fma(a_0[2], b_2[2], c_0_2);
c_0_3 = fma(a_0[2], b_2[3], c_0_3);
c_0_4 = fma(a_0[2], b_2[4], c_0_4);
c_1_0 = fma(a_1[2], b_2[0], c_1_0);
c_1_1 = fma(a_1[2], b_2[1], c_1_1);
c_1_2 = fma(a_1[2], b_2[2], c_1_2);
c_1_3 = fma(a_1[2], b_2[3], c_1_3);
c_1_4 = fma(a_1[2], b_2[4], c_1_4);
c_2_0 = fma(a_2[2], b_2[0], c_2_0);
c_2_1 = fma(a_2[2], b_2[1], c_2_1);
c_2_2 = fma(a_2[2], b_2[2], c_2_2);
c_2_3 = fma(a_2[2], b_2[3], c_2_3);
c_2_4 = fma(a_2[2], b_2[4], c_2_4);
c_3_0 = fma(a_3[2], b_2[0], c_3_0);
c_3_1 = fma(a_3[2], b_2[1], c_3_1);
c_3_2 = fma(a_3[2], b_2[2], c_3_2);
c_3_3 = fma(a_3[2], b_2[3], c_3_3);
c_3_4 = fma(a_3[2], b_2[4], c_3_4);
c_0_0 = fma(a_0[3], b_3[0], c_0_0);
c_0_1 = fma(a_0[3], b_3[1], c_0_1);
c_0_2 = fma(a_0[3], b_3[2], c_0_2);
c_0_3 = fma(a_0[3], b_3[3], c_0_3);
c_0_4 = fma(a_0[3], b_3[4], c_0_4);
c_1_0 = fma(a_1[3], b_3[0], c_1_0);
c_1_1 = fma(a_1[3], b_3[1], c_1_1);
c_1_2 = fma(a_1[3], b_3[2], c_1_2);
c_1_3 = fma(a_1[3], b_3[3], c_1_3);
c_1_4 = fma(a_1[3], b_3[4], c_1_4);
c_2_0 = fma(a_2[3], b_3[0], c_2_0);
c_2_1 = fma(a_2[3], b_3[1], c_2_1);
c_2_2 = fma(a_2[3], b_3[2], c_2_2);
c_2_3 = fma(a_2[3], b_3[3], c_2_3);
c_2_4 = fma(a_2[3], b_3[4], c_2_4);
c_3_0 = fma(a_3[3], b_3[0], c_3_0);
c_3_1 = fma(a_3[3], b_3[1], c_3_1);
c_3_2 = fma(a_3[3], b_3[2], c_3_2);
c_3_3 = fma(a_3[3], b_3[3], c_3_3);
c_3_4 = fma(a_3[3], b_3[4], c_3_4);
c_0_0 = fma(a_0[4], b_4[0], c_0_0);
c_0_1 = fma(a_0[4], b_4[1], c_0_1);
c_0_2 = fma(a_0[4], b_4[2], c_0_2);
c_0_3 = fma(a_0[4], b_4[3], c_0_3);
c_0_4 = fma(a_0[4], b_4[4], c_0_4);
c_1_0 = fma(a_1[4], b_4[0], c_1_0);
c_1_1 = fma(a_1[4], b_4[1], c_1_1);
c_1_2 = fma(a_1[4], b_4[2], c_1_2);
c_1_3 = fma(a_1[4], b_4[3], c_1_3);
c_1_4 = fma(a_1[4], b_4[4], c_1_4);
c_2_0 = fma(a_2[4], b_4[0], c_2_0);
c_2_1 = fma(a_2[4], b_4[1], c_2_1);
c_2_2 = fma(a_2[4], b_4[2], c_2_2);
c_2_3 = fma(a_2[4], b_4[3], c_2_3);
c_2_4 = fma(a_2[4], b_4[4], c_2_4);
c_3_0 = fma(a_3[4], b_4[0], c_3_0);
c_3_1 = fma(a_3[4], b_4[1], c_3_1);
c_3_2 = fma(a_3[4], b_4[2], c_3_2);
c_3_3 = fma(a_3[4], b_4[3], c_3_3);
c_3_4 = fma(a_3[4], b_4[4], c_3_4);
c_0_0 = fma(a_0[5], b_5[0], c_0_0);
c_0_1 = fma(a_0[5], b_5[1], c_0_1);
c_0_2 = fma(a_0[5], b_5[2], c_0_2);
c_0_3 = fma(a_0[5], b_5[3], c_0_3);
c_0_4 = fma(a_0[5], b_5[4], c_0_4);
c_1_0 = fma(a_1[5], b_5[0], c_1_0);
c_1_1 = fma(a_1[5], b_5[1], c_1_1);
c_1_2 = fma(a_1[5], b_5[2], c_1_2);
c_1_3 = fma(a_1[5], b_5[3], c_1_3);
c_1_4 = fma(a_1[5], b_5[4], c_1_4);
c_2_0 = fma(a_2[5], b_5[0], c_2_0);
c_2_1 = fma(a_2[5], b_5[1], c_2_1);
c_2_2 = fma(a_2[5], b_5[2], c_2_2);
c_2_3 = fma(a_2[5], b_5[3], c_2_3);
c_2_4 = fma(a_2[5], b_5[4], c_2_4);
c_3_0 = fma(a_3[5], b_5[0], c_3_0);
c_3_1 = fma(a_3[5], b_5[1], c_3_1);
c_3_2 = fma(a_3[5], b_5[2], c_3_2);
c_3_3 = fma(a_3[5], b_5[3], c_3_3);
c_3_4 = fma(a_3[5], b_5[4], c_3_4);
}
for (t *a = a0 + p/RBK*RBK, *b = b0 + p/RBK*RBK*ldb; a < a0 + p; a++, b += ldb)
{
t* a_0 = &a[lda*0];
t* a_1 = &a[lda*1];
t* a_2 = &a[lda*2];
t* a_3 = &a[lda*3];
t* b_0 = &b[ldb*0];
c_0_0 = fma(a_0[0], b_0[0], c_0_0);
c_0_1 = fma(a_0[0], b_0[1], c_0_1);
c_0_2 = fma(a_0[0], b_0[2], c_0_2);
c_0_3 = fma(a_0[0], b_0[3], c_0_3);
c_0_4 = fma(a_0[0], b_0[4], c_0_4);
c_1_0 = fma(a_1[0], b_0[0], c_1_0);
c_1_1 = fma(a_1[0], b_0[1], c_1_1);
c_1_2 = fma(a_1[0], b_0[2], c_1_2);
c_1_3 = fma(a_1[0], b_0[3], c_1_3);
c_1_4 = fma(a_1[0], b_0[4], c_1_4);
c_2_0 = fma(a_2[0], b_0[0], c_2_0);
c_2_1 = fma(a_2[0], b_0[1], c_2_1);
c_2_2 = fma(a_2[0], b_0[2], c_2_2);
c_2_3 = fma(a_2[0], b_0[3], c_2_3);
c_2_4 = fma(a_2[0], b_0[4], c_2_4);
c_3_0 = fma(a_3[0], b_0[0], c_3_0);
c_3_1 = fma(a_3[0], b_0[1], c_3_1);
c_3_2 = fma(a_3[0], b_0[2], c_3_2);
c_3_3 = fma(a_3[0], b_0[3], c_3_3);
c_3_4 = fma(a_3[0], b_0[4], c_3_4);
}
c_0[0] = c_0_0;
c_0[1] = c_0_1;
c_0[2] = c_0_2;
c_0[3] = c_0_3;
c_0[4] = c_0_4;
c_1[0] = c_1_0;
c_1[1] = c_1_1;
c_1[2] = c_1_2;
c_1[3] = c_1_3;
c_1[4] = c_1_4;
c_2[0] = c_2_0;
c_2[1] = c_2_1;
c_2[2] = c_2_2;
c_2[3] = c_2_3;
c_2[4] = c_2_4;
c_3[0] = c_3_0;
c_3[1] = c_3_1;
c_3[2] = c_3_2;
c_3[3] = c_3_3;
c_3[4] = c_3_4;
}

16
examples/C/simple/Makefile
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@ -1,16 +0,0 @@
TARGET = simple
$(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64d -mcmodel=medany \
-DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common \
-fno-builtin-printf -fno-tree-loop-distribute-patterns \
-static -nostdlib -nostartfiles -lm -lgcc -T../common/test.ld \
-I../common \
-O0 $(TARGET).c \
../common/crt.S ../common/syscalls.c comp1.s
clean:
rm -f $(TARGET) $(TARGET).objdump

10
examples/C/simple/comp1.s
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@ -1,10 +0,0 @@
.global _comp1
_comp1:
li a0, 42
ret

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40
examples/C/simple/simple.c
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@ -1,40 +0,0 @@
// simple.C
// David_Harris@hmc.edu 24 December 2021
// Simple illustration of compiling C code
//#include <stdio.h>
#include "util.h"
extern int printf(const char* fmt, ...);
extern int _comp1(void);
/*
long sum(long N) {
long result, i;
result = 0;
for (i=1; i<=N; i++) {
result = result + i;
}
return result;
int a;
asm volatile ("li s0, 10;");
asm volatile(
"li %0, 3;"
// "csrrs %0, 0xF14, zero" //CSSRS rd, mhartid, 0
: "=r"(a) //output
: //input
: //clobbered
);
return a;
}
*/
int main(void) {
int s[1], expected[1];
// s[0] = sum(4);
s[0] = _comp1();
printf("s = %d\n", s[0]);
expected[0] = 42;
return verify(1, s, expected); // 0 means success
}

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examples/C/simple/simple.dis
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35
examples/C/simple/simple_orig.c
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@ -1,35 +0,0 @@
// simple.C
// David_Harris@hmc.edu 24 December 2021
// Simple illustration of compiling C code
//#include <stdio.h>
#include "util.h"
extern int printf(const char* fmt, ...);
long sum(long N) {
/* long result, i;
result = 0;
for (i=1; i<=N; i++) {
result = result + i;
}
return result; */
int a;
// asm volatile ("li s0, 10;");
asm volatile(
"li %0, 10"
// "csrrs %0, 0xF14, zero" //CSSRS rd, mhartid, 0
: "=r"(a) //output
: //input
: //clobbered
);
return a;
}
int main(void) {
int s[1], expected[1];
s[0] = sum(4);
printf("s = %d\n", s[0]);
expected[0] = 10;
return verify(1, s, expected); // 0 means success
}

19
examples/C/sum/Makefile
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@ -1,27 +1,32 @@
TARGET = sum TARGET = sum
$(TARGET).objdump: $(TARGET) $(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S $(TARGET) > $(TARGET).objdump riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile $(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -g -O \ riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \ -march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostartfiles -T../common/test.ld -I../common \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \
$(TARGET).c ../common/crt.S ../common/syscalls.c $(TARGET).c ../common/crt.S ../common/syscalls.c
# Compiler flags: # Compiler flags:
# -o $(TARGET) defines the name of the output file # -o $(TARGET) defines the name of the output file
# -g generates debugging symbols for gdb # -g generates debugging symbols for gdb
# -O turns on basic optimization # -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits # -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
# -nostartfiles avoids inserting standard startup files because we are using crt.s # -static forces static linking (no dynamic shared libraries on bare metal)
# -lm links the math library if necessary (when #include math.h)
# -nostdlib avoids inserting standard startup files and default libraries
# because we are using crt.s on bare metal
# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library
# -T specifies the linker file # -T specifies the linker file
# -I specifies the include path (e.g. for util.h) # -I specifies the include path (e.g. for util.h)
# The last line defines the C files to compile. # The last line defines the C files to compile.
# crt.S is needed as our startup file to initialize the processor # crt.S is needed as our startup file to initialize the processor
# syscalls.c implements printf through the HTIF for Spike # syscalls.c implements printf through the HTIF for Spike
# other flags from riscv-tests makefiles that don't seem to be important # other flags from riscv-tests makefiles that don't seem to be important
# -ffast-math -DPREALLOCATE=1 -std=gnu99 -fno-tree-loop-distribute-patterns # -ffast-math -DPREALLOCATE=1 -std=gnu99 \
# -fno-common -static -fno-builtin-printf -nostdlib -lm -lgcc # -fno-common -fno-builtin-printf -nostartfiles -lgcc \
clean: clean:
rm -f $(TARGET) $(TARGET).objdump rm -f $(TARGET) $(TARGET).objdump

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4
examples/C/sum/sum.c
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@ -1,4 +1,4 @@
// sum.C // sum.c
// David_Harris@hmc.edu 24 December 2021 // David_Harris@hmc.edu 24 December 2021
// Simple illustration of compiling C code // Simple illustration of compiling C code
@ -16,7 +16,9 @@ long sum(long N) {
int main(void) { int main(void) {
int s[1], expected[1]; int s[1], expected[1];
setStats(1);
s[0] = sum(4); s[0] = sum(4);
setStats(0);
printf("s = %d\n", s[0]); printf("s = %d\n", s[0]);
expected[0] = 10; expected[0] = 10;
return verify(1, s, expected); // 0 means success return verify(1, s, expected); // 0 means success

32
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@ -0,0 +1,32 @@
TARGET = sum_mixed
$(TARGET).objdump: $(TARGET)
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
$(TARGET): $(TARGET).c Makefile
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
-march=rv64gc -mabi=lp64d -mcmodel=medany \
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-T../common/test.ld -I../common \
$(TARGET).c ../common/crt.S ../common/syscalls.c ../../asm/sumtest/sum.S
# Compiler flags:
# -o $(TARGET) defines the name of the output file
# -g generates debugging symbols for gdb
# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
# -static forces static linking (no dynamic shared libraries on bare metal)
# -lm links the math library if necessary (when #include math.h)
# -nostdlib avoids inserting standard startup files and default libraries
# because we are using crt.s on bare metal
# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library
# -T specifies the linker file
# -I specifies the include path (e.g. for util.h)
# The last line defines the C files to compile.
# crt.S is needed as our startup file to initialize the processor
# syscalls.c implements printf through the HTIF for Spike
# other flags from riscv-tests makefiles that don't seem to be important
# -ffast-math -DPREALLOCATE=1 -std=gnu99 \
# -fno-common -fno-builtin-printf -nostartfiles -lgcc \
clean:
rm -f $(TARGET) $(TARGET).objdump

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examples/C/sum_mixed/sum_mixed.c Normal file
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// sum_mixed.c
// David_Harris@hmc.edu 12 January 2022
// Call assembly language from C
#include <stdio.h>
#include "util.h"
extern int sum(int);
int main(void) {
int s[1], expected[1];
setStats(1);
s[0] = sum(4);
setStats(0);
printf("s = %d\n", s[0]);
expected[0] = 10;
return verify(1, s, expected); // 0 means success
}

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vsim -c -do srt.do

2
pipelined/srt/srt.do
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@ -17,7 +17,7 @@ if [file exists work] {
} }
vlib work vlib work
vlog srt.sv vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv
vopt +acc work.testbench -o workopt vopt +acc work.testbench -o workopt
vsim workopt vsim workopt

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pipelined/srt/srt.sv
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@ -1,65 +1,113 @@
/////////////////////////////////////////////////////// ///////////////////////////////////////////
// srt.sv // // srt.sv
// // //
// Written 10/31/96 by David Harris harrisd@leland // // Written: David_Harris@hmc.edu 13 January 2022
// Updated 10/19/21 David_Harris@hmc.edu // // Modified:
// // //
// This file models a simple Radix 2 SRT divider. // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
// // //
/////////////////////////////////////////////////////// // A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// MIT LICENSE
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
// to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
// OR OTHER DEALINGS IN THE SOFTWARE.
////////////////////////////////////////////////////////////////////////////////////////////////
// This Verilog file models a radix 2 SRT divider which `include "wally-config.vh"
// produces one quotient digit per cycle. The divider
// keeps the partial remainder in carry-save form.
///////// module srt #(parameter Nf=52) (
// srt // input logic clk,
///////// input logic Start,
module srt(input logic clk, input logic Stall, // *** multiple pipe stages
input logic req, input logic Flush, // *** multiple pipe stages
input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b // Floating Point Inputs
input logic [51:0] a, b, // later add exponents, signs, special cases
output logic [54:0] rp, rm); input logic [Nf-1:0] SrcXFrac, SrcYFrac,
input logic [`XLEN-1:0] SrcA, SrcB,
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
input logic W64, // 32-bit ints on XLEN=64
input logic Signed, // Interpret integers as signed 2's complement
input logic Int, // Choose integer inputss
input logic Sqrt, // perform square root, not divide
output logic [Nf-1:0] Quot, Rem, // *** later handle integers
output logic [3:0] Flags
);
// A simple Radix 2 SRT divider/sqrt
// Internal signals
logic [55:0] ps, pc; // partial remainder in carry-save form
logic [55:0] d; // divisor
logic [55:0] psa, pca; // partial remainder result of csa
logic [55:0] psn, pcn; // partial remainder for next cycle
logic [55:0] dn; // divisor for next cycle
logic [55:0] dsel; // selected divisor multiple
logic qp, qz, qm; // quotient is +1, 0, or -1 logic qp, qz, qm; // quotient is +1, 0, or -1
logic [55:0] d_b; // inverse of divisor logic [Nf-1:0] X, Dpreproc;
logic [Nf+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
logic [Nf+2:0] rp, rm;
srtpreproc #(Nf) preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc);
// Top Muxes and Registers // Top Muxes and Registers
// When start is asserted, the inputs are loaded into the divider. // When start is asserted, the inputs are loaded into the divider.
// Otherwise, the divisor is retained and the partial remainder // Otherwise, the divisor is retained and the partial remainder
// is fed back for the next iteration. // is fed back for the next iteration.
mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn); mux2 #(Nf+4) wsmux({WSA[54:0], 1'b0}, {4'b0001, X}, Start, WSN);
flop psflop(clk, psn, ps); flop #(Nf+4) wsflop(clk, WSN, WS);
mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn); mux2 #(Nf+4) wcmux({WCA[54:0], 1'b0}, 56'b0, Start, WCN);
flop pcflop(clk, pcn, pc); flop #(Nf+4) wcflop(clk, WCN, WC);
mux2 dmux(d, {4'b0001, b}, req, dn); flopen #(Nf+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
flop dflop(clk, dn, d);
// Quotient Selection logic // Quotient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// Accumulate quotient digits in a shift register // Accumulate quotient digits in a shift register
qsel qsel(ps[55:52], pc[55:52], qp, qz, qm); qsel #(Nf) qsel(WS[55:52], WC[55:52], qp, qz, qm);
qacc qacc(clk, req, qp, qz, qm, rp, rm); qacc #(Nf+3) qacc(clk, Start, qp, qz, qm, rp, rm);
// Divisor Selection logic // Divisor Selection logic
inv dinv(d, d_b); inv dinv(D, Db);
mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel); mux3onehot divisorsel(Db, 56'b0, D, qp, qz, qm, Dsel);
// Partial Product Generation // Partial Product Generation
csa csa(ps, pc, dsel, qp, psa, pca); csa csa(WS, WC, Dsel, qp, WSA, WCA);
srtpostproc postproc(rp, rm, Quot);
endmodule endmodule
module srtpostproc #(parameter N=52) (
input [N+2:0] rp, rm,
output [N-1:0] Quot
);
//assign Quot = rp - rm;
finaladd finaladd(rp, rm, Quot);
endmodule
module srtpreproc #(parameter Nf=52) (
input logic [`XLEN-1:0] SrcA, SrcB,
input logic [Nf-1:0] SrcXFrac, SrcYFrac,
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
input logic W64, // 32-bit ints on XLEN=64
input logic Signed, // Interpret integers as signed 2's complement
input logic Int, // Choose integer inputss
input logic Sqrt, // perform square root, not divide
output logic [Nf-1:0] X, D
);
// Initial: just pass X and Y through for simple fp division
assign X = SrcXFrac;
assign D = SrcYFrac;
endmodule
/*
////////// //////////
// mux2 // // mux2 //
////////// //////////
@ -86,13 +134,17 @@ module flop(clk, in, out);
assign #1 out = state; assign #1 out = state;
endmodule endmodule
*/
////////// //////////
// qsel // // qsel //
////////// //////////
module qsel(input logic [55:52] ps, pc, module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits
output logic qp, qz, qm); input logic [Nf+3:Nf] ps, pc,
output logic qp, qz, qm
);
logic [55:52] p, g; logic [Nf+3:Nf] p, g;
logic magnitude, sign, cout; logic magnitude, sign, cout;
// The quotient selection logic is presented for simplicity, not // The quotient selection logic is presented for simplicity, not
@ -122,19 +174,16 @@ endmodule
////////// //////////
// qacc // // qacc //
////////// //////////
module qacc(clk, req, qp, qz, qm, rp, rm); module qacc #(parameter N=55) (
input clk; input logic clk,
input req; input logic req,
input qp; input logic qp, qz, qm,
input qz; output logic [N-1:0] rp, rm
input qm; );
output [54:0] rp;
output [54:0] rm;
logic [54:0] rp, rm; // quotient bit is +/- 1; flopr #(N) rmreg(clk, req, {rm[53:0], qm}, rm);
logic [7:0] count; flopr #(N) rpreg(clk, req, {rp[53:0], qp}, rp);
/* always @(posedge clk)
always @(posedge clk)
begin begin
if (req) if (req)
begin begin
@ -143,10 +192,10 @@ module qacc(clk, req, qp, qz, qm, rp, rm);
end end
else else
begin begin
rp <= #1 {rp[54:0], qp};
rm <= #1 {rm[54:0], qm}; rm <= #1 {rm[54:0], qm};
rp <= #1 {rp[54:0], qp};
end end
end end */
endmodule endmodule
///////// /////////
@ -161,7 +210,7 @@ endmodule
////////// //////////
// mux3 // // mux3 //
////////// //////////
module mux3(in0, in1, in2, sel0, sel1, sel2, out); module mux3onehot(in0, in1, in2, sel0, sel1, sel2, out);
input [55:0] in0; input [55:0] in0;
input [55:0] in1; input [55:0] in1;
input [55:0] in2; input [55:0] in2;
@ -175,16 +224,15 @@ module mux3(in0, in1, in2, sel0, sel1, sel2, out);
assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2); assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2);
endmodule endmodule
///////// /////////
// csa // // csa //
///////// /////////
module csa(in1, in2, in3, cin, out1, out2); module csa #(parameter N=56) (
input [55:0] in1; input logic [N-1:0] in1, in2, in3,
input [55:0] in2; input logic cin,
input [55:0] in3; output logic [N-1:0] out1, out2
input cin; );
output [55:0] out1;
output [55:0] out2;
// This block adds in1, in2, in3, and cin to produce // This block adds in1, in2, in3, and cin to produce
// a result out1 / out2 in carry-save redundant form. // a result out1 / out2 in carry-save redundant form.
@ -202,10 +250,10 @@ endmodule
////////////// //////////////
// finaladd // // finaladd //
////////////// //////////////
module finaladd(rp, rm, r); module finaladd(
input [54:0] rp; input logic [54:0] rp, rm,
input [54:0] rm; output logic [51:0] r
output [51:0] r; );
logic [54:0] diff; logic [54:0] diff;
@ -284,14 +332,16 @@ module testbench;
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
// bit field of an array // bit field of an array
logic [51:0] correctr, nextr; logic [51:0] correctr, nextr, diffn, diffp;
integer testnum, errors; integer testnum, errors;
// Divider // Divider
srt srt(clk, req, a, b, rp, rm); srt #(52) srt(.clk, .Start(req),
.Stall(1'b0), .Flush(1'b0),
// Final adder converts quotient digits to 2's complement & normalizes .SrcXFrac(a), .SrcYFrac(b),
finaladd finaladd(rp, rm, r); .SrcA('0), .SrcB('0), .Fmt(2'b00),
.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
.Quot(r), .Rem(), .Flags());
// Counter // Counter
counter counter(clk, req, done); counter counter(clk, req, done);
@ -325,16 +375,18 @@ module testbench;
if (done) if (done)
begin begin
req <= #5 1; req <= #5 1;
$display("result was %h, should be %h\n", r, correctr); diffp = correctr - r;
if ((correctr - r) > 1) // check if accurate to 1 ulp diffn = r - correctr;
if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
begin begin
errors = errors+1; errors = errors+1;
$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
$display("failed\n"); $display("failed\n");
$stop; $stop;
end end
if (a === 52'hxxxxxxxxxxxxx) if (a === 52'hxxxxxxxxxxxxx)
begin begin
$display("Tests completed successfully"); $display("%d Tests completed successfully", testnum);
$stop; $stop;
end end
end end

355
pipelined/srt/srt_stanford.sv Normal file
View File

@ -0,0 +1,355 @@
///////////////////////////////////////////////////////
// srt.sv //
// //
// Written 10/31/96 by David Harris harrisd@leland //
// Updated 10/19/21 David_Harris@hmc.edu //
// //
// This file models a simple Radix 2 SRT divider. //
// //
///////////////////////////////////////////////////////
// This Verilog file models a radix 2 SRT divider which
// produces one quotient digit per cycle. The divider
// keeps the partial remainder in carry-save form.
/////////
// srt //
/////////
module srt(input logic clk,
input logic req,
input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b
input logic [51:0] a, b,
output logic [54:0] rp, rm);
// A simple Radix 2 SRT divider/sqrt
// Internal signals
logic [55:0] ps, pc; // partial remainder in carry-save form
logic [55:0] d; // divisor
logic [55:0] psa, pca; // partial remainder result of csa
logic [55:0] psn, pcn; // partial remainder for next cycle
logic [55:0] dn; // divisor for next cycle
logic [55:0] dsel; // selected divisor multiple
logic qp, qz, qm; // quotient is +1, 0, or -1
logic [55:0] d_b; // inverse of divisor
// Top Muxes and Registers
// When start is asserted, the inputs are loaded into the divider.
// Otherwise, the divisor is retained and the partial remainder
// is fed back for the next iteration.
mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn);
flop psflop(clk, psn, ps);
mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn);
flop pcflop(clk, pcn, pc);
mux2 dmux(d, {4'b0001, b}, req, dn);
flop dflop(clk, dn, d);
// Quotient Selection logic
// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
// Accumulate quotient digits in a shift register
qsel qsel(ps[55:52], pc[55:52], qp, qz, qm);
qacc qacc(clk, req, qp, qz, qm, rp, rm);
// Divisor Selection logic
inv dinv(d, d_b);
mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel);
// Partial Product Generation
csa csa(ps, pc, dsel, qp, psa, pca);
endmodule
//////////
// mux2 //
//////////
module mux2(input logic [55:0] in0, in1,
input logic sel,
output logic [55:0] out);
assign #1 out = sel ? in1 : in0;
endmodule
//////////
// flop //
//////////
module flop(clk, in, out);
input clk;
input [55:0] in;
output [55:0] out;
logic [55:0] state;
always @(posedge clk)
state <= #1 in;
assign #1 out = state;
endmodule
//////////
// qsel //
//////////
module qsel(input logic [55:52] ps, pc,
output logic qp, qz, qm);
logic [55:52] p, g;
logic magnitude, sign, cout;
// The quotient selection logic is presented for simplicity, not
// for efficiency. You can probably optimize your logic to
// select the proper divisor with less delay.
// Quotient equations from EE371 lecture notes 13-20
assign p = ps ^ pc;
assign g = ps & pc;
assign #1 magnitude = ~(&p[54:52]);
assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
assign #1 sign = p[55] ^ cout;
/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
(ps[52]^pc[52]));
assign #1 sign = (ps[55]^pc[55])^
(ps[54] & pc[54] | ((ps[54]^pc[54]) &
(ps[53]&pc[53] | ((ps[53]^pc[53]) &
(ps[52]&pc[52]))))); */
// Produce quotient = +1, 0, or -1
assign #1 qp = magnitude & ~sign;
assign #1 qz = ~magnitude;
assign #1 qm = magnitude & sign;
endmodule
//////////
// qacc //
//////////
module qacc(clk, req, qp, qz, qm, rp, rm);
input clk;
input req;
input qp;
input qz;
input qm;
output [54:0] rp;
output [54:0] rm;
logic [54:0] rp, rm; // quotient bit is +/- 1;
logic [7:0] count;
always @(posedge clk)
begin
if (req)
begin
rp <= #1 0;
rm <= #1 0;
end
else
begin
rp <= #1 {rp[54:0], qp};
rm <= #1 {rm[54:0], qm};
end
end
endmodule
/////////
// inv //
/////////
module inv(input logic [55:0] in,
output logic [55:0] out);
assign #1 out = ~in;
endmodule
//////////
// mux3 //
//////////
module mux3(in0, in1, in2, sel0, sel1, sel2, out);
input [55:0] in0;
input [55:0] in1;
input [55:0] in2;
input sel0;
input sel1;
input sel2;
output [55:0] out;
// lazy inspection of the selects
// really we should make sure selects are mutually exclusive
assign #1 out = sel0 ? in0 : (sel1 ? in1 : in2);
endmodule
/////////
// csa //
/////////
module csa(in1, in2, in3, cin, out1, out2);
input [55:0] in1;
input [55:0] in2;
input [55:0] in3;
input cin;
output [55:0] out1;
output [55:0] out2;
// This block adds in1, in2, in3, and cin to produce
// a result out1 / out2 in carry-save redundant form.
// cin is just added to the least significant bit and
// is required to handle adding a negative divisor.
// Fortunately, the carry (out2) is shifted left by one
// bit, leaving room in the least significant bit to
// insert cin.
assign #1 out1 = in1 ^ in2 ^ in3;
assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) |
(in2[54:0] & in3[54:0]), cin};
endmodule
//////////////
// finaladd //
//////////////
module finaladd(rp, rm, r);
input [54:0] rp;
input [54:0] rm;
output [51:0] r;
logic [54:0] diff;
// this magic block performs the final addition for you
// to convert the positive and negative quotient digits
// into a normalized mantissa. It returns the 52 bit
// mantissa after shifting to guarantee a leading 1.
// You can assume this block operates in one cycle
// and do not need to budget it in your area and power
// calculations.
// Since no rounding is performed, the result may be too
// small by one unit in the least significant place (ulp).
// The checker ignores such an error.
assign #1 diff = rp - rm;
assign #1 r = diff[54] ? diff[53:2] : diff[52:1];
endmodule
/////////////
// counter //
/////////////
module counter(input logic clk,
input logic req,
output logic done);
logic [5:0] count;
// This block of control logic sequences the divider
// through its iterations. You may modify it if you
// build a divider which completes in fewer iterations.
// You are not responsible for the (trivial) circuit
// design of the block.
always @(posedge clk)
begin
if (count == 54) done <= #1 1;
else if (done | req) done <= #1 0;
if (req) count <= #1 0;
else count <= #1 count+1;
end
endmodule
///////////
// clock //
///////////
module clock(clk);
output clk;
// Internal clk signal
logic clk;
endmodule
//////////
// testbench //
//////////
module testbench;
logic clk;
logic req;
logic done;
logic [51:0] a;
logic [51:0] b;
logic [51:0] r;
logic [54:0] rp, rm; // positive quotient digits
// Test parameters
parameter MEM_SIZE = 40000;
parameter MEM_WIDTH = 52+52+52;
`define memr 51:0
`define memb 103:52
`define mema 155:104
// Test logicisters
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a
// bit field of an array
logic [51:0] correctr, nextr;
integer testnum, errors;
// Divider
srt srt(clk, req, a, b, rp, rm);
// Final adder converts quotient digits to 2's complement & normalizes
finaladd finaladd(rp, rm, r);
// Counter
counter counter(clk, req, done);
initial
forever
begin
clk = 1; #17;
clk = 0; #16;
end
// Read test vectors from disk
initial
begin
testnum = 0;
errors = 0;
$readmemh ("testvectors", Tests);
Vec = Tests[testnum];
a = Vec[`mema];
b = Vec[`memb];
nextr = Vec[`memr];
req <= #5 1;
end
// Apply directed test vectors read from file.
always @(posedge clk)
begin
if (done)
begin
req <= #5 1;
$display("result was %h, should be %h\n", r, correctr);
if ((correctr - r) > 1) // check if accurate to 1 ulp
begin
errors = errors+1;
$display("failed\n");
$stop;
end
if (a === 52'hxxxxxxxxxxxxx)
begin
$display("Tests completed successfully");
$stop;
end
end
if (req)
begin
req <= #5 0;
correctr = nextr;
testnum = testnum+1;
Vec = Tests[testnum];
$display("a = %h b = %h",a,b);
a = Vec[`mema];
b = Vec[`memb];
nextr = Vec[`memr];
end
end
endmodule