From 7d0462dc595982dea6dcbe100e550b9d05c35eb3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 12 Apr 2022 17:56:36 -0500 Subject: [PATCH] UART and clock speed changes to support 30Mhz. --- fpga/generator/xlnx_ddr4.tcl | 2 +- pipelined/src/uncore/uartPC16550D.sv | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl index e04f0e465..dd9e4d31d 100644 --- a/fpga/generator/xlnx_ddr4.tcl +++ b/fpga/generator/xlnx_ddr4.tcl @@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {35} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 31e558cfc..a6e2dd71d 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -143,7 +143,9 @@ module uartPC16550D( LSR <= #1 8'b01100000; MSR <= #1 4'b0; if (`FPGA) begin - DLL <= #1 8'd38; + //DLL <= #1 8'd38; // 35Mhz + //DLL <= #1 8'd11; // 10 Mhz + DLL <= #1 8'd33; // 30 Mhz DLM <= #1 8'b0; end else begin DLL <= #1 8'd1; // this cannot be zero with DLM also zer0. @@ -161,7 +163,9 @@ module uartPC16550D( -----/\----- EXCLUDED -----/\----- */ // *** BUG FIX ME for now for the divider to be 38. Our clock is 35 Mhz. 35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud // freq /baud / 16 = div - 3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section + //3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section + //3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in + 3'b000: if (DLAB) DLL <= #1 8'd33; //else TXHR <= #1 Din; // TX handled in 3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0]; 3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing