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	initial commit pmp basic coverage working
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							@ -29,8 +29,8 @@ print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim
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# Validate arguments
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					# Validate arguments
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if (args.gui):
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					if (args.gui):
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    if (args.sim != "questa"):
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					    if args.sim not in ["questa", "vcs"]:
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        print("GUI option only supported for Questa")
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					        print("GUI option only supported for Questa and VCS")
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        exit(1)
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					        exit(1)
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if (args.coverage):
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					if (args.coverage):
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@ -83,8 +83,8 @@ elif (args.sim == "vcs"):
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        print("Coverage option not available for VCS")
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					        print("Coverage option not available for VCS")
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        exit(1)
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					        exit(1)
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    if (args.gui):  
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					    if (args.gui):  
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        print("GUI option not available for VCS")
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					        cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.tb + " " + "1"
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        exit(1)
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					    os.system(cmd)
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    cmd = cd + "; ./run_vcs " + args.config + " " + "\""+args.testsuite+"\""
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					    cmd = cd + "; ./run_vcs " + args.config + " " + "\""+args.testsuite+"\""
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    print(cmd)
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					    print(cmd)
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    os.system(cmd)
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					    os.system(cmd)
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@ -97,7 +97,7 @@ if {$argc >= 3} {
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# "Extra checking for conflicts with always_comb done at vopt time"
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					# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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					# because vsim will run vopt
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vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv  ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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					vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${TB}/coverage/test_pmp_coverage.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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					# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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					# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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@ -12,7 +12,26 @@ TB=${WALLY}/testbench
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CONFIG_VARIANT=${1}
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					CONFIG_VARIANT=${1}
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# Set TESTSUITE from the second script argument
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					# Set TESTSUITE from the second script argument
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TESTSUITE=$2
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					TESTSUITE=$2
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					WKDIR=wkdir/${1}_${2}
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					if [ ! -d "$WKDIR" ]; then
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					    #echo "Directory $WKDIR does not exist. Creating it now..."
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					    mkdir -p "$WKDIR"
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					    if [ $? -eq 0 ]; then
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					        echo "Directory $WKDIR created successfully."
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					    else
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					        echo "Failed to create directory $WKDIR."
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					        exit 1
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					    fi
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					else
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					    echo "Directory $WKDIR already exists."
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					fi
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					if [[ -n "$4" ]]; then
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					    GUI="-gui"
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					else
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					    GUI=""
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					fi
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INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
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					INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
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SOURCE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" 
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					SOURCE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}" 
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@ -21,14 +40,12 @@ SIMFILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clock
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OUTPUT="sim_out"
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					OUTPUT="sim_out"
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clean() {
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					clean() {
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    rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
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					    rm -rf ${WKDIR}/*
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    rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
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}
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					}
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# Clean and run simulation with VCS
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					# Clean and run simulation with VCS
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clean
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					clean
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#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
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					#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
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# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO]
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					# lint ignores Unused Inputs (UI), Unnamed Assertipons (SVA-UA), Dynamic Type Sensitivty [IDTS], Null Statement [NS], Unequal Length in Comparison Operation [ULCO]
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vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse  ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
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					vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU -simprofile -suppress -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse  ${SOURCE_PATH} $SIMFILES -o ${WKDIR}/$OUTPUT  -simdir ${WKDIR} -error=NOODV -work ${WKDIR} ${GUI}
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./$OUTPUT | tee program.out
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					./${WKDIR}/$OUTPUT +TEST=${TESTSUITE}  +fsdb+gate=off  | tee ${WKDIR}/${WKDIR}.out 
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										108
									
								
								testbench/coverage/test_pmp_coverage.sv
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										108
									
								
								testbench/coverage/test_pmp_coverage.sv
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,108 @@
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					module test_pmp_coverage import cvw::*; #(parameter cvw_t P) (input clk);
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					// Ensure the covergroup is defined correctly
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					covergroup cg_priv_mode @(posedge clk);
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					    coverpoint dut.core.ifu.PrivilegeModeW {
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					        bins user   = {2'b00};
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					        bins superv = {2'b01};
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					        bins hyperv = {2'b10};
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					        bins mach   = {2'b11};
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					    }
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					endgroup
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					covergroup cg_PMPConfig @(posedge clk);
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					    coverpoint dut.core.ifu.PMPCFG_ARRAY_REGW[0][0] {
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					        bins ones    = {1};
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					        bins zeros = {0};
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					    }
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					endgroup
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					function bit [1:0] getPMPConfigSlice(int index);
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					    return dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[index][4:3];
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					endfunction
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					//if (P.PMP_ENTRIES > 0) begin : pmp
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					    covergroup cg_pmpcfg_mode @(posedge clk);
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[0][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[1][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[2][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[3][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[4][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[5][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[6][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[7][4:3] {
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					                bins off   = {2'b00};
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					                bins tor   = {2'b01};
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					                bins na4   = {2'b10};
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					                bins napot = {2'b11};
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					            }
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					    endgroup
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					//end
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					// Ensure that the instantiation and sampling of covergroups are within the correct procedural context
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					initial begin
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					    cg_priv_mode privmodeCG = new();  // Instantiate the privilege mode covergroup
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					    cg_PMPConfig pmpconfigCG = new(); // Instantiate the PMP config covergroup
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					    cg_pmpcfg_mode pmpcfgmodeCG = new();
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					    forever begin
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					        @(posedge clk) begin
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					            privmodeCG.sample();  // Sample the privilege mode covergroup
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					            pmpconfigCG.sample(); // Sample the PMP config covergroupi
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						    pmpcfgmodeCG.sample();
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					        end
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					    end
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					end
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					endmodule
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