From 6a905aa2f2d06274a41b15b1f349585a28aa0b06 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 10 Oct 2024 17:14:27 -0500 Subject: [PATCH 001/232] Possible start to resolution on issue #839. --- src/mmu/hptw.sv | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 7a0d2c4a6..daed5dde5 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -274,23 +274,23 @@ module hptw import cvw::*; #(parameter cvw_t P) ( IDLE: if (TLBMissOrUpdateDA) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // First access in SV48 - L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; - L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; - L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; - L0_RD: if (DCacheBusStallM) NextWalkerState = L0_RD; - else if (HPTWFaultM) NextWalkerState = FAULT; + L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; + else if (DCacheBusStallM) NextWalkerState = L0_RD; else NextWalkerState = LEAF; LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; From fe5f342d2f282c5a307e6bbcb13b3917ed0ee9c3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 12:07:26 -0500 Subject: [PATCH 002/232] Does not work. But there is a bug hiding the IgnoreRequest confusion. --- src/lsu/lsu.sv | 4 ++-- src/mmu/hptw.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index bc8852cf4..a068bf172 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -342,7 +342,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .FetchBuffer, .CacheBusRW(CacheBusRWTemp), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); - assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; + assign DCacheStallM = CacheStall; assign CacheBusRW = CacheBusRWTemp; ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( @@ -386,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign {DCacheStallM, DCacheCommittedM} = '0; end - assign LSUBusStallM = BusStall & ~IgnoreRequestTLB; + assign LSUBusStallM = BusStall; ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index daed5dde5..ee22e3a70 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -300,7 +300,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); From 7a92d41ef5d2e70524567559385e3a430b4488c0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 14:41:52 -0500 Subject: [PATCH 003/232] Simplified logic around IgnoreRequest and HPTWFaultM. --- src/lsu/lsu.sv | 18 +++++------------- src/mmu/hptw.sv | 7 +++++-- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index a068bf172..51f4d9d6e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -110,7 +110,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic BusStall; // Bus interface busy with multicycle operation logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB logic HPTWStall; // HPTW busy with multicycle operation logic DCacheBusStallM; // Cache or bus stall @@ -309,8 +308,6 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11) logic FlushDCache; // Suppress d cache flush if there is an ITLB miss. - logic CacheStall; - logic [1:0] CacheBusRWTemp; logic BusCMOZero; logic [3:0] CacheCMOpM; logic BusAtomic; @@ -336,15 +333,12 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .WriteData(LSUWriteDataSpillM), .SelHPTW, - .CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), + .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), - .FetchBuffer, .CacheBusRW(CacheBusRWTemp), + .FetchBuffer, .CacheBusRW(CacheBusRW), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); - assign DCacheStallM = CacheStall; - assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), @@ -353,7 +347,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusAtomic, .BusCMOZero, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW), - .BusStall, .BusCommitted(BusCommittedM)); + .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM)); mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}), .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}), @@ -369,7 +363,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), - .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); // Mux between the 2 sources of read data, 0: Bus, 1: DTIM if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]); @@ -381,12 +375,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; assign DCacheReadDataWordM = '0; assign ReadDataWordMuxM = DTIMReadDataWordM; - assign {BusStall, BusCommittedM} = '0; + assign {LSUBusStallM, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM} = '0; end - - assign LSUBusStallM = BusStall; ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index ee22e3a70..deb89b285 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -105,6 +105,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic TakeHPTWFault; logic PBMTFaultM; logic HPTWFaultM; + logic ResetPTE; // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; @@ -143,7 +144,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // State flops flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE; - flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache + flopenr #(P.XLEN) PTEReg(clk, ResetPTE, PRegEn, NextPTE, PTE); // Capture page table entry from data cache // Assign PTE descriptors common across all XLEN values // For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table @@ -300,7 +301,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); // If hptw request has pmp/a fault suppress bus access. + assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | + ((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. + assign ResetPTE = reset | (WalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); From 37d3db916b6302cef1bd324866d076db316e54b3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 15:31:20 -0500 Subject: [PATCH 004/232] Resolved the HPTW's not taking the PBMT fault on the right cycle by having the fsm branch to fault on any cycle a HPTWFaultM occurs. This of course changes the figure in the book but it really relevant to PBMT. This appeared to work because the HPTW happened to also generate an access fault at the end of the walk and the logic produced both faults. I wrote new test which confirms just the one is generated. --- src/mmu/hptw.sv | 15 ++-- tests/coverage/nonleafpmbtfault.S | 143 ++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+), 5 deletions(-) create mode 100644 tests/coverage/nonleafpmbtfault.S diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index deb89b285..e48bf85dd 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -278,17 +278,20 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L0_RD; @@ -302,8 +305,10 @@ module hptw import cvw::*; #(parameter cvw_t P) ( endcase // case (WalkerState) assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | - ((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. - assign ResetPTE = reset | (WalkerState == IDLE); + //((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. + (WalkerState != IDLE & HPTWFaultM); + + assign ResetPTE = reset | (NextWalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); diff --git a/tests/coverage/nonleafpmbtfault.S b/tests/coverage/nonleafpmbtfault.S new file mode 100644 index 000000000..8a580ce02 --- /dev/null +++ b/tests/coverage/nonleafpmbtfault.S @@ -0,0 +1,143 @@ +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate +// a load or store/amo page fault based on the original access type. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t2, 0x1000 + li t0, 0x8000001000 + + lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. + li t1, 0x00008067 + add t0, t0, t2 + sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. + + fence.I + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 + .8byte 0x200044C1 + +.align 12 + .8byte 0x40000040200048C1 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF + .8byte 0x200008CF + .8byte 0x20000CCF + + .8byte 0x200010CF + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x2000A0CF + .8byte 0x2000A4CF + .8byte 0x2000A8CF + .8byte 0x2000ACCF + + .8byte 0x2000B0CF + .8byte 0x2000B4CF + .8byte 0x2000B8CF + .8byte 0x2000BCCF + + .8byte 0x2000C0CF + .8byte 0x2000C4CF + .8byte 0x2000C8CF + .8byte 0x2000CCCF + + .8byte 0x2000D0CF + .8byte 0x2000D4CF From 4c7eb1d11f4c863753730f36063e7991356ab363 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 15:41:40 -0500 Subject: [PATCH 005/232] Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW. --- src/lsu/atomic.sv | 4 ++-- src/lsu/lsu.sv | 22 +++++++++++----------- src/mmu/hptw.sv | 6 ++---- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 9c37b636c..8ad9159ce 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -39,7 +39,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal - input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation + input logic LSUFlushW, // On FlushM or TLB miss ignore memory operation output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data output logic SquashSCW, // Store conditional failed disable write to GPR output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC @@ -57,7 +57,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( // LRSC unit if (P.ZALRSC_SUPPORTED) begin - assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; + assign MemReadM = PreLSURWM[1] & ~LSUFlushW; lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); end else begin assign SquashSCW = 0; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 51f4d9d6e..08e62f9ad 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -110,7 +110,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB + logic LSUBusStallM; // Bus interface busy with multicycle operation masked by HPTWFlushW logic HPTWStall; // HPTW busy with multicycle operation logic DCacheBusStallM; // Cache or bus stall logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall @@ -145,8 +145,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic DTLBWriteM; // Writes PTE and PageType to DTLB logic LSULoadAccessFaultM; // Load acces fault logic LSUStoreAmoAccessFaultM; // Store access fault - logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle - logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation + logic HPTWFlushW; // HPTW needs to flush operation + logic LSUFlushW; // HPTW or hazard unit flushes operation logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; @@ -199,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IHAdrM, .HPTWStall, .SelHPTW, - .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, + .HPTWFlushW, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF ); @@ -214,7 +214,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, HPTWFlushW} = '0; assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; end @@ -273,7 +273,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Pause IEU memory request if TLB miss. After TLB fill, replay request. // Discard memory request on pipeline flush - assign IgnoreRequest = IgnoreRequestTLB | FlushW; + assign LSUFlushW = HPTWFlushW | FlushW; if (P.DTIM_SUPPORTED) begin : dtim logic [P.PA_BITS-1:0] DTIMAdr; @@ -284,7 +284,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DTIMMemRWM = SelDTIM ? LSURWM : 0; dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), - .DTIMAdr, .FlushW(IgnoreRequest), .WriteDataM(LSUWriteDataM), + .DTIMAdr, .FlushW(LSUFlushW), .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM)); end else assign DTIMReadDataWordM = '0; @@ -328,7 +328,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( - .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(IgnoreRequest), + .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW), .CacheRW(CacheRWM), .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), @@ -340,7 +340,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( - .HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), + .HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM), @@ -360,7 +360,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; - ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY), + ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); @@ -386,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, - .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, + .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .LSUFlushW, .IMAWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 1'b0; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index e48bf85dd..4e9003dc3 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -58,7 +58,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( output logic [1:0] LSUAtomicM, output logic [2:0] LSUFunct3M, output logic [6:0] LSUFunct7M, - output logic IgnoreRequestTLB, + output logic HPTWFlushW, output logic SelHPTW, output logic HPTWStall, input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, @@ -304,9 +304,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | - //((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. - (WalkerState != IDLE & HPTWFaultM); + assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); assign ResetPTE = reset | (NextWalkerState == IDLE); assign SelHPTW = WalkerState != IDLE; From 1ded4a972fc96efca6f8e12fc01ec1ca905a281e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 16:02:27 -0500 Subject: [PATCH 006/232] This is a better solution. It's closer to the original book HPTW FSM, but is slightly more complex in RTL. Instead it looks at ReadDataM for the PTE for PBMT faults. I was worried this would cause critical path issues but I think it is ok. ReadDataM is used only to created PBMT and this directly controlls the enable to a flop and the state inputs to the FSM. --- sim/questa/wave.do | 741 +++++++++++++++++++++++---------------------- src/mmu/hptw.sv | 13 +- 2 files changed, 378 insertions(+), 376 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index b00abf659..34079f049 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/InstrValidM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM -add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -72,122 +72,122 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} -add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} -add wave -noupdate -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory -add wave -noupdate -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr -add wave -noupdate -group ifu -group Bpred -divider {class check} -add wave -noupdate -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF -add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage -add wave -noupdate -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess -add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU -add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory -add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} +add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} +add wave -noupdate -expand -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory +add wave -noupdate -expand -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr +add wave -noupdate -expand -group ifu -group Bpred -divider {class check} +add wave -noupdate -expand -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -expand -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF +add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess +add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -210,219 +210,221 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask -add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel -add wave -noupdate -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask +add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel +add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushStage +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWRW +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -666,9 +668,10 @@ add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg +add wave -noupdate /testbench/dut/core/priv/priv/trap/CommittedF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {1197 ns} 0} {{Cursor 4} {223860 ns} 1} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 4} {3636 ns} 0} {{Cursor 4} {787447 ns} 1} {{Cursor 3} {710675 ns} 1} {{Cursor 4} {223860 ns} 1} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -683,4 +686,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1130 ns} {1230 ns} +WaveRestoreZoom {3524 ns} {3788 ns} diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 4e9003dc3..2e9829cb1 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -153,7 +153,9 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign ValidPTE = Valid & ~(Writable & ~Readable); assign ValidLeafPTE = ValidPTE & LeafPTE; assign ValidNonLeafPTE = Valid & ~LeafPTE; - if(P.XLEN == 64) assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); + // assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); // This is delayed one cycle so use ReadDataM instead + // It's ok for critical path because PBMTFaultM is only used to enable registers and as input to the FSM. + if(P.XLEN == 64) assign PBMTFaultM = ReadDataM[0] & ~(ReadDataM[3] | ReadDataM[2] | ReadDataM[1]) & (|ReadDataM[62:61]) & HPTWRW[1] & ~DCacheBusStallM; else assign PBMTFaultM = 1'b0; if(P.SVADU_SUPPORTED) begin : hptwwrites @@ -278,20 +280,17 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; - else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; - else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; - else if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L0_RD; From 5011084d4028df2e2df17916d370caeea4bf656c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 17:02:51 -0500 Subject: [PATCH 007/232] Revert "This is a better solution. It's closer to the original book HPTW FSM," This actually adds to the critical path and it's more complex than I feel comfortable. This reverts commit 1ded4a972fc96efca6f8e12fc01ec1ca905a281e. --- sim/questa/wave.do | 741 ++++++++++++++++++++++----------------------- src/mmu/hptw.sv | 13 +- 2 files changed, 376 insertions(+), 378 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index 34079f049..b00abf659 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM +add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -72,122 +72,122 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} -add wave -noupdate -expand -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} -add wave -noupdate -expand -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory -add wave -noupdate -expand -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr -add wave -noupdate -expand -group ifu -group Bpred -divider {class check} -add wave -noupdate -expand -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -expand -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage -add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess -add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -expand -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -expand -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -expand -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]} +add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]} +add wave -noupdate -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory +add wave -noupdate -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr +add wave -noupdate -group ifu -group Bpred -divider {class check} +add wave -noupdate -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/FlushStage +add wave -noupdate -group ifu -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheRW +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/Stall +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/CacheAccess +add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/FlushStage +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory[50]} +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU +add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory +add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits} +add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits} +add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay} +add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits} +add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout} +add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -group ifu -group itlb -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -group ifu -group itlb -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -210,221 +210,219 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask -add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel -add wave -noupdate -expand -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtE -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrExtM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushStage -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWRW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu -group stalls /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskExtendedM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask +add wave -noupdate -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/FetchBufferByteSel +add wave -noupdate -group lsu -group alignment {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/LineWriteData} +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache -expand -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay +add wave -noupdate -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/TagWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/TagWay} +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/TranslationVAdr +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBMissOrUpdateAF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW @@ -668,10 +666,9 @@ add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/Active add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitShiftReg -add wave -noupdate /testbench/dut/core/priv/priv/trap/CommittedF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {3636 ns} 0} {{Cursor 4} {787447 ns} 1} {{Cursor 3} {710675 ns} 1} {{Cursor 4} {223860 ns} 1} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {1197 ns} 0} {{Cursor 4} {223860 ns} 1} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -686,4 +683,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {3524 ns} {3788 ns} +WaveRestoreZoom {1130 ns} {1230 ns} diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 2e9829cb1..4e9003dc3 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -153,9 +153,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign ValidPTE = Valid & ~(Writable & ~Readable); assign ValidLeafPTE = ValidPTE & LeafPTE; assign ValidNonLeafPTE = Valid & ~LeafPTE; - // assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); // This is delayed one cycle so use ReadDataM instead - // It's ok for critical path because PBMTFaultM is only used to enable registers and as input to the FSM. - if(P.XLEN == 64) assign PBMTFaultM = ReadDataM[0] & ~(ReadDataM[3] | ReadDataM[2] | ReadDataM[1]) & (|ReadDataM[62:61]) & HPTWRW[1] & ~DCacheBusStallM; + if(P.XLEN == 64) assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]); else assign PBMTFaultM = 1'b0; if(P.SVADU_SUPPORTED) begin : hptwwrites @@ -280,17 +278,20 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L3_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; - L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 + L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39 else NextWalkerState = LEAF; L2_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 + L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32 else NextWalkerState = LEAF; L1_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; - L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; + L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT; + else if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; L0_RD: if (HPTWFaultM) NextWalkerState = FAULT; else if (DCacheBusStallM) NextWalkerState = L0_RD; From 21e6ccd8ddf073e0d5a4e39c90211ea7ae66a67b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 12 Oct 2024 16:39:17 -0700 Subject: [PATCH 008/232] Waived tlbMisaligned lockstep sim due to Issue 976 and improved timeout warning message --- bin/regression-wally | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 16286c60b..67cd4815b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -233,6 +233,7 @@ bpredtests = [ # list of tests not supported by ImperasDV yet that should be waived during lockstep testing lockstepwaivers = [ "WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV + "coverage_tlbMisaligned.elf", # Issue 976: ImperasDV bug disagrees with Wally related to misaligned pages when PBMT makes page uncachable "WALLY-cbom-01.S_ref.elf" #, # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV ] @@ -542,7 +543,7 @@ def main(): num_fail+=result.get(timeout=TIMEOUT_DUR) except TimeoutError: num_fail+=1 - print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR)) + print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR)) # Coverage report if args.ccov: From 2ef7005ea63af45d54c4016a80c6db4f3ee8dbed Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 13 Oct 2024 15:29:27 -0500 Subject: [PATCH 009/232] Fixed name of test and added to tests.vh --- testbench/tests.vh | 1 + tests/coverage/{nonleafpmbtfault.S => nonleafpbmtfault.S} | 0 2 files changed, 1 insertion(+) rename tests/coverage/{nonleafpmbtfault.S => nonleafpbmtfault.S} (100%) diff --git a/testbench/tests.vh b/testbench/tests.vh index a91aeda15..bef41ef22 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -60,6 +60,7 @@ string coverage64gc[] = '{ "tlbTP", "tlbMisaligned", "hptwAccessFault", + "nonleafpbmtfault", "amoAccessFault", "floatmisc", "ifuCamlineWrite", diff --git a/tests/coverage/nonleafpmbtfault.S b/tests/coverage/nonleafpbmtfault.S similarity index 100% rename from tests/coverage/nonleafpmbtfault.S rename to tests/coverage/nonleafpbmtfault.S From d5649f6f1d650c90824c5039172f1127ce1c3904 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 17:32:38 -0700 Subject: [PATCH 010/232] Limit number of threads if 8 GB of memory --- bin/wally-tool-chain-install.sh | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 53bc01c8b..7d4dd206d 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -112,11 +112,27 @@ if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then exit 1 fi -# Create installation directory -mkdir -p "$RISCV"/logs +# Check available memory +total_mem=$(grep MemTotal < /proc/meminfo | awk '{print $2}') +total_mem_gb=$((total_mem / 1024 / 1024)) + +# Print system information echo "Running as root: $ROOT" echo "Installation path: $RISCV" +echo "Number of cores: $(nproc)" +echo "Total memory: $total_mem_gb GB" +# Reduce number of threads for systems with less than 8 GB of memory +if ((total_mem < 8400000 )) ; then + NUM_THREADS=1 + echo -e "${WARNING_COLOR}Detected less than or equal to 8 GB of memory. Using a single thread for compiling tools. This may take a while.${ENDC}" +fi + +# Print number of threads +echo "Using $NUM_THREADS thread(s) for compilation" + +# Create installation directory +mkdir -p "$RISCV"/logs # Install/update system packages if root. Otherwise, check that packages are already installed. STATUS="system packages" From da35944dceb6d946e63aace798a8da31117fd722 Mon Sep 17 00:00:00 2001 From: Mysterio-Abdullah Date: Sun, 13 Oct 2024 17:41:59 -0700 Subject: [PATCH 011/232] Configuring Zcb --- addins/cvw-arch-verif | 2 +- config/rv32gc/coverage.svh | 3 +++ config/rv64gc/coverage.svh | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 80cdee231..bbcba7864 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 80cdee231f924b3045054594d4a7769e6eddcdcc +Subproject commit bbcba78647080dee82e96bc1b8ff9cd9a3cf7fa1 diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 8fe5d6622..3a04643ad 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -11,3 +11,6 @@ `include "RV32Zfh_coverage.svh" `include "RV32Zicond_coverage.svh" `include "RV32Zca_coverage.svh" +`include "RV32Zcb_coverage.svh" +`include "RV32ZcbM_coverage.svh" +`include "RV32ZcbZbb_coverage.svh" \ No newline at end of file diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index f21eb2b1a..d1bbaedbb 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -16,3 +16,6 @@ // `include "RV64Zicbom_coverage.svh" `include "RV64Zicond_coverage.svh" `include "RV64Zca_coverage.svh" +`include "RV64Zcb_coverage.svh" +`include "RV64ZcbM_coverage.svh" +`include "RV64ZcbZbb_coverage.svh" \ No newline at end of file From 1e34a970684fbbd6743d85fa57f89bb4f8d087fa Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:04:26 -0700 Subject: [PATCH 012/232] Temporarily remove matplotlib --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 462898a60..5445ac69f 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -1,7 +1,7 @@ adjustText>=1.2 lief>=0.14.1 Markdown>=3.6 -matplotlib>=3.9.0 +#matplotlib>=3.9.0 PyYAML>=5.2 riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git From 3084fa9c371c13eb88b4b0280594d950585322a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:13:42 -0700 Subject: [PATCH 013/232] Temporarily remove PyYAML from requirements.txt --- bin/requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 5445ac69f..a983b8ca4 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -1,8 +1,8 @@ adjustText>=1.2 lief>=0.14.1 Markdown>=3.6 -#matplotlib>=3.9.0 -PyYAML>=5.2 +# matplotlib>=3.9.0 +# PyYAML>=5.2 riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 From 0f2dae0da11adb456f42367ef52d18ae540a85a7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:19:21 -0700 Subject: [PATCH 014/232] Temporarily remove sphinx from requirements.txt --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index a983b8ca4..b4280bacc 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 -Sphinx>=7.3.7 +# Sphinx>=7.3.7 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 3c88bb9771666f48709951005ad7f7e4c091ebea Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 15:23:22 -0700 Subject: [PATCH 015/232] Temporarily remove sphinx-rtd-theme from requirements.txt --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index b4280bacc..d1a102d3a 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -10,5 +10,5 @@ riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 # Sphinx>=7.3.7 -sphinx-rtd-theme>=2.0.0 +# sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 8f3d888da5258ab2a2e19838b2315124f5fb8d11 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 16:04:32 -0700 Subject: [PATCH 016/232] Attempt to install riscof only --- bin/requirements.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index d1a102d3a..8cfad9c70 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -3,9 +3,9 @@ lief>=0.14.1 Markdown>=3.6 # matplotlib>=3.9.0 # PyYAML>=5.2 -riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac +# riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac riscof @ git+https://github.com/riscv/riscof.git -riscv-config>=3.18.3 +# riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 From 5580bf2fb0914dd1537c0314453920594a0cdd57 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 16:06:58 -0700 Subject: [PATCH 017/232] Attempt clone and install riscv-isac --- bin/wally-tool-chain-install.sh | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7d4dd206d..3cc774af3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -176,6 +176,12 @@ pip install --upgrade pip && pip install -r "$dir"/requirements.txt source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" +# Install riscv-isac +cd $RISCV +STATUS="riscv-isac" +git clone https://github.com/riscv-non-isa/riscv-arch-test +cd riscv-arch-test/riscv-isac +pip install . # Extra dependecies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then From 826b3775b61db0338094a637333b3c70d10497eb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 21:52:44 -0700 Subject: [PATCH 018/232] Add setuptools to pip --- bin/requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/requirements.txt b/bin/requirements.txt index 8cfad9c70..22afbb775 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -4,6 +4,7 @@ Markdown>=3.6 # matplotlib>=3.9.0 # PyYAML>=5.2 # riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac +setuptools riscof @ git+https://github.com/riscv/riscof.git # riscv-config>=3.18.3 riscv-isac>=0.18.0 From 5f28ee5959239829e3f9309d7e44c488b14a0ecf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:22:20 -0700 Subject: [PATCH 019/232] Test forked riscv-arch-test --- bin/requirements.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 22afbb775..f50d507cb 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -1,15 +1,15 @@ adjustText>=1.2 lief>=0.14.1 Markdown>=3.6 -# matplotlib>=3.9.0 -# PyYAML>=5.2 -# riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac +matplotlib>=3.9.0 +PyYAML>=5.2 +riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac setuptools riscof @ git+https://github.com/riscv/riscof.git -# riscv-config>=3.18.3 +riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 scipy>=1.13.0 -# Sphinx>=7.3.7 -# sphinx-rtd-theme>=2.0.0 +Sphinx>=7.3.7 +sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 20b157de628597bc141987bc5292e51e92a83e56 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:39:49 -0700 Subject: [PATCH 020/232] Remove manual riscv-isac installation --- bin/wally-tool-chain-install.sh | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3cc774af3..437023fb8 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -171,18 +171,11 @@ source "$RISCV"/riscv-python/bin/activate # activate python virtual environment # Install python packages, including RISCOF (https://github.com/riscv-software-src/riscof.git) # RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. STATUS="python packages" -pip install --upgrade pip && pip install -r "$dir"/requirements.txt +pip install --upgrade pip && pip install --upgrade -r "$dir"/requirements.txt source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" -# Install riscv-isac -cd $RISCV -STATUS="riscv-isac" -git clone https://github.com/riscv-non-isa/riscv-arch-test -cd riscv-arch-test/riscv-isac -pip install . - # Extra dependecies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then # Newer versin of glib required for QEMU. From 1076b9c179d709ff8b904afdf50c0fc5405233ff Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:44:16 -0700 Subject: [PATCH 021/232] Use python 3.11 for rhel 8 --- bin/wally-package-install.sh | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 725d3b201..94631ad6a 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -46,7 +46,12 @@ fi # Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" == rhel ]; then - PYTHON_VERSION=python3.12 + if (( RHEL_VERSION == 8 )); then + PYTHON_VERSION=python3.11 + elif (( RHEL_VERSION >= 9 )); then + PYTHON_VERSION=python3.12 + VERILATOR_PACKAGES+=(perl-doc) # Not availale in rhel8, nice for Verilator + fi PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp) @@ -55,10 +60,6 @@ if [ "$FAMILY" == rhel ]; then SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux - # Extra packages not availale in rhel8, nice for Verilator - if (( RHEL_VERSION >= 9 )); then - VERILATOR_PACKAGES+=(perl-doc) - fi # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then From ab1797753bbe6778bac35f0cdd9bc5fe86f80cf4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 19:49:30 -0700 Subject: [PATCH 022/232] Revert "Use python 3.11 for rhel 8" This reverts commit d76cda4dd7613583d41a4bc4624a1915f490a583. --- bin/wally-package-install.sh | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 94631ad6a..725d3b201 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -46,12 +46,7 @@ fi # Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" == rhel ]; then - if (( RHEL_VERSION == 8 )); then - PYTHON_VERSION=python3.11 - elif (( RHEL_VERSION >= 9 )); then - PYTHON_VERSION=python3.12 - VERILATOR_PACKAGES+=(perl-doc) # Not availale in rhel8, nice for Verilator - fi + PYTHON_VERSION=python3.12 PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp) @@ -60,6 +55,10 @@ if [ "$FAMILY" == rhel ]; then SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux + # Extra packages not availale in rhel8, nice for Verilator + if (( RHEL_VERSION >= 9 )); then + VERILATOR_PACKAGES+=(perl-doc) + fi # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then From 1cb22fbe8a17be39dc30aeba8595bac4c2555c46 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 20:35:36 -0700 Subject: [PATCH 023/232] Fix duplicate riscv-isac --- bin/requirements.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index f50d507cb..69c22216e 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -3,13 +3,12 @@ lief>=0.14.1 Markdown>=3.6 matplotlib>=3.9.0 PyYAML>=5.2 -riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac -setuptools riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 -riscv-isac>=0.18.0 +riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac scikit-learn>=1.5.0 scipy>=1.13.0 +setuptools Sphinx>=7.3.7 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 9ef211b40d6807aabc7cf3c065f617f21d7aad8b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Oct 2024 20:59:01 -0700 Subject: [PATCH 024/232] mcountinhibit bit 1 should be hardwired to 0. Discovered during functional coverage testing --- src/privileged/csrm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 24132ab93..2a4a6d668 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -171,7 +171,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); flopenr #(P.XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW); flopenr #(P.XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); - flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); + flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, {CSRWriteValM[31:2], 1'b0, CSRWriteValM[0]}, MCOUNTINHIBIT_REGW); if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); end else assign MCOUNTEREN_REGW = '0; From 669ee6ca121ef9fc5ab4892a63c5dad254a92c8e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Oct 2024 20:59:41 -0700 Subject: [PATCH 025/232] WALLY-init-lib improvements to support functional coverage --- tests/coverage/WALLY-init-lib.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index edf867240..b6b4f56b1 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -127,6 +127,17 @@ write_tohost: self_loop: j self_loop # wait + +// utility routines + +# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 +setmsb: + li a0, 0x80000000 # 1 in bit 31 + slli a1, a0, 1 # check if register is wider than 31 bits + beqz a1, 1f # yes, a0 has 1 in bit 31 + slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63 + slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 + ret # return to calller .section .tohost tohost: # write to HTIF @@ -139,6 +150,9 @@ begin_signature: .fill 6*(XLEN/32),4,0xdeadbeef # end_signature: +scratch: + .fill 4,4,0x0 + # Initialize stack with room for 512 bytes .bss .space 512 From 5f5dac2bda2e1aa0b511a76badc3ab1bd53a9819 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Oct 2024 21:42:16 -0700 Subject: [PATCH 026/232] Some Imperas configuration changes to match unimplemented Wally registers --- config/rv64gc/imperas.ic | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 2ee487094..1b038c920 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -57,6 +57,17 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T +--override cpu/scontext_undefined=T +--override cpu/mcontext_undefined=T +--override cpu/mnoise_undefined=T +# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers +#--override cpu/seed_undefined=T +#--override mhpmevent3_undefined=T +#--override cpu/mseccfg_undefined=T +#--override cpu/tselect_undefined=T +#--override cpu/tdata1_undefined=T + + --override cpu/reset_address=0x80000000 --override cpu/unaligned=T # Zicclsm (should be true) From 0cb1ac70f64a0f68c8944ccafd318336d7c8ceee Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:01:15 -0700 Subject: [PATCH 027/232] Limit Sphinx version --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 69c22216e..b29b34507 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=r scikit-learn>=1.5.0 scipy>=1.13.0 setuptools -Sphinx>=7.3.7 +Sphinx>=7.3.7, ~=7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 48ee8b0a184613fd330740e30e1721ecae2ce2c2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:07:06 -0700 Subject: [PATCH 028/232] Fix sphinx version format --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index b29b34507..10466f601 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=r scikit-learn>=1.5.0 scipy>=1.13.0 setuptools -Sphinx>=7.3.7, ~=7 # QEMU fails to build with Sphinx 8 +Sphinx>=7.3.7; ~=7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From 77eb250ef66effffc81b3016af342b9efd495d76 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:14:12 -0700 Subject: [PATCH 029/232] Fix sphinx version format --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 10466f601..e5701f08e 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -9,6 +9,6 @@ riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=r scikit-learn>=1.5.0 scipy>=1.13.0 setuptools -Sphinx>=7.3.7; ~=7 # QEMU fails to build with Sphinx 8 +Sphinx~=7.3.7 # QEMU fails to build with Sphinx 8 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From dc98f29ffaa90842a5495d563e53101a5e0329dd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 23:26:51 -0700 Subject: [PATCH 030/232] Add --no-buildroot option to installation script --- bin/wally-tool-chain-install.sh | 44 ++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 437023fb8..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -77,11 +77,17 @@ trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages # Check for clean flag -if [ "$1" == "--clean" ]; then +if [ "$1" == "--clean" ] || [ "$2" == "--clean" ]; then clean=true shift fi +# Check for clean flag +if [ "$1" == "--no-buildroot" ] || [ "$2" == "--no-buildroot" ]; then + no_buidroot=true + shift +fi + # Determine script directory to locate related scripts dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" @@ -391,23 +397,27 @@ fi # Buildroot and Linux testvectors # Buildroot is used to boot a minimal versio of Linux on Wally. # Testvectors are generated using QEMU. -section_header "Installing Buildroot and Creating Linux testvectors" -STATUS="buildroot" -if [ -z "$LD_LIBRARY_PATH" ]; then - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ +if [ ! "$no_buidroot" ]; then + section_header "Installing Buildroot and Creating Linux testvectors" + STATUS="buildroot" + if [ -z "$LD_LIBRARY_PATH" ]; then + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ + else + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ + fi + cd "$dir"/../linux + if [ ! -e "$RISCV"/buildroot ]; then + make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" + elif [ ! -e "$RISCV"/linux-testvectors ]; then + echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" + make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" + else + echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" + fi else - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ -fi -cd "$dir"/../linux -if [ ! -e "$RISCV"/buildroot ]; then - make 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" -elif [ ! -e "$RISCV"/linux-testvectors ]; then - echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" - make dumptvs 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" -else - echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" + echo -e "${OK_COLOR}Skipping Buildroot and Linux testvectors.${ENDC}" fi From b8d50fd6217ea513ceae970408bb9a390ad18fa3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 00:42:47 -0700 Subject: [PATCH 031/232] Switch back to standard riscv-arch-test repo --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index e5701f08e..d55bf7eda 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -5,7 +5,7 @@ matplotlib>=3.9.0 PyYAML>=5.2 riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 -riscv-isac @ git+https://github.com/jordancarlin/riscv-arch-test/#subdirectory=riscv-isac +riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac scikit-learn>=1.5.0 scipy>=1.13.0 setuptools From 64069319589e187c83622b5e815b5fe7deb02cf7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 23:52:52 -0400 Subject: [PATCH 032/232] Test installation regression GitHub action --- .github/workflows/install.yml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 .github/workflows/install.yml diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml new file mode 100644 index 000000000..bb77a0c62 --- /dev/null +++ b/.github/workflows/install.yml @@ -0,0 +1,14 @@ +name: Installation test + +on: [workflow_dispatch] + +jobs: + install: + name: Test installation on Ubuntu 22.04LTS + runs-on: ubuntu-22.04 + + steps: + - uses: actions/checkout@v4 + - name: install + run: sudo ./bin/wally-tool-chain-install + From 780147dfd6a072da358c319ef01e9418d47e5bb3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 23:55:13 -0400 Subject: [PATCH 033/232] Update install.yml --- .github/workflows/install.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index bb77a0c62..eb8255234 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -10,5 +10,8 @@ jobs: steps: - uses: actions/checkout@v4 - name: install - run: sudo ./bin/wally-tool-chain-install + run: | + pwd + cd cvw + sudo ./bin/wally-tool-chain-install From 9f38600caceb4f22ff29c227e8534907ca52db95 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 23:56:24 -0400 Subject: [PATCH 034/232] Update install.yml --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index eb8255234..8a48f690a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -12,6 +12,6 @@ jobs: - name: install run: | pwd - cd cvw - sudo ./bin/wally-tool-chain-install + ls + sudo ./bin/wally-tool-chain-install.sh From ac5a469034ac30332f77581f2d91e007ea79e1cd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 5 Jul 2024 00:11:11 -0400 Subject: [PATCH 035/232] Update install.yml --- .github/workflows/install.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 8a48f690a..ca517a7b0 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,6 +9,9 @@ jobs: steps: - uses: actions/checkout@v4 + - run: sudo apt update + - run: sudo apt upgrade -y + - run: sudo apt install -y libunwind-dev - name: install run: | pwd From 9a399e7ef0e25c789449b409999114f3826f2488 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 5 Jul 2024 10:03:15 -0400 Subject: [PATCH 036/232] Update install.yml --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ca517a7b0..e9ecdd0e5 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -12,6 +12,7 @@ jobs: - run: sudo apt update - run: sudo apt upgrade -y - run: sudo apt install -y libunwind-dev + - run: git clone --recurse-submodules -j 4 https://github.com/qemu/qemu - name: install run: | pwd From 8dcdd71830662e703287e01adb86860fda780207 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 5 Jul 2024 10:08:11 -0400 Subject: [PATCH 037/232] Update install.yml --- .github/workflows/install.yml | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e9ecdd0e5..16da4248e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,13 +9,6 @@ jobs: steps: - uses: actions/checkout@v4 - - run: sudo apt update - - run: sudo apt upgrade -y - - run: sudo apt install -y libunwind-dev - - run: git clone --recurse-submodules -j 4 https://github.com/qemu/qemu - name: install - run: | - pwd - ls - sudo ./bin/wally-tool-chain-install.sh + run: sudo ./bin/wally-tool-chain-install.sh From 9fe94b86d2b1ae8a2a1ab93ceec1b3c3356500a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 09:12:05 -0400 Subject: [PATCH 038/232] Update install.yml --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 16da4248e..d07636bfa 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,6 +8,7 @@ jobs: runs-on: ubuntu-22.04 steps: + - run: df -h - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh From 0029483139d0da88640493fb103d18827729ac23 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 09:45:34 -0400 Subject: [PATCH 039/232] Update install.yml --- .github/workflows/install.yml | 37 ++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index d07636bfa..b8a29a9b4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,7 +9,38 @@ jobs: steps: - run: df -h - - uses: actions/checkout@v4 - - name: install - run: sudo ./bin/wally-tool-chain-install.sh + - run: | + sudo rm -rf /usr/local/lib/android + df -h + - run: | + sudo rm -rf /usr/share/dotnet + df -h + - run: | + sudo rm -rf /opt/ghc + df -h + - run: | + sudo rm -rf /opt/hostedtoolcache/CodeQL + df -h + - run: | + sudo docker image prune --all --force + df -h + - run: | + sudo apt-get purge -y \ + '^llvm-.*' \ + 'php.*' \ + '^mongodb-.*' \ + '^mysql-.*' \ + azure-cli \ + google-cloud-cli \ + google-chrome-stable \ + firefox \ + powershell \ + microsoft-edge-stable \ + mono-devel + sudo apt-get autoremove -y + sudo apt-get clean + df -h + #- uses: actions/checkout@v4 + #- name: install + # run: sudo ./bin/wally-tool-chain-install.sh From 319982a65c10ae222a535a5dc87f7df40b227c86 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 09:52:43 -0400 Subject: [PATCH 040/232] Update install.yml --- .github/workflows/install.yml | 37 +++++++++++++---------------------- 1 file changed, 14 insertions(+), 23 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b8a29a9b4..b3cc2b6f4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,23 +8,13 @@ jobs: runs-on: ubuntu-22.04 steps: - - run: df -h - - run: | - sudo rm -rf /usr/local/lib/android - df -h - - run: | - sudo rm -rf /usr/share/dotnet - df -h - - run: | - sudo rm -rf /opt/ghc - df -h - - run: | - sudo rm -rf /opt/hostedtoolcache/CodeQL - df -h - - run: | - sudo docker image prune --all --force - df -h - - run: | + - name: Free up storage + run: | + sudo rm -rf /usr/local/lib/android &> /dev/null + sudo rm -rf /usr/share/dotnet &> /dev/null + sudo rm -rf /opt/ghc &> /dev/null + sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null + sudo docker image prune --all --force &> /dev/null sudo apt-get purge -y \ '^llvm-.*' \ 'php.*' \ @@ -36,11 +26,12 @@ jobs: firefox \ powershell \ microsoft-edge-stable \ - mono-devel - sudo apt-get autoremove -y - sudo apt-get clean + mono-devel \ + &> /dev/null + sudo apt-get autoremove -y &> /dev/null + sudo apt-get clean &> /dev/null df -h - #- uses: actions/checkout@v4 - #- name: install - # run: sudo ./bin/wally-tool-chain-install.sh + - uses: actions/checkout@v4 + - name: install + run: sudo ./bin/wally-tool-chain-install.sh From 5717089c0219a1eaae6c94c6fa7faf805bbbf96c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 10:00:28 -0400 Subject: [PATCH 041/232] Create rocky.yml --- .github/workflows/rocky.yml | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .github/workflows/rocky.yml diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml new file mode 100644 index 000000000..85ab33eff --- /dev/null +++ b/.github/workflows/rocky.yml @@ -0,0 +1,38 @@ +name: Installation test + +on: [workflow_dispatch] + +jobs: + install: + name: Test installation on Rocky 9 + runs-on: ubuntu-latest + container: rockylinux:8 + + steps: + - name: Free up storage + run: | + sudo rm -rf /usr/local/lib/android &> /dev/null + sudo rm -rf /usr/share/dotnet &> /dev/null + sudo rm -rf /opt/ghc &> /dev/null + sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null + sudo docker image prune --all --force &> /dev/null + sudo apt-get purge -y \ + '^llvm-.*' \ + 'php.*' \ + '^mongodb-.*' \ + '^mysql-.*' \ + azure-cli \ + google-cloud-cli \ + google-chrome-stable \ + firefox \ + powershell \ + microsoft-edge-stable \ + mono-devel \ + &> /dev/null + sudo apt-get autoremove -y &> /dev/null + sudo apt-get clean &> /dev/null + df -h + - uses: actions/checkout@v4 + - name: install + run: sudo ./bin/wally-tool-chain-install.sh + From a111541da596457723096111da54b6e5309b52bc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 10:37:41 -0400 Subject: [PATCH 042/232] Update rocky.yml --- .github/workflows/rocky.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 85ab33eff..9c4097aae 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -7,6 +7,9 @@ jobs: name: Test installation on Rocky 9 runs-on: ubuntu-latest container: rockylinux:8 + defaults: + run: + shell: bash steps: - name: Free up storage From 81e3b5024211cb025782bfa63c38c720cb93a3c2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 20:27:22 -0400 Subject: [PATCH 043/232] Update rocky.yml --- .github/workflows/rocky.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 9c4097aae..2a828667b 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -12,6 +12,9 @@ jobs: shell: bash steps: + - run: pwd + - run: ls + - run: df -h - name: Free up storage run: | sudo rm -rf /usr/local/lib/android &> /dev/null From e9d1c501eba24899bb3dee738caa9a76319c1372 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 20:30:23 -0400 Subject: [PATCH 044/232] Update rocky.yml --- .github/workflows/rocky.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 2a828667b..72772f357 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -17,11 +17,11 @@ jobs: - run: df -h - name: Free up storage run: | - sudo rm -rf /usr/local/lib/android &> /dev/null - sudo rm -rf /usr/share/dotnet &> /dev/null - sudo rm -rf /opt/ghc &> /dev/null - sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null - sudo docker image prune --all --force &> /dev/null + sudo rm -rf /usr/local/lib/android + sudo rm -rf /usr/share/dotnet + sudo rm -rf /opt/ghc + sudo rm -rf /opt/hostedtoolcache/CodeQL + sudo docker image prune --all --force sudo apt-get purge -y \ '^llvm-.*' \ 'php.*' \ @@ -35,7 +35,7 @@ jobs: microsoft-edge-stable \ mono-devel \ &> /dev/null - sudo apt-get autoremove -y &> /dev/null + sudo apt-get autoremove -y sudo apt-get clean &> /dev/null df -h - uses: actions/checkout@v4 From 9e9e30112752fdbbc61f5a88484e9ace1139785e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:42:24 -0400 Subject: [PATCH 045/232] Update rocky.yml --- .github/workflows/rocky.yml | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 72772f357..7a4bca157 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -12,32 +12,15 @@ jobs: shell: bash steps: - - run: pwd - - run: ls - run: df -h - name: Free up storage run: | - sudo rm -rf /usr/local/lib/android - sudo rm -rf /usr/share/dotnet - sudo rm -rf /opt/ghc - sudo rm -rf /opt/hostedtoolcache/CodeQL - sudo docker image prune --all --force - sudo apt-get purge -y \ - '^llvm-.*' \ - 'php.*' \ - '^mongodb-.*' \ - '^mysql-.*' \ - azure-cli \ - google-cloud-cli \ - google-chrome-stable \ - firefox \ - powershell \ - microsoft-edge-stable \ - mono-devel \ - &> /dev/null - sudo apt-get autoremove -y - sudo apt-get clean &> /dev/null - df -h + rm -rf /usr/local/lib/android + rm -rf /usr/share/dotnet + rm -rf /opt/ghc + rm -rf /opt/hostedtoolcache/CodeQL + docker image prune --all --&> /dev/null + - run: df -h - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh From fb40f0477223d0320c9bb16391ece97b57b57b83 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:50:46 -0400 Subject: [PATCH 046/232] Update rocky.yml --- .github/workflows/rocky.yml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 7a4bca157..f9a5450e9 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -13,14 +13,6 @@ jobs: steps: - run: df -h - - name: Free up storage - run: | - rm -rf /usr/local/lib/android - rm -rf /usr/share/dotnet - rm -rf /opt/ghc - rm -rf /opt/hostedtoolcache/CodeQL - docker image prune --all --&> /dev/null - - run: df -h - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh From 2e31836e69495f03bc590d94b15882a9b131c344 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:53:05 -0400 Subject: [PATCH 047/232] Update rocky.yml --- .github/workflows/rocky.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index f9a5450e9..a99c13521 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -15,5 +15,5 @@ jobs: - run: df -h - uses: actions/checkout@v4 - name: install - run: sudo ./bin/wally-tool-chain-install.sh + run: ./bin/wally-tool-chain-install.sh From e01c70a9d4a7ab3f5e50a5ffca9e39d45eb8a1e7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 6 Jul 2024 21:54:55 -0400 Subject: [PATCH 048/232] Update rocky.yml --- .github/workflows/rocky.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index a99c13521..b405864d9 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -13,6 +13,7 @@ jobs: steps: - run: df -h + - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh From 19244c9bd708f89351dabf31445a72877f9b4e54 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 7 Jul 2024 08:52:54 -0400 Subject: [PATCH 049/232] Update rocky.yml --- .github/workflows/rocky.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index b405864d9..32f02f000 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -6,13 +6,15 @@ jobs: install: name: Test installation on Rocky 9 runs-on: ubuntu-latest - container: rockylinux:8 defaults: run: shell: bash steps: - run: df -h + - name: free up storage + run: sudo rm -rf /usr/local/lib/android + - run: docker run rockylinux:8 - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install From 653aaa80f4ca823768cef8d5457337ad31d4d915 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 7 Jul 2024 08:59:34 -0400 Subject: [PATCH 050/232] Update rocky.yml --- .github/workflows/rocky.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index 32f02f000..ba33a14e3 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -14,7 +14,7 @@ jobs: - run: df -h - name: free up storage run: sudo rm -rf /usr/local/lib/android - - run: docker run rockylinux:8 + - run: docker start -ia rockylinux:8 - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install From b9ff0c18b0136b43624bab1df5374c161f1be0b6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 7 Jul 2024 09:36:44 -0400 Subject: [PATCH 051/232] Update rocky.yml --- .github/workflows/rocky.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/rocky.yml b/.github/workflows/rocky.yml index ba33a14e3..be64697c0 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rocky.yml @@ -14,7 +14,7 @@ jobs: - run: df -h - name: free up storage run: sudo rm -rf /usr/local/lib/android - - run: docker start -ia rockylinux:8 + - run: docker run -ia rockylinux:8 - run: dnf install -y sudo - uses: actions/checkout@v4 - name: install From 5ef5633a62fca387775c64a9d9a3ff5e38cb9ef4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 05:31:59 -0700 Subject: [PATCH 052/232] Adjusted menvcfg.CBIE reserved 10 behavior to match ImperasDV; spec is ambiguous (riscv-isa-manual Issue #1682 --- src/privileged/csrm.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 2a4a6d668..fd82106c1 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -180,7 +180,9 @@ module csrm import cvw::*; #(parameter cvw_t P) ( if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control logic WriteMENVCFGM; logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; + logic [1:0] LegalizedCBIE; assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG); + assign LegalizedCBIE = MENVCFG_PreWriteValM[5:4] == 2'b10 ? MENVCFG_REGW[5:4] : MENVCFG_PreWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value // MENVCFG is always 64 bits even for RV32 assign MENVCFG_WriteValM = { MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED, @@ -188,7 +190,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MENVCFG_PreWriteValM[61] & P.SVADU_SUPPORTED, 53'b0, MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED, - MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, + MENVCFG_PreWriteValM[6] & P.ZICBOM_SUPPORTED, + LegalizedCBIE & {2{P.ZICBOM_SUPPORTED}}, 3'b0, MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED }; From 43162aa088be9cb0440dd86c2059620e0149415d Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 08:42:52 -0700 Subject: [PATCH 053/232] Fixed handling writing reserved 10 value to mstatus.mpp --- src/privileged/csrsr.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index d0a7b00c6..9989bceed 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -106,7 +106,8 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( always_comb if (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE; else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE; - else STATUS_MPP_NEXT = P.M_MODE; + else if (CSRWriteValM[12:11] == 2'b10) STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10 + else STATUS_MPP_NEXT = P.M_MODE; /////////////////////////////////////////// // Endianness logic Privileged Spec 3.1.6.4 From 5e550554b5d15cfb5d242c91aa4746b539323294 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 08:58:37 -0700 Subject: [PATCH 054/232] Fixed bug in WALLY-init-lib label for RV32 --- tests/coverage/WALLY-init-lib.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index b6b4f56b1..7e2aee771 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -134,9 +134,10 @@ self_loop: setmsb: li a0, 0x80000000 # 1 in bit 31 slli a1, a0, 1 # check if register is wider than 31 bits - beqz a1, 1f # yes, a0 has 1 in bit 31 + beqz a1, setmsbdone # yes, a0 has 1 in bit 31 slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63 slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 +setmsbdone: ret # return to calller .section .tohost From f208b11b51600551e82fb73a19dbc077f4d6789a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 16:51:46 -0500 Subject: [PATCH 055/232] Update hptwAccessFault to generate additional hptw access faults during ifu fetches. --- tests/coverage/hptwAccessFault.S | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index 7c1bc3be1..e1a2ea49c 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -48,7 +48,32 @@ main: lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault add t0, t0, t2 - sw t1, 0(t0) + sw t1, 0(t0) + + j jumppoint + +jumppoint: +.align 6 # aligns to cache line size + sw t1, 0(t0) + sw t1, 4(t0) + sw t1, 8(t0) + sw t1, 12(t0) + sw t1, 16(t0) + sw t1, 20(t0) + sw t1, 24(t0) + sw t1, 28(t0) + sw t1, 32(t0) + sw t1, 36(t0) + sw t1, 40(t0) + sw t1, 44(t0) + sw t1, 48(t0) + sw t1, 52(t0) # this one causes a concurrent I$ miss with HPTW access exception (store access exception) + sw t1, 56(t0) + lw t3, 0(t0) + lw t3, 4(t0) + lw t3, 8(t0) + lw t3, 12(t0) + lw t3, 16(t0) fence.I From 9a76af809aa1732552e6c289b0ede261d7c9256c Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 15:28:28 -0700 Subject: [PATCH 056/232] Documented ecall services in WALLY-init-lib --- tests/coverage/WALLY-init-lib.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 7e2aee771..3a40d8351 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -28,6 +28,12 @@ // The PMP tests are sensitive to the exact addresses in this code, so unfortunately // modifying anything breaks those tests. +// Provides simple firmware services through ecall. Place argument in a0 and issue ecall: +// 0: change to user mode +// 1: change to supervisor mode +// 3: change to machine mode +// 4: terminate program + .section .text.init .global rvtest_entry_point From de8a707361c1049c38b7f8c6461b4d483b92bda9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 15:28:56 -0700 Subject: [PATCH 057/232] Updated WARL field in senvcfg.CBIE to match ImperasDV --- src/privileged/csrs.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 4797f800b..a2a21c2ee 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -128,13 +128,16 @@ module csrs import cvw::*; #(parameter cvw_t P) ( else assign STimerInt = 1'b0; + logic [1:0] LegalizedCBIE; + assign LegalizedCBIE = CSRWriteValM[5:4] == 2'b10 ? SENVCFG_REGW[5:4] : CSRWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value assign SENVCFG_WriteValM = { {(P.XLEN-8){1'b0}}, CSRWriteValM[7] & P.ZICBOZ_SUPPORTED, - CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, + CSRWriteValM[6] & P.ZICBOM_SUPPORTED, + LegalizedCBIE & {2{P.ZICBOM_SUPPORTED}}, 3'b0, CSRWriteValM[0] & P.VIRTMEM_SUPPORTED - }; + }; flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW); From 816e54f4510cd5256970dd0e310dda2692e55f72 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 21:29:02 -0500 Subject: [PATCH 058/232] Revert "Revmoed file from fpga zbbl which should not have been added." This reverts commit d6944cdaa46aeacfa095a2da1926d0974efb369e. --- fpga/zsbl/bios.S | 102 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 fpga/zsbl/bios.S diff --git a/fpga/zsbl/bios.S b/fpga/zsbl/bios.S new file mode 100644 index 000000000..a7283b38d --- /dev/null +++ b/fpga/zsbl/bios.S @@ -0,0 +1,102 @@ +#include "system.h" + +PERIOD = (SYSTEMCLOCK / 2) + +.section .init +.global _start +.type _start, @function + + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, (EXT_MEM_END - 8) + + li a0, 0x00000000 + li a1, EXT_MEM_BASE + #li a2, 128*1024*1024/512 # copy 128MB + li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra) + #li a2, 800 # copy 400KB + jal ra, copyFlash + + fence.i + # now toggle led so we know the copy completed. + + # write to gpio + li t2, 0xFF + la t3, 0x1006000C + li t4, 5 + +loop: + + # delay + li t0, PERIOD/2 +delay1: + addi t0, t0, -1 + bge t0, x0, delay1 + sw t2, 0x0(t3) + + li t0, PERIOD/2 +delay2: + addi t0, t0, -1 + bge t0, x0, delay2 + sw x0, 0x0(t3) + + addi t4, t4, -1 + bgt t4, x0, loop + + + # now that the card is copied and the led toggled we + # jump to the copied contents of the sd card. + +jumpToLinux: + csrrs a0, 0xF14, x0 # copy hart ID to a0 + li a1, FDT_ADDRESS # This is the device tree address + la a2, end_of_bios + li t0, EXT_MEM_BASE # start of code + + jalr x0, t0, 0 + +end_of_bios: + + + + From 86ec7f609b1ae9d3f0c6323f34cc9d54f0deef4a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 22:06:38 -0500 Subject: [PATCH 059/232] Updated FPGA readme. --- fpga/README.md | 71 +++++++++++++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 32 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index dfa27479e..fbe9876cc 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -1,46 +1,53 @@ -The FPGA currently only targets the VCU118 board. +Wally supports the following boards -* Build Process +ArtyA7 +vcu108 +vcu118 + +* Quick Start + +** build FPGA cd generator -make +make -* Description +example +make vcu108 -The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4, -axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks -and builds wally. fpga/src/fpgaTop.v is the top level which instanciates -wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic -analyzer) which provides the current instruction PCM, instrM, etc along with -a large number of debuging signals. +** Make flash card image +ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. +Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). +cd $WALLY/linux/sd-card +This following script requires root. +./flash-sd.sh -b -d -* Programming the flash card -You'll need to write the linux image to the flash card. Use the convert2bin.py -script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt -file from QEMU's preload to generate the binary. Then to copy - sudo dd if=ram.bin of=. +example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc +./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc -* Loading the FPGA +Wait until the the script completes then remove the car. -After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's -gui and open the WallyFPGA.xpr project file. Open the hardware manager under -program and debug. Open target and then program with the bit file. +** FPGA setup -* Test Run +For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card. -Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide -status of the reset and ddr4 calibration. LED 7 should always be lit. -LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once -wally begins running. +For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards. -Next the bootloader program will copy the flash card into the DDR4 memory. -When this done the lower 5 LEDs will blink 5 times and then try to boot -the program loaded in the DDR4 memory at physical address 0x8000_0000. +Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch. +The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the +VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead. -* Connecting uart -You'll need to connect both usb cables. The first connects the FPGA programer -while the connect connects UART. UART is configured to use 57600 baud with -no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should -let you view the com port. +cd $WALLY/fpga/generator +vivado & +open the design in the current directory WallyFPGA.xpr. + +Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. + +** Connect to UART + +In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. + +screen /dev/ttyUSB1 115200 + +Swap out the USB1 for USB0 or USB1 as needed. From cdc0ecc87c2c0a03bd005f00f93c23a5d40799a8 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 22:08:09 -0500 Subject: [PATCH 060/232] FPGA readme now in markdown. --- fpga/README.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index fbe9876cc..3651661f0 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -4,9 +4,9 @@ ArtyA7 vcu108 vcu118 -* Quick Start +# Quick Start -** build FPGA +## build FPGA cd generator make @@ -14,7 +14,7 @@ make example make vcu108 -** Make flash card image +## Make flash card image ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). cd $WALLY/linux/sd-card @@ -26,7 +26,7 @@ example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash Wait until the the script completes then remove the car. -** FPGA setup +## FPGA setup For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card. @@ -43,7 +43,7 @@ open the design in the current directory WallyFPGA.xpr. Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. -** Connect to UART +## Connect to UART In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. From fed88f6b175a0ee537f69651655c4950a6368cac Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 14 Oct 2024 22:10:28 -0500 Subject: [PATCH 061/232] Better formatting for readme. --- fpga/README.md | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index 3651661f0..236bc7ddb 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -1,28 +1,32 @@ Wally supports the following boards -ArtyA7 -vcu108 -vcu118 +1. ArtyA7 +2. vcu108 +3. vcu118 (Do not recommend.) # Quick Start ## build FPGA -cd generator -make +`cd generator +make ` example -make vcu108 +`make vcu108` ## Make flash card image ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). -cd $WALLY/linux/sd-card + +`cd $WALLY/linux/sd-card` + This following script requires root. -./flash-sd.sh -b -d + +`./flash-sd.sh -b -d ` example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc -./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc + +`./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc` Wait until the the script completes then remove the car. @@ -36,8 +40,8 @@ Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead. -cd $WALLY/fpga/generator -vivado & +`cd $WALLY/fpga/generator +vivado &` open the design in the current directory WallyFPGA.xpr. @@ -47,7 +51,7 @@ Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. -screen /dev/ttyUSB1 115200 +`screen /dev/ttyUSB1 115200` Swap out the USB1 for USB0 or USB1 as needed. From d4fc3245b0e4d4421d65c6f04a94a91853bd4dad Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 15 Oct 2024 10:11:12 -0500 Subject: [PATCH 062/232] Removed ahbsdc submodule since it is no longer used. Updated old submodules pointing to ross144 to rosethompson repos. --- .gitmodules | 7 ++----- addins/ahbsdc | 1 - fpga/generator/wally.tcl | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) delete mode 160000 addins/ahbsdc diff --git a/.gitmodules b/.gitmodules index b066104f7..eed0bb58f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,14 +20,11 @@ branch = dev [submodule "addins/branch-predictor-simulator"] path = addins/branch-predictor-simulator - url = https://github.com/ross144/branch-predictor-simulator -[submodule "addins/ahbsdc"] - path = addins/ahbsdc - url = https://github.com/JacobPease/ahbsdc.git + url = https://github.com/rosethompson/branch-predictor-simulator [submodule "addins/verilog-ethernet"] sparseCheckout = true path = addins/verilog-ethernet - url = https://github.com/ross144/verilog-ethernet.git + url = https://github.com/rosethompson/verilog-ethernet.git [submodule "cvw-arch-verif"] path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif diff --git a/addins/ahbsdc b/addins/ahbsdc deleted file mode 160000 index 33418c8dc..000000000 --- a/addins/ahbsdc +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3 diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5151b0e77..3ca0c3360 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -47,7 +47,7 @@ if {$board=="ArtyA7"} { # read in all other rtl add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] -set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] +set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset] # define top level From 8fb1673ab321f251d797a14306e097b25d40d826 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 15 Oct 2024 10:27:53 -0500 Subject: [PATCH 063/232] Updated email address authorship for my files. --- bin/CModelBTBAccuracy.sh | 2 +- bin/CModelBranchAccuracy.sh | 2 +- bin/SeparateBranch.sh | 2 +- bin/extractFunctionRadix.sh | 2 +- bin/parseHPMC.py | 2 +- bin/wally-tool-chain-install.sh | 2 +- fpga/rvvidaemon/rvvidaemon.c | 2 +- fpga/src/fpgaTop.sv | 2 +- fpga/src/fpgaTopArtyA7.sv | 2 +- fpga/src/wallypipelinedsocwrapper.sv | 2 +- src/cache/cache.sv | 2 +- src/cache/cacheLRU.sv | 2 +- src/cache/cachefsm.sv | 2 +- src/cache/cacheway.sv | 2 +- src/cache/subcachelineread.sv | 2 +- src/ebu/ahbcacheinterface.sv | 2 +- src/ebu/ahbinterface.sv | 2 +- src/ebu/buscachefsm.sv | 2 +- src/ebu/busfsm.sv | 2 +- src/ebu/controllerinput.sv | 2 +- src/ebu/ebu.sv | 2 +- src/ebu/ebufsmarb.sv | 2 +- src/generic/arrs.sv | 2 +- src/generic/binencoder.sv | 2 +- src/generic/mem/ram1p1rwbe.sv | 2 +- src/generic/mem/ram1p1rwe.sv | 2 +- src/generic/mem/ram2p1r1wbe.sv | 2 +- src/generic/onehotdecoder.sv | 2 +- src/ifu/bpred/RASPredictor.sv | 2 +- src/ifu/bpred/bpred.sv | 2 +- src/ifu/bpred/btb.sv | 2 +- src/ifu/bpred/gshare.sv | 2 +- src/ifu/bpred/gsharebasic.sv | 2 +- src/ifu/bpred/icpred.sv | 2 +- src/ifu/bpred/localaheadbp.sv | 2 +- src/ifu/bpred/localbpbasic.sv | 2 +- src/ifu/bpred/localrepairbp.sv | 2 +- src/ifu/bpred/satCounter2.sv | 2 +- src/ifu/bpred/twoBitPredictor.sv | 2 +- src/ifu/irom.sv | 2 +- src/ifu/spill.sv | 2 +- src/lsu/align.sv | 2 +- src/lsu/atomic.sv | 2 +- src/lsu/dtim.sv | 2 +- src/lsu/lsu.sv | 2 +- src/rvvi/csrindextoaddr.sv | 2 +- src/rvvi/packetizer.sv | 2 +- src/rvvi/priorityaomux.sv | 2 +- src/rvvi/regchangedetect.sv | 2 +- src/rvvi/rvvisynth.sv | 2 +- src/rvvi/triggergen.sv | 2 +- testbench/common/DCacheFlushFSM.sv | 2 +- testbench/common/functionName.sv | 2 +- testbench/common/loggers.sv | 2 +- testbench/common/rvvitbwrapper.sv | 2 +- testbench/common/watchdog.sv | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S | 2 +- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S | 2 +- 60 files changed, 60 insertions(+), 60 deletions(-) diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 20a65bf98..504edf439 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 23 October 2023 ## Modified: ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 5e0e7bc01..039e38a8b 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 12 March 2023 ## Modified: ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index 87648589f..27e0b1962 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -1,7 +1,7 @@ #!/bin/bash ########################################### -## Written: ross1728@gmail.com +## Written: rose@rosethompson.net ## Created: 12 March 2023 ## Modified: ## diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh index a0480f855..c9446a3b5 100755 --- a/bin/extractFunctionRadix.sh +++ b/bin/extractFunctionRadix.sh @@ -4,7 +4,7 @@ ## extractFunctionRadix.sh ## ## Written: Rose Thompson -## email: ross1728@gmail.com +## email: rose@rosethompson.net ## Created: March 1, 2021 ## Modified: March 10, 2021 ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 4408f2211..c0137916f 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ########################################### -## Written: Rose Thompson ross1728@gmail.com +## Written: Rose Thompson rose@rosethompson.net ## Created: 20 September 2023 ## Modified: ## diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..d27e2a392 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -2,7 +2,7 @@ ########################################### ## Tool chain install script. ## -## Written: Rose Thompson ross1728@gmail.com +## Written: Rose Thompson rose@rosethompson.net ## Created: 18 January 2023 ## Modified: 22 January 2023 ## Modified: 23 March 2023 diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c index 1932038ad..3ac9c6f43 100644 --- a/fpga/rvvidaemon/rvvidaemon.c +++ b/fpga/rvvidaemon/rvvidaemon.c @@ -1,7 +1,7 @@ /////////////////////////////////////////// // rvvi daemon // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 31 May 2024 // Modified: 31 May 2024 // diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 0ecce067b..2bf6aee5e 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fpgaTop.sv // -// Written: ross1728@gmail.com November 17, 2021 +// Written: rose@rosethompson.net November 17, 2021 // Modified: // // Purpose: This is a top level for the fpga's implementation of wally. diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index cb350e08a..07c66ff95 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // fpgaTop.sv // -// Written: ross1728@gmail.com November 17, 2021 +// Written: rose@rosethompson.net November 17, 2021 // Modified: // // Purpose: This is a top level for the fpga's implementation of wally. diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index a1e907913..db382ade1 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // wallypipelinedsocwrapper.sv // -// Written: Rose Thompson ross1728@gmail.com 16 June 2023 +// Written: Rose Thompson rose@rosethompson.net 16 June 2023 // Modified: // // Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 4c89d08cc..5855afb03 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cache.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 79b277a03..7f1904bbd 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheLRU.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 20 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 28cdc7440..1a39ad17a 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cachefsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 25 August 2021 // Modified: 20 January 2023 // diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index fb9d39f41..addf1a019 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // cacheway // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 7 July 2021 // Modified: 20 January 2023 // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 2c340c092..262992b52 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // subcachelineread.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 4 February 2022 // Modified: 20 January 2023 // diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 572e824bb..f3fc676b0 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbcacheinterface.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 821633f71..5e5406c1f 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ahbinterface.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 9461bd5c5..f81bfa67a 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 9080dbb83..fbd6fe3f6 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // busfsm.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: December 29, 2021 // Modified: 18 January 2023 // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 1c4c360ec..9f644e1d3 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // controllerinput.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 31, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 8242d27e6..642eb6de4 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // abhmulticontroller // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: August 29, 2022 // Modified: 18 January 2023 // diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 2e7b345f2..853acd09b 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ebufsmarb.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 23 January 2023 // Modified: 23 January 2023 // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index c0d314dd5..9fa09f4b6 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // arrs.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: November 12, 2021 // // Purpose: resets are typically asynchronous but need to be synchronized to diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 83b245485..558eb759a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // binencoder.sv // -// Written: ross1728@gmail.com November 14, 2022 +// Written: rose@rosethompson.net November 14, 2022 // // Purpose: one-hot to binary encoding. // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index d17262d22..9151a35d2 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -2,7 +2,7 @@ // ram1p1r2be.sv // 1 port sram with byte enables // -// Written: ross1728@gmail.com +// Written: rose@rosethompson.net // Created: 3 May 2021 // Modified: 20 January 2023 // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index cdca14e38..84effae19 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -2,7 +2,7 @@ // ram1p1rwe.sv // 1 port sram. // -// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com) +// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net) // Created: 04 April 2023 // // Purpose: ram1p1wre, but without byte-enable. Used for icache data. diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 196aa0875..95840c2cc 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -2,7 +2,7 @@ // ram2p1r1wbe.sv // 2 port sram. // -// Written: ross1728@gmail.com May 3, 2021 +// Written: rose@rosethompson.net May 3, 2021 // Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 9b25feb65..91873c8e8 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // onehotdecoder.sv // -// Written: ross1728@gmail.com July 09, 2021 +// Written: rose@rosethompson.net July 09, 2021 // Modified: // // Purpose: Bin to one hot decoder. Power of 2 only. diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index d72f0e0d8..3bef28881 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // RASPredictor.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 15 February 2021 // Modified: 25 January 2023 // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 8d6a55d75..8b8793f27 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // bpred.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: 12 February 2021 // Modified: 19 January 2023 // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index e0ee0aaf4..6c6ace763 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // btb.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: February 15, 2021 // Modified: 24 January 2023 // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 057993536..46702e6b1 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -2,7 +2,7 @@ // gshare.sv // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) // Modified: 20 February 2023 diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index a0563d809..3f88494fe 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -2,7 +2,7 @@ // gsharebasic.sv // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. // Modified: 20 February 2023 diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 01ebaca01..0b1992210 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // icpred.sv // -// Written: Rose Thomposn ross1728@gmail.com +// Written: Rose Thomposn rose@rosethompson.net // Created: February 26, 2023 // Modified: February 26, 2023 // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index a2c7bda5a..e3d6ef8ed 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -2,7 +2,7 @@ // localaheadbp // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // // Purpose: local history branch predictor with ahead pipelining and SRAM memories. diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index b5634ef8a..5b2334a3d 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -2,7 +2,7 @@ // localbpbasic // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 16 March 2021 // // Purpose: Local history branch predictor. Basic implementation without any repair and flop memories. diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 5bb614d7f..e15c77f3c 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -2,7 +2,7 @@ // localrepairbp // // Written: Rose Thompson -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: 15 April 2023 // // Purpose: Local history branch predictor with speculation and repair using CBH. diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index f59cef82b..90cdf4f58 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -2,7 +2,7 @@ // satCounter2.sv // // Written: Rose Thomposn -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: February 13, 2021 // Modified: // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 52a04d6e4..2277f8b9b 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -2,7 +2,7 @@ // twoBitPredictor.sv // // Written: Rose Thomposn -// Email: ross1728@gmail.com +// Email: rose@rosethompson.net // Created: February 14, 2021 // Modified: // diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index ebebfbe4a..f85b60a5d 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // irom.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index c3c518913..f073398f3 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 28 January 2022 // Modified: 19 January 2023 // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index db37f4a66..f1e2e1892 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // spill.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 26 October 2023 // Modified: 26 October 2023 // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 8ad9159ce..cd87d70ac 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // atomic.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 31 January 2022 // Modified: 18 January 2023 // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 3fb6c81f6..f6530edc8 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // dtim.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 30 January 2022 // Modified: 18 January 2023 // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 08e62f9ad..a1dd85d98 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -1,7 +1,7 @@ ///////////////////////////////////////////////////////////////////////////////////////////////////////// // lsu.sv // -// Written: David_Harris@hmc.edu, ross1728@gmail.com +// Written: David_Harris@hmc.edu, rose@rosethompson.net // Created: 9 January 2021 // Modified: 11 January 2023 // diff --git a/src/rvvi/csrindextoaddr.sv b/src/rvvi/csrindextoaddr.sv index 0a843f491..4612dd4ee 100644 --- a/src/rvvi/csrindextoaddr.sv +++ b/src/rvvi/csrindextoaddr.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // csrindextoaddr.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 77c58f467..29a58d383 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // packetizer.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 21 May 2024 // Modified: 21 May 2024 // diff --git a/src/rvvi/priorityaomux.sv b/src/rvvi/priorityaomux.sv index d542c946f..7b119a81f 100644 --- a/src/rvvi/priorityaomux.sv +++ b/src/rvvi/priorityaomux.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // priorityaomux.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/regchangedetect.sv b/src/rvvi/regchangedetect.sv index 8becf867d..31d4ea1ec 100644 --- a/src/rvvi/regchangedetect.sv +++ b/src/rvvi/regchangedetect.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // regchangedetect.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 24 January 2024 // Modified: 24 January 2024 // diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index aa1c55aef..3e8170c93 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // rvvisynth.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: 23 January 2024 // Modified: 23 January 2024 // diff --git a/src/rvvi/triggergen.sv b/src/rvvi/triggergen.sv index 0a4269024..a4e74de91 100644 --- a/src/rvvi/triggergen.sv +++ b/src/rvvi/triggergen.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // triggergen.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Created: June 26, 2024 // Modified: June 26, 2024 // diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index cde584af2..5764ce26b 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // DCacheFlushFSM.sv // -// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com +// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index eac58f40a..5a14c84a4 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // functionName.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // // Purpose: decode name of function // diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index a9edb7892..6b026257a 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: Log branch instructions, log instruction fetches, diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv index bd964d40d..f9c1f316c 100644 --- a/testbench/common/rvvitbwrapper.sv +++ b/testbench/common/rvvitbwrapper.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // loggers.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 24 July 2024 // // Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench. diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv index 9dbf6fa8b..f4b02a2e3 100644 --- a/testbench/common/watchdog.sv +++ b/testbench/common/watchdog.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // watchdog.sv // -// Written: Rose Thompson ross1728@gmail.com +// Written: Rose Thompson rose@rosethompson.net // Modified: 14 June 2023 // // Purpose: Detects if the processor is stuck and halts the simulation diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S index 2edd1fc55..f3e3846f3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 18 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S index ceb3c3603..2df8c246f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 22 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S index 31b11874b..e0c724aec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 18 August 2023 // diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S index 97c3946eb..0e615a943 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S @@ -3,7 +3,7 @@ // WALLY-cache-management-tests // invalidate, clean, and flush // -// Author: Rose Thompson +// Author: Rose Thompson // // Created 22 August 2023 // From 150641e5d329412626ad418fad1557c021d89578 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 15 Oct 2024 09:08:25 -0700 Subject: [PATCH 064/232] Implemented mhpmevent[3:31] as read-only zero rather than illegal --- src/privileged/csrc.sv | 66 ++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 31 deletions(-) diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index 848cb7e01..8b292513b 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -8,7 +8,6 @@ // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // // Documentation: RISC-V System on Chip Design -// MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -66,7 +65,8 @@ module csrc import cvw::*; #(parameter cvw_t P) ( localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul; localparam MHPMCOUNTERHBASE = 12'hB80; localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault - localparam MHPMEVENTBASE = 12'h320; + localparam MHPMEVENTBASE = 12'h323; + localparam MHPMEVENTLAST = 12'h33F; localparam HPMCOUNTERBASE = 12'hC00; localparam HPMCOUNTERHBASE = 12'hC80; localparam TIME = 12'hC01; @@ -156,37 +156,41 @@ module csrc import cvw::*; #(parameter cvw_t P) ( if (PrivilegeModeW == P.M_MODE | MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin IllegalCSRCAccessM = 1'b0; - if (P.XLEN==64) begin // 64-bit counter reads - // Veri lator doesn't realize this only occurs for XLEN=64 - /* verilator lint_off WIDTH */ - if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT - /* verilator lint_on WIDTH */ - else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else begin + if (CSRAdrM >= MHPMEVENTBASE & CSRAdrM <= MHPMEVENTLAST) begin + CSRCReadValM = '0; // mphmevent[3:31] tied to read-only zero + end else begin + if (P.XLEN==64) begin // 64-bit counter reads + // Veri lator doesn't realize this only occurs for XLEN=64 + /* verilator lint_off WIDTH */ + if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT + /* verilator lint_on WIDTH */ + else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else begin + CSRCReadValM = '0; + IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist + end + end else begin // 32-bit counter reads + // Veril ator doesn't realize this only occurs for XLEN=32 + /* verilator lint_off WIDTH */ + if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT + else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32]; + /* verilator lint_on WIDTH */ + else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH) + CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; + else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only + CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; + else begin CSRCReadValM = '0; - IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist + IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist + end end - end else begin // 32-bit counter reads - // Veril ator doesn't realize this only occurs for XLEN=32 - /* verilator lint_off WIDTH */ - if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT - else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32]; - /* verilator lint_on WIDTH */ - else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH) - CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only - CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; - else begin - CSRCReadValM = '0; - IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist - end end end else begin CSRCReadValM = '0; From 69898f65da527ece235c4135cb8df2cd41b3d3c4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 15 Oct 2024 09:09:42 -0700 Subject: [PATCH 065/232] Disabled some features in imperasdv not implemented by Wally --- config/rv32gc/imperas.ic | 18 ++++++++++++++++++ config/rv64gc/imperas.ic | 20 ++++++++++++++------ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index fe4a3dbed..9e9eef55f 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -59,6 +59,24 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T +# context registers not implemented +--override cpu/scontext_undefined=T +--override cpu/mcontext_undefined=T + +# nonratified mnosie register not implemented +--override cpu/mnoise_undefined=T + +# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag +#--override cpu/ecode_mask=0x8000000F # for RV32 +--override cpu/ecode_mask=0x800000000000000F # for RV64 + +# Debug mode not yet supported +--override cpu/debug_mode=none + +# Zkr entropy source and seed register not supported. +--override cpu/Zkr=F + + --override cpu/reset_address=0x80000000 --override cpu/unaligned=F # Zicclsm (should be true) diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 1b038c920..31584d22d 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -57,15 +57,23 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T +# context registers not implemented --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T + +# nonratified mnosie register not implemented --override cpu/mnoise_undefined=T -# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers -#--override cpu/seed_undefined=T -#--override mhpmevent3_undefined=T -#--override cpu/mseccfg_undefined=T -#--override cpu/tselect_undefined=T -#--override cpu/tdata1_undefined=T + +# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag +#--override cpu/ecode_mask=0x8000000F # for RV32 +--override cpu/ecode_mask=0x800000000000000F # for RV64 + +# Debug mode not yet supported +--override cpu/debug_mode=none + +# Zkr entropy source and seed register not supported. +--override cpu/Zkr=F + --override cpu/reset_address=0x80000000 From 58018ceff6921dc2fdaa7dc982a4862a043db012 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:14:24 -0700 Subject: [PATCH 066/232] More rocky testing --- .github/workflows/{rocky.yml => rockyInstall.yml} | 6 +++--- .github/workflows/rockytest.yml | 15 +++++++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) rename .github/workflows/{rocky.yml => rockyInstall.yml} (91%) create mode 100644 .github/workflows/rockytest.yml diff --git a/.github/workflows/rocky.yml b/.github/workflows/rockyInstall.yml similarity index 91% rename from .github/workflows/rocky.yml rename to .github/workflows/rockyInstall.yml index be64697c0..e01ea855f 100644 --- a/.github/workflows/rocky.yml +++ b/.github/workflows/rockyInstall.yml @@ -1,4 +1,4 @@ -name: Installation test +name: Rocky installation test on: [workflow_dispatch] @@ -7,7 +7,7 @@ jobs: name: Test installation on Rocky 9 runs-on: ubuntu-latest defaults: - run: + run: shell: bash steps: @@ -19,4 +19,4 @@ jobs: - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh - + diff --git a/.github/workflows/rockytest.yml b/.github/workflows/rockytest.yml new file mode 100644 index 000000000..03fda22ae --- /dev/null +++ b/.github/workflows/rockytest.yml @@ -0,0 +1,15 @@ +name: Rocky Linux 8 Workflow + +on: [workflow_dispatch] + +jobs: + build: + runs-on: ubuntu-latest + steps: + - name: parent os + run: cat /etc/os-release + - name: docker os + uses: docker://rockylinux:8 + with: + entrypoint: /bin/bash + args: cat /etc/os-release \ No newline at end of file From 06f909f9bf457c30426b453fd0740d1e60645efb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:22:53 -0700 Subject: [PATCH 067/232] New rocky approach --- .github/workflows/rockyInstall.yml | 17 +++++++++-------- .github/workflows/rockytest.yml | 15 --------------- 2 files changed, 9 insertions(+), 23 deletions(-) delete mode 100644 .github/workflows/rockytest.yml diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index e01ea855f..cd4c324ee 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -6,16 +6,17 @@ jobs: install: name: Test installation on Rocky 9 runs-on: ubuntu-latest - defaults: - run: - shell: bash - + container: + image: rockylinux:8 + options: --privileged --mount type=bind, source=/, target=/ steps: - - run: df -h - - name: free up storage - run: sudo rm -rf /usr/local/lib/android - - run: docker run -ia rockylinux:8 + - name: check distro + run: cat /etc/os-release - run: dnf install -y sudo + - name: free up storage + run: | + df -h + sudo rm -rf /usr/local/lib/android - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh diff --git a/.github/workflows/rockytest.yml b/.github/workflows/rockytest.yml deleted file mode 100644 index 03fda22ae..000000000 --- a/.github/workflows/rockytest.yml +++ /dev/null @@ -1,15 +0,0 @@ -name: Rocky Linux 8 Workflow - -on: [workflow_dispatch] - -jobs: - build: - runs-on: ubuntu-latest - steps: - - name: parent os - run: cat /etc/os-release - - name: docker os - uses: docker://rockylinux:8 - with: - entrypoint: /bin/bash - args: cat /etc/os-release \ No newline at end of file From f910564fa4fd950ec84cebc9420d72055471795f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:26:41 -0700 Subject: [PATCH 068/232] Update rocky.yml for Rocky 8 testing --- .github/workflows/rockyInstall.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index cd4c324ee..cd35bd855 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -4,11 +4,11 @@ on: [workflow_dispatch] jobs: install: - name: Test installation on Rocky 9 + name: Test installation on Rocky 8 runs-on: ubuntu-latest container: image: rockylinux:8 - options: --privileged --mount type=bind, source=/, target=/ + options: --privileged --mount type=bind,source=/,target=/ steps: - name: check distro run: cat /etc/os-release From 919fd8c2db2c33c8cc01d2e568c4d6591a57909b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:28:12 -0700 Subject: [PATCH 069/232] Update rocky.yml for Rocky 8 testing --- .github/workflows/rockyInstall.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index cd35bd855..ab3780c4a 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -8,7 +8,7 @@ jobs: runs-on: ubuntu-latest container: image: rockylinux:8 - options: --privileged --mount type=bind,source=/,target=/ + options: --privileged --mount type=bind,source=/,target=/host steps: - name: check distro run: cat /etc/os-release @@ -16,7 +16,7 @@ jobs: - name: free up storage run: | df -h - sudo rm -rf /usr/local/lib/android + sudo rm -rf /host/usr/local/lib/android - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh From c0ffc56d3857fc53b0d7c7efb480e7ae81599fef Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 15 Jul 2024 23:32:43 -0700 Subject: [PATCH 070/232] Save space on rocky --- .github/workflows/rockyInstall.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml index ab3780c4a..627ab6bcc 100644 --- a/.github/workflows/rockyInstall.yml +++ b/.github/workflows/rockyInstall.yml @@ -17,6 +17,10 @@ jobs: run: | df -h sudo rm -rf /host/usr/local/lib/android + sudo rm -rf /host/usr/share/dotnet &> /dev/null + sudo rm -rf /host/opt/ghc &> /dev/null + sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null + df -h - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh From 5811099446104fab2ce0668270fe0a05e98d3857 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:14:57 -0700 Subject: [PATCH 071/232] Test all supported distros --- .github/workflows/install.yml | 37 +++++++++++++++++++++++++----- .github/workflows/rockyInstall.yml | 27 ---------------------- 2 files changed, 31 insertions(+), 33 deletions(-) delete mode 100644 .github/workflows/rockyInstall.yml diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b3cc2b6f4..ac25d884b 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,12 +1,14 @@ -name: Installation test +name: Installation on: [workflow_dispatch] jobs: - install: - name: Test installation on Ubuntu 22.04LTS - runs-on: ubuntu-22.04 - + ubuntu_install: + name: Test installation on ${{ matrix.os }} + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: [ubuntu-20.04, ubuntu-22.04, ubuntu-24.04] steps: - name: Free up storage run: | @@ -34,4 +36,27 @@ jobs: - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh - + rhel_family_install: + name: Test installation on ${{ matrix.os }} + runs-on: ubuntu-latest + container: + image: ${{ matrix.os }} + options: --privileged --mount type=bind,source=/,target=/host + strategy: + matrix: + os: [rockylinux:8, rockylinux:9, almalinux:8, almalinux:9] + steps: + - name: check distro + run: cat /etc/os-release + - run: dnf install -y sudo + - name: free up storage + run: | + df -h + sudo rm -rf /host/usr/local/lib/android + sudo rm -rf /host/usr/share/dotnet &> /dev/null + sudo rm -rf /host/opt/ghc &> /dev/null + sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null + df -h + - uses: actions/checkout@v4 + - name: install + run: ./bin/wally-tool-chain-install.sh diff --git a/.github/workflows/rockyInstall.yml b/.github/workflows/rockyInstall.yml deleted file mode 100644 index 627ab6bcc..000000000 --- a/.github/workflows/rockyInstall.yml +++ /dev/null @@ -1,27 +0,0 @@ -name: Rocky installation test - -on: [workflow_dispatch] - -jobs: - install: - name: Test installation on Rocky 8 - runs-on: ubuntu-latest - container: - image: rockylinux:8 - options: --privileged --mount type=bind,source=/,target=/host - steps: - - name: check distro - run: cat /etc/os-release - - run: dnf install -y sudo - - name: free up storage - run: | - df -h - sudo rm -rf /host/usr/local/lib/android - sudo rm -rf /host/usr/share/dotnet &> /dev/null - sudo rm -rf /host/opt/ghc &> /dev/null - sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null - df -h - - uses: actions/checkout@v4 - - name: install - run: ./bin/wally-tool-chain-install.sh - From 978c6b3d1477d11fbfa58f366267aededb488eee Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:17:16 -0700 Subject: [PATCH 072/232] Add quotes --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ac25d884b..074b5a408 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,7 +8,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - os: [ubuntu-20.04, ubuntu-22.04, ubuntu-24.04] + os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - name: Free up storage run: | @@ -44,7 +44,7 @@ jobs: options: --privileged --mount type=bind,source=/,target=/host strategy: matrix: - os: [rockylinux:8, rockylinux:9, almalinux:8, almalinux:9] + os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - name: check distro run: cat /etc/os-release From f0b42abd88a0b22f422f4a90212e60a582b740b1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:22:45 -0700 Subject: [PATCH 073/232] fewer targets --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 074b5a408..1fd07a8ca 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,7 +8,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] + os: ["ubuntu-20.04", "ubuntu-22.04"] steps: - name: Free up storage run: | @@ -44,7 +44,7 @@ jobs: options: --privileged --mount type=bind,source=/,target=/host strategy: matrix: - os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] + os: ["rockylinux:8", "almalinux:8"] steps: - name: check distro run: cat /etc/os-release From d7af9bbccbf6d42114d9d4093c1cb562828b06ae Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:33:56 -0700 Subject: [PATCH 074/232] Continue install tests if one fails --- .github/workflows/install.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 1fd07a8ca..51940249a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -7,6 +7,7 @@ jobs: name: Test installation on ${{ matrix.os }} runs-on: ${{ matrix.os }} strategy: + fail-fast: false matrix: os: ["ubuntu-20.04", "ubuntu-22.04"] steps: @@ -43,6 +44,7 @@ jobs: image: ${{ matrix.os }} options: --privileged --mount type=bind,source=/,target=/host strategy: + fail-fast: false matrix: os: ["rockylinux:8", "almalinux:8"] steps: From 59b8eacf70691efd8e972beeb63784ead48fb524 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:41:54 -0700 Subject: [PATCH 075/232] Add test.yml --- .github/workflows/test.yml | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 000000000..54b201622 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,38 @@ +name: test + +on: [workflow_dispatch] + +jobs: + ubuntu_install: + name: Test installation on ${{ matrix.os }} + runs-on: ${{ matrix.os }} + strategy: + fail-fast: false + matrix: + os: ["ubuntu-20.04", "ubuntu-22.04"] + steps: + - uses: actions/checkout@v4 + - name: check + run: | + pwd + ls + cd cvw + ls + rhel_family_install: + name: Test installation on ${{ matrix.os }} + runs-on: ubuntu-latest + container: + image: ${{ matrix.os }} + options: --privileged --mount type=bind,source=/,target=/host + strategy: + fail-fast: false + matrix: + os: ["rockylinux:8", "almalinux:8"] + steps: + - uses: actions/checkout@v4 + - name: check + run: | + pwd + ls + cd cvw + ls From 6b582cc24885928a417cd94c84343d502e2b3a95 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:43:21 -0700 Subject: [PATCH 076/232] Update test --- .github/workflows/test.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 54b201622..50b85c2e7 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -16,8 +16,8 @@ jobs: run: | pwd ls - cd cvw - ls + source setup.sh + echo $PATH rhel_family_install: name: Test installation on ${{ matrix.os }} runs-on: ubuntu-latest @@ -34,5 +34,5 @@ jobs: run: | pwd ls - cd cvw - ls + source setup.sh + echo $PATH From 17b3013f8d366f6385b9c57eb3b4a176d7e5a190 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:44:32 -0700 Subject: [PATCH 077/232] update test --- .github/workflows/test.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 50b85c2e7..0c95356f3 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -16,6 +16,7 @@ jobs: run: | pwd ls + mkdir /opt/riscv source setup.sh echo $PATH rhel_family_install: @@ -34,5 +35,6 @@ jobs: run: | pwd ls + mkdir /opt/riscv source setup.sh echo $PATH From 479a59e44be676ac3a3b91e19c2835f35881a5a8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 00:47:38 -0700 Subject: [PATCH 078/232] Run make and regression-wally in installation test --- .github/workflows/install.yml | 12 +++++++++++ .github/workflows/test.yml | 40 ----------------------------------- 2 files changed, 12 insertions(+), 40 deletions(-) delete mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 51940249a..4c2e36afd 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -37,6 +37,12 @@ jobs: - uses: actions/checkout@v4 - name: install run: sudo ./bin/wally-tool-chain-install.sh + - name: setup + run: source setup.sh + - name: make tests + run: make + - name: regresssion + run: regression-wally rhel_family_install: name: Test installation on ${{ matrix.os }} runs-on: ubuntu-latest @@ -62,3 +68,9 @@ jobs: - uses: actions/checkout@v4 - name: install run: ./bin/wally-tool-chain-install.sh + - name: setup + run: source setup.sh + - name: make tests + run: make + - name: regresssion + run: regression-wally diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml deleted file mode 100644 index 0c95356f3..000000000 --- a/.github/workflows/test.yml +++ /dev/null @@ -1,40 +0,0 @@ -name: test - -on: [workflow_dispatch] - -jobs: - ubuntu_install: - name: Test installation on ${{ matrix.os }} - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: ["ubuntu-20.04", "ubuntu-22.04"] - steps: - - uses: actions/checkout@v4 - - name: check - run: | - pwd - ls - mkdir /opt/riscv - source setup.sh - echo $PATH - rhel_family_install: - name: Test installation on ${{ matrix.os }} - runs-on: ubuntu-latest - container: - image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host - strategy: - fail-fast: false - matrix: - os: ["rockylinux:8", "almalinux:8"] - steps: - - uses: actions/checkout@v4 - - name: check - run: | - pwd - ls - mkdir /opt/riscv - source setup.sh - echo $PATH From fab1b6eab99a64424c7b084e0bb840435c372cea Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:08:52 -0700 Subject: [PATCH 079/232] Checkout submodules in install test action --- .github/workflows/install.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4c2e36afd..31018d685 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -35,6 +35,8 @@ jobs: sudo apt-get clean &> /dev/null df -h - uses: actions/checkout@v4 + with: + submodules: recursive - name: install run: sudo ./bin/wally-tool-chain-install.sh - name: setup @@ -54,8 +56,6 @@ jobs: matrix: os: ["rockylinux:8", "almalinux:8"] steps: - - name: check distro - run: cat /etc/os-release - run: dnf install -y sudo - name: free up storage run: | @@ -66,6 +66,8 @@ jobs: sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null df -h - uses: actions/checkout@v4 + with: + submodules: recursive - name: install run: ./bin/wally-tool-chain-install.sh - name: setup From 4b534acde81edab1c330e403e409bf2d51ec0913 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:13:40 -0700 Subject: [PATCH 080/232] add test --- .github/workflows/test.yml | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 000000000..04285aaf3 --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,38 @@ +name: List Storage Space +on: [workflow_dispatch] + + +jobs: + storage-space: + runs-on: ubuntu-22 + + steps: + - name: Root + run: | + df -h + cd / + du -h --max-depth=1 / | sort -h + - name: /usr + run: | + cd /usr + du -h --max-depth=1 / | sort -h + - name: /usr/bin + run: | + cd /usr/bin + du -h --max-depth=1 / | sort -h + - name: /usr/local + run: | + cd /usr/local + du -h --max-depth=1 / | sort -h + - name: /usr/share + run: | + cd /usr/share + du -h --max-depth=1 / | sort -h + - name: /opt + run: | + cd /opt + du -h --max-depth=1 / | sort -h + - name: /opt/hostedtoolcache + run: | + cd /opt/hostedtoolcache + du -h --max-depth=1 / | sort -h From f8b078d0d8f1e2b06dc6c236b7d52032b9c23df5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:20:29 -0700 Subject: [PATCH 081/232] install git in redhat docker test --- .github/workflows/install.yml | 2 +- .github/workflows/test.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 31018d685..4f29a6be1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -56,7 +56,7 @@ jobs: matrix: os: ["rockylinux:8", "almalinux:8"] steps: - - run: dnf install -y sudo + - run: dnf install -y sudo git - name: free up storage run: | df -h diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 04285aaf3..1a9c1d8d6 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -4,7 +4,7 @@ on: [workflow_dispatch] jobs: storage-space: - runs-on: ubuntu-22 + runs-on: ubuntu-22.04 steps: - name: Root From c8f473b6b71199b40c7f1cbe9d1484d07ae05945 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 07:22:01 -0700 Subject: [PATCH 082/232] update test --- .github/workflows/test.yml | 42 +++++++++----------------------------- 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 1a9c1d8d6..a4b65cfcb 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -3,36 +3,14 @@ on: [workflow_dispatch] jobs: - storage-space: - runs-on: ubuntu-22.04 - + check-packages: + name: Test installation on ${{ matrix.os }} + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - - name: Root - run: | - df -h - cd / - du -h --max-depth=1 / | sort -h - - name: /usr - run: | - cd /usr - du -h --max-depth=1 / | sort -h - - name: /usr/bin - run: | - cd /usr/bin - du -h --max-depth=1 / | sort -h - - name: /usr/local - run: | - cd /usr/local - du -h --max-depth=1 / | sort -h - - name: /usr/share - run: | - cd /usr/share - du -h --max-depth=1 / | sort -h - - name: /opt - run: | - cd /opt - du -h --max-depth=1 / | sort -h - - name: /opt/hostedtoolcache - run: | - cd /opt/hostedtoolcache - du -h --max-depth=1 / | sort -h + - name: check packages + run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr + + From a384f22554c607e59e020139e313baa73777c999 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 22:43:42 -0700 Subject: [PATCH 083/232] Update test.yml --- .github/workflows/test.yml | 99 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 3 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a4b65cfcb..b41c784bf 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -3,14 +3,107 @@ on: [workflow_dispatch] jobs: - check-packages: - name: Test installation on ${{ matrix.os }} + clean-ubuntu: + name: clean ${{ matrix.os }} runs-on: ${{ matrix.os }} strategy: + fail-fast: false matrix: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: + - run: df -h + - name: remove packages + run: | + removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) + for pack in "${removePacks[@]}"; do + echo "REMOVING ${pack}" + sudo apt-get purge -y $pack || true + done + sudo apt-get autoremove -y + sudo apt-get clean + - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr + - name: remove dirs + run: | + sudo rm -rf /usr/local/lib/android + sudo rm -rf /usr/share/dotnet + sudo rm -rf /usr/share/swift + sudo rm -rf /usr/share/miniconda + sudo rm -rf /usr/share/az* + sudo rm -rf /usr/share/gradle-* + sudo rm -rf /usr/share/sbt + sudo rm -rf /opt/ghc + sudo rm -rf /usr/local/.ghcup + sudo rm -rf /usr/local/share/powershell + sudo rm -rf /usr/local/lib/node_modules + sudo rm -rf /usr/local/julia* + sudo rm -rf /usr/local/share/chromium + sudo rm -rf /usr/local/share/vcpkg + sudo rm -rf /usr/local/games + sudo rm -rf /usr/local/sqlpackage + sudo rm -rf /usr/lib/google-cloud-sdk + sudo rm -rf /usr/lib/jvm + sudo rm -rf /usr/lib/mono + sudo rm -rf /usr/lib/R + sudo rm -rf /usr/lib/postgresql + sudo rm -rf /usr/lib/heroku + sudo rm -rf /usr/lib/llvm* + sudo rm -rf /usr/lib/firefox + sudo rm -rf /opt/hostedtoolcache + sudo docker image prune --all --force + - run: df -h - + clean-rhel: + name: clean ${{ matrix.os }} + runs-on: ubuntu-latest + container: + image: ${{ matrix.os }} + options: --privileged --mount type=bind,source=/,target=/host + strategy: + fail-fast: false + matrix: + os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] + steps: + - run: df -h + - name: remove packages + run: | + removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) + for pack in "${removePacks[@]}"; do + echo "REMOVING ${pack}" + sudo apt-get purge -y $pack || true + done + sudo apt-get autoremove -y + sudo apt-get clean + - run: df -h + - name: check packages + run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr + - name: remove dirs + run: | + sudo rm -rf host/usr/local/lib/android + sudo rm -rf host/usr/share/dotnet + sudo rm -rf host/usr/share/swift + sudo rm -rf host/usr/share/miniconda + sudo rm -rf host/usr/share/az* + sudo rm -rf host/usr/share/gradle-* + sudo rm -rf host/usr/share/sbt + sudo rm -rf host/opt/ghc + sudo rm -rf host/usr/local/.ghcup + sudo rm -rf host/usr/local/share/powershell + sudo rm -rf host/usr/local/lib/node_modules + sudo rm -rf host/usr/local/julia* + sudo rm -rf host/usr/local/share/chromium + sudo rm -rf host/usr/local/share/vcpkg + sudo rm -rf host/usr/local/games + sudo rm -rf host/usr/local/sqlpackage + sudo rm -rf host/usr/lib/google-cloud-sdk + sudo rm -rf host/usr/lib/jvm + sudo rm -rf host/usr/lib/mono + sudo rm -rf host/usr/lib/R + sudo rm -rf host/usr/lib/postgresql + sudo rm -rf host/usr/lib/heroku + sudo rm -rf host/usr/lib/llvm* + sudo rm -rf host/usr/lib/firefox + sudo rm -rf host/opt/hostedtoolcache + sudo docker image prune --all --force + - run: df -h From 72e1125c632cbdc222d11a96e943cb2eb853504c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 16 Jul 2024 23:51:29 -0700 Subject: [PATCH 084/232] Update test.yml --- .github/workflows/test.yml | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index b41c784bf..315a9a89b 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -59,22 +59,17 @@ jobs: runs-on: ubuntu-latest container: image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host + options: --privileged --mount type=bind,source=/,target=/host --pid=host strategy: fail-fast: false matrix: os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] steps: + - uses: actions/checkout@v4 - run: df -h - name: remove packages run: | - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) - for pack in "${removePacks[@]}"; do - echo "REMOVING ${pack}" - sudo apt-get purge -y $pack || true - done - sudo apt-get autoremove -y - sudo apt-get clean + nsenter -t 1 -m -u -n -i bash .github/cli-space-cleanup.sh - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From a8105f058d3dc90ab5c0e040acaa7bfab1212ad8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:17:07 -0700 Subject: [PATCH 085/232] Create cli-space-cleanup.sh --- .github/cli-space-cleanup.sh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 .github/cli-space-cleanup.sh diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh new file mode 100644 index 000000000..035fede94 --- /dev/null +++ b/.github/cli-space-cleanup.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) +for pack in "${removePacks[@]}"; do + echo "REMOVING ${pack}" + sudo apt-get purge -y $pack || true +done +sudo apt-get autoremove -y +sudo apt-get clean From 82f8a78f1d329913193f30ce0775a3d166f627e5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:20:46 -0700 Subject: [PATCH 086/232] Update test.yml --- .github/workflows/test.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 315a9a89b..13dda37a0 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -65,11 +65,11 @@ jobs: matrix: os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] steps: + - run: dnf install -y sudo git - uses: actions/checkout@v4 - run: df -h - name: remove packages - run: | - nsenter -t 1 -m -u -n -i bash .github/cli-space-cleanup.sh + run: nsenter -t 1 -m -u -n -i bash /__w/cvw/cvw/.github/cli-space-cleanup.sh - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From ca7f95d5d2b4f62f592da96a33008b98d6f852b4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:52:49 -0700 Subject: [PATCH 087/232] make cli-space-cleanup executable --- .github/cli-space-cleanup.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 .github/cli-space-cleanup.sh diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh old mode 100644 new mode 100755 From 22b3a9bfd1c3ba677bc6affd099adedd5cda9cbb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:35:13 -0700 Subject: [PATCH 088/232] Update test.yml --- .github/workflows/test.yml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 13dda37a0..567578e2e 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -57,9 +57,12 @@ jobs: clean-rhel: name: clean ${{ matrix.os }} runs-on: ubuntu-latest + defaults: + run: + shell: bash container: image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash strategy: fail-fast: false matrix: @@ -69,7 +72,10 @@ jobs: - uses: actions/checkout@v4 - run: df -h - name: remove packages - run: nsenter -t 1 -m -u -n -i bash /__w/cvw/cvw/.github/cli-space-cleanup.sh + run: | + cd .github + ls + nsenter -t 1 -m -u -n -i bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From cd0c090658387552d376d7d10ca040f440cd77f5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 00:59:51 -0700 Subject: [PATCH 089/232] Update cli-space-cleanup.sh --- .github/cli-space-cleanup.sh | 2 -- 1 file changed, 2 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 035fede94..8fd1cfdc8 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -1,5 +1,3 @@ -#!/bin/bash - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) for pack in "${removePacks[@]}"; do echo "REMOVING ${pack}" From db2cfa88caaedc9d4392408d55328479a108b817 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:23:16 -0700 Subject: [PATCH 090/232] Update test.yml --- .github/workflows/test.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 567578e2e..ff414f151 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -75,7 +75,10 @@ jobs: run: | cd .github ls - nsenter -t 1 -m -u -n -i bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" + echo "Standard bash" + bash cli-space-cleanup.sh + echo "nsenter bash" + nsenter -t 1 -m -u -n -i /bin/bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From f5dac34fb740f200ef626269d4a07e96536bc5cf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:25:06 -0700 Subject: [PATCH 091/232] Update install test with space saver --- .github/workflows/install.yml | 90 +++++++++++++++++++++++++---------- 1 file changed, 64 insertions(+), 26 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4f29a6be1..36453511f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -9,30 +9,44 @@ jobs: strategy: fail-fast: false matrix: - os: ["ubuntu-20.04", "ubuntu-22.04"] + os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - name: Free up storage run: | - sudo rm -rf /usr/local/lib/android &> /dev/null - sudo rm -rf /usr/share/dotnet &> /dev/null - sudo rm -rf /opt/ghc &> /dev/null - sudo rm -rf /opt/hostedtoolcache/CodeQL &> /dev/null - sudo docker image prune --all --force &> /dev/null - sudo apt-get purge -y \ - '^llvm-.*' \ - 'php.*' \ - '^mongodb-.*' \ - '^mysql-.*' \ - azure-cli \ - google-cloud-cli \ - google-chrome-stable \ - firefox \ - powershell \ - microsoft-edge-stable \ - mono-devel \ - &> /dev/null + df -h + removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) + for pack in "${removePacks[@]}"; do + sudo apt-get purge -y $pack &> /dev/null || true + done sudo apt-get autoremove -y &> /dev/null sudo apt-get clean &> /dev/null + + sudo rm -rf /usr/local/lib/android &> /dev/null + sudo rm -rf /usr/share/dotnet &> /dev/null + sudo rm -rf /usr/share/swift &> /dev/null + sudo rm -rf /usr/share/miniconda &> /dev/null + sudo rm -rf /usr/share/az* &> /dev/null + sudo rm -rf /usr/share/gradle-* &> /dev/null + sudo rm -rf /usr/share/sbt &> /dev/null + sudo rm -rf /opt/ghc &> /dev/null + sudo rm -rf /usr/local/.ghcup &> /dev/null + sudo rm -rf /usr/local/share/powershell &> /dev/null + sudo rm -rf /usr/local/lib/node_modules &> /dev/null + sudo rm -rf /usr/local/julia* &> /dev/null + sudo rm -rf /usr/local/share/chromium &> /dev/null + sudo rm -rf /usr/local/share/vcpkg &> /dev/null + sudo rm -rf /usr/local/games &> /dev/null + sudo rm -rf /usr/local/sqlpackage &> /dev/null + sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null + sudo rm -rf /usr/lib/jvm &> /dev/null + sudo rm -rf /usr/lib/mono &> /dev/null + sudo rm -rf /usr/lib/R &> /dev/null + sudo rm -rf /usr/lib/postgresql &> /dev/null + sudo rm -rf /usr/lib/heroku &> /dev/null + sudo rm -rf /usr/lib/llvm* &> /dev/null + sudo rm -rf /usr/lib/firefox &> /dev/null + sudo rm -rf /opt/hostedtoolcache &> /dev/null + sudo docker image prune --all --force &> /dev/null df -h - uses: actions/checkout@v4 with: @@ -45,6 +59,7 @@ jobs: run: make - name: regresssion run: regression-wally + rhel_family_install: name: Test installation on ${{ matrix.os }} runs-on: ubuntu-latest @@ -54,25 +69,48 @@ jobs: strategy: fail-fast: false matrix: - os: ["rockylinux:8", "almalinux:8"] + os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - run: dnf install -y sudo git - name: free up storage run: | df -h - sudo rm -rf /host/usr/local/lib/android + sudo rm -rf /host/usr/local/lib/android &> /dev/null sudo rm -rf /host/usr/share/dotnet &> /dev/null + sudo rm -rf /host/usr/share/swift &> /dev/null + sudo rm -rf /host/usr/share/miniconda &> /dev/null + sudo rm -rf /host/usr/share/az* &> /dev/null + sudo rm -rf /host/usr/share/gradle-* &> /dev/null + sudo rm -rf /host/usr/share/sbt &> /dev/null sudo rm -rf /host/opt/ghc &> /dev/null - sudo rm -rf /host/opt/hostedtoolcache/CodeQL &> /dev/null + sudo rm -rf /host/usr/local/.ghcup &> /dev/null + sudo rm -rf /host/usr/local/share/powershell &> /dev/null + sudo rm -rf /host/usr/local/lib/node_modules &> /dev/null + sudo rm -rf /host/usr/local/julia* &> /dev/null + sudo rm -rf /host/usr/local/share/chromium &> /dev/null + sudo rm -rf /host/usr/local/share/vcpkg &> /dev/null + sudo rm -rf /host/usr/local/games &> /dev/null + sudo rm -rf /host/usr/local/sqlpackage &> /dev/null + sudo rm -rf /host/usr/lib/google-cloud-sdk &> /dev/null + sudo rm -rf /host/usr/lib/jvm &> /dev/null + sudo rm -rf /host/usr/lib/mono &> /dev/null + sudo rm -rf /host/usr/lib/R &> /dev/null + sudo rm -rf /host/usr/lib/postgresql &> /dev/null + sudo rm -rf /host/usr/lib/heroku &> /dev/null + sudo rm -rf /host/usr/lib/llvm* &> /dev/null + sudo rm -rf /host/usr/lib/firefox &> /dev/null + sudo rm -rf /host/opt/hostedtoolcache &> /dev/null df -h - uses: actions/checkout@v4 with: submodules: recursive - name: install run: ./bin/wally-tool-chain-install.sh - - name: setup - run: source setup.sh - name: make tests - run: make + run: | + source setup.sh + make - name: regresssion - run: regression-wally + run: | + source setup.sh + regression-wally From bb7888f59a28a4dc62cddd3be08a25388484cf0c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:25:55 -0700 Subject: [PATCH 092/232] Update test.yml --- .github/workflows/test.yml | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index ff414f151..8aa430252 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -73,12 +73,7 @@ jobs: - run: df -h - name: remove packages run: | - cd .github - ls - echo "Standard bash" - bash cli-space-cleanup.sh - echo "nsenter bash" - nsenter -t 1 -m -u -n -i /bin/bash cli-space-cleanup.sh #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From 482256cb842440fa733ff64e2f15579f08b20baa Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:42:02 -0700 Subject: [PATCH 093/232] New install action --- .github/cli-space-cleanup.sh | 69 ++++++++++++++++++++++++++++++--- .github/workflows/install.yml | 72 +++++------------------------------ .github/workflows/test.yml | 2 +- 3 files changed, 74 insertions(+), 69 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 8fd1cfdc8..5a85eb1d0 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -1,7 +1,66 @@ -removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) +#!/bin/bash +########################################### +## GitHub runner space cleanup +## +## Written: Jordan Carlin, jcarlin@hmc.edu +## Created: 30 June 2024 +## Modified: +## +## Purpose: Remove unnecessary packages/directories from GitHub Actions runner + +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Remove unnecessary packages +removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) for pack in "${removePacks[@]}"; do - echo "REMOVING ${pack}" - sudo apt-get purge -y $pack || true + sudo apt-get purge -y $pack &> /dev/null || true done -sudo apt-get autoremove -y -sudo apt-get clean +sudo apt-get autoremove -y &> /dev/null || true +sudo apt-get clean &> /dev/null || true + +# Remove unnecessary directories +sudo rm -rf /usr/local/lib/android &> /dev/null +sudo rm -rf /usr/share/dotnet &> /dev/null +sudo rm -rf /usr/share/swift &> /dev/null +sudo rm -rf /usr/share/miniconda &> /dev/null +sudo rm -rf /usr/share/az* &> /dev/null +sudo rm -rf /usr/share/gradle-* &> /dev/null +sudo rm -rf /usr/share/sbt &> /dev/null +sudo rm -rf /opt/ghc &> /dev/null +sudo rm -rf /usr/local/.ghcup &> /dev/null +sudo rm -rf /usr/local/share/powershell &> /dev/null +sudo rm -rf /usr/local/lib/node_modules &> /dev/null +sudo rm -rf /usr/local/julia* &> /dev/null +sudo rm -rf /usr/local/share/chromium &> /dev/null +sudo rm -rf /usr/local/share/vcpkg &> /dev/null +sudo rm -rf /usr/local/games &> /dev/null +sudo rm -rf /usr/local/sqlpackage &> /dev/null +sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null +sudo rm -rf /usr/lib/jvm &> /dev/null +sudo rm -rf /usr/lib/mono &> /dev/null +sudo rm -rf /usr/lib/R &> /dev/null +sudo rm -rf /usr/lib/postgresql &> /dev/null +sudo rm -rf /usr/lib/heroku &> /dev/null +sudo rm -rf /usr/lib/llvm* &> /dev/null +sudo rm -rf /usr/lib/firefox &> /dev/null +sudo rm -rf /opt/hostedtoolcache &> /dev/null + +# Clean up docker images +sudo docker image prune --all --force &> /dev/null diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 36453511f..221c39f9f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -14,51 +14,21 @@ jobs: - name: Free up storage run: | df -h - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) - for pack in "${removePacks[@]}"; do - sudo apt-get purge -y $pack &> /dev/null || true - done - sudo apt-get autoremove -y &> /dev/null - sudo apt-get clean &> /dev/null - - sudo rm -rf /usr/local/lib/android &> /dev/null - sudo rm -rf /usr/share/dotnet &> /dev/null - sudo rm -rf /usr/share/swift &> /dev/null - sudo rm -rf /usr/share/miniconda &> /dev/null - sudo rm -rf /usr/share/az* &> /dev/null - sudo rm -rf /usr/share/gradle-* &> /dev/null - sudo rm -rf /usr/share/sbt &> /dev/null - sudo rm -rf /opt/ghc &> /dev/null - sudo rm -rf /usr/local/.ghcup &> /dev/null - sudo rm -rf /usr/local/share/powershell &> /dev/null - sudo rm -rf /usr/local/lib/node_modules &> /dev/null - sudo rm -rf /usr/local/julia* &> /dev/null - sudo rm -rf /usr/local/share/chromium &> /dev/null - sudo rm -rf /usr/local/share/vcpkg &> /dev/null - sudo rm -rf /usr/local/games &> /dev/null - sudo rm -rf /usr/local/sqlpackage &> /dev/null - sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null - sudo rm -rf /usr/lib/jvm &> /dev/null - sudo rm -rf /usr/lib/mono &> /dev/null - sudo rm -rf /usr/lib/R &> /dev/null - sudo rm -rf /usr/lib/postgresql &> /dev/null - sudo rm -rf /usr/lib/heroku &> /dev/null - sudo rm -rf /usr/lib/llvm* &> /dev/null - sudo rm -rf /usr/lib/firefox &> /dev/null - sudo rm -rf /opt/hostedtoolcache &> /dev/null - sudo docker image prune --all --force &> /dev/null + ./github/cli-space-cleanup.sh df -h - uses: actions/checkout@v4 with: submodules: recursive - name: install run: sudo ./bin/wally-tool-chain-install.sh - - name: setup - run: source setup.sh - name: make tests - run: make + run: | + source setup.sh + make - name: regresssion - run: regression-wally + run: | + source setup.sh + regression-wally rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -72,34 +42,10 @@ jobs: os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - run: dnf install -y sudo git - - name: free up storage + - name: Free up storage run: | df -h - sudo rm -rf /host/usr/local/lib/android &> /dev/null - sudo rm -rf /host/usr/share/dotnet &> /dev/null - sudo rm -rf /host/usr/share/swift &> /dev/null - sudo rm -rf /host/usr/share/miniconda &> /dev/null - sudo rm -rf /host/usr/share/az* &> /dev/null - sudo rm -rf /host/usr/share/gradle-* &> /dev/null - sudo rm -rf /host/usr/share/sbt &> /dev/null - sudo rm -rf /host/opt/ghc &> /dev/null - sudo rm -rf /host/usr/local/.ghcup &> /dev/null - sudo rm -rf /host/usr/local/share/powershell &> /dev/null - sudo rm -rf /host/usr/local/lib/node_modules &> /dev/null - sudo rm -rf /host/usr/local/julia* &> /dev/null - sudo rm -rf /host/usr/local/share/chromium &> /dev/null - sudo rm -rf /host/usr/local/share/vcpkg &> /dev/null - sudo rm -rf /host/usr/local/games &> /dev/null - sudo rm -rf /host/usr/local/sqlpackage &> /dev/null - sudo rm -rf /host/usr/lib/google-cloud-sdk &> /dev/null - sudo rm -rf /host/usr/lib/jvm &> /dev/null - sudo rm -rf /host/usr/lib/mono &> /dev/null - sudo rm -rf /host/usr/lib/R &> /dev/null - sudo rm -rf /host/usr/lib/postgresql &> /dev/null - sudo rm -rf /host/usr/lib/heroku &> /dev/null - sudo rm -rf /host/usr/lib/llvm* &> /dev/null - sudo rm -rf /host/usr/lib/firefox &> /dev/null - sudo rm -rf /host/opt/hostedtoolcache &> /dev/null + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - uses: actions/checkout@v4 with: diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 8aa430252..a39d3b1e1 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -73,7 +73,7 @@ jobs: - run: df -h - name: remove packages run: | - nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" #-c "sudo apt-get purge -y google-cloud-cli || true; sudo apt-get autoremove -y; sudo apt-get clean" + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" - run: df -h - name: check packages run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr From 9df1a79f10a7892ca6581fe66a1eccb1e929005c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:46:51 -0700 Subject: [PATCH 094/232] Fix installation workflow curl-minimal dependency --- .github/workflows/install.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 221c39f9f..e67b3f28f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -41,7 +41,10 @@ jobs: matrix: os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - - run: dnf install -y sudo git + - name: Install dependencies + run: | + dnf install -y sudo git + dnf remove -y curl-minimal || true - name: Free up storage run: | df -h From de3bac0f59d7c81d80d373d2525780a1cea5f735 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 01:50:19 -0700 Subject: [PATCH 095/232] Update cli-space-saver --- .github/cli-space-cleanup.sh | 58 +++++++++++++++++------------------ .github/workflows/install.yml | 20 ++++++------ 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 5a85eb1d0..27fb300d8 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -30,37 +30,37 @@ # Remove unnecessary packages removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) for pack in "${removePacks[@]}"; do - sudo apt-get purge -y $pack &> /dev/null || true + sudo apt-get purge -y $pack || true done -sudo apt-get autoremove -y &> /dev/null || true -sudo apt-get clean &> /dev/null || true +sudo apt-get autoremove -y || true +sudo apt-get clean || true # Remove unnecessary directories -sudo rm -rf /usr/local/lib/android &> /dev/null -sudo rm -rf /usr/share/dotnet &> /dev/null -sudo rm -rf /usr/share/swift &> /dev/null -sudo rm -rf /usr/share/miniconda &> /dev/null -sudo rm -rf /usr/share/az* &> /dev/null -sudo rm -rf /usr/share/gradle-* &> /dev/null -sudo rm -rf /usr/share/sbt &> /dev/null -sudo rm -rf /opt/ghc &> /dev/null -sudo rm -rf /usr/local/.ghcup &> /dev/null -sudo rm -rf /usr/local/share/powershell &> /dev/null -sudo rm -rf /usr/local/lib/node_modules &> /dev/null -sudo rm -rf /usr/local/julia* &> /dev/null -sudo rm -rf /usr/local/share/chromium &> /dev/null -sudo rm -rf /usr/local/share/vcpkg &> /dev/null -sudo rm -rf /usr/local/games &> /dev/null -sudo rm -rf /usr/local/sqlpackage &> /dev/null -sudo rm -rf /usr/lib/google-cloud-sdk &> /dev/null -sudo rm -rf /usr/lib/jvm &> /dev/null -sudo rm -rf /usr/lib/mono &> /dev/null -sudo rm -rf /usr/lib/R &> /dev/null -sudo rm -rf /usr/lib/postgresql &> /dev/null -sudo rm -rf /usr/lib/heroku &> /dev/null -sudo rm -rf /usr/lib/llvm* &> /dev/null -sudo rm -rf /usr/lib/firefox &> /dev/null -sudo rm -rf /opt/hostedtoolcache &> /dev/null +sudo rm -rf /usr/local/lib/android +sudo rm -rf /usr/share/dotnet +sudo rm -rf /usr/share/swift +sudo rm -rf /usr/share/miniconda +sudo rm -rf /usr/share/az* +sudo rm -rf /usr/share/gradle-* +sudo rm -rf /usr/share/sbt +sudo rm -rf /opt/ghc +sudo rm -rf /usr/local/.ghcup +sudo rm -rf /usr/local/share/powershell +sudo rm -rf /usr/local/lib/node_modules +sudo rm -rf /usr/local/julia* +sudo rm -rf /usr/local/share/chromium +sudo rm -rf /usr/local/share/vcpkg +sudo rm -rf /usr/local/games +sudo rm -rf /usr/local/sqlpackage +sudo rm -rf /usr/lib/google-cloud-sdk +sudo rm -rf /usr/lib/jvm +sudo rm -rf /usr/lib/mono +sudo rm -rf /usr/lib/R +sudo rm -rf /usr/lib/postgresql +sudo rm -rf /usr/lib/heroku +sudo rm -rf /usr/lib/llvm* +sudo rm -rf /usr/lib/firefox +sudo rm -rf /opt/hostedtoolcache # Clean up docker images -sudo docker image prune --all --force &> /dev/null +sudo docker image prune --all --force diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e67b3f28f..0dd453b13 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -11,14 +11,14 @@ jobs: matrix: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - - name: Free up storage - run: | - df -h - ./github/cli-space-cleanup.sh - df -h - uses: actions/checkout@v4 with: submodules: recursive + - name: Free up storage + run: | + df -h + ./.github/cli-space-cleanup.sh + df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh - name: make tests @@ -35,7 +35,7 @@ jobs: runs-on: ubuntu-latest container: image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash strategy: fail-fast: false matrix: @@ -44,15 +44,15 @@ jobs: - name: Install dependencies run: | dnf install -y sudo git - dnf remove -y curl-minimal || true + dnf install curl -y --allowerasing || true + - uses: actions/checkout@v4 + with: + submodules: recursive - name: Free up storage run: | df -h nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - - uses: actions/checkout@v4 - with: - submodules: recursive - name: install run: ./bin/wally-tool-chain-install.sh - name: make tests From 51cb85045271a05d1aa44188cb3231e5bd89794f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 07:56:03 -0700 Subject: [PATCH 096/232] Update test.yml --- .github/workflows/test.yml | 131 +++++++++++++------------------------ 1 file changed, 46 insertions(+), 85 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a39d3b1e1..1343c6700 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -1,108 +1,69 @@ -name: List Storage Space +name: Test + on: [workflow_dispatch] - jobs: - clean-ubuntu: - name: clean ${{ matrix.os }} + ubuntu_install: + name: Test on ${{ matrix.os }} runs-on: ${{ matrix.os }} strategy: fail-fast: false matrix: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - - run: df -h - - name: remove packages + - uses: actions/checkout@v4 + with: + submodules: recursive + - name: Free up storage run: | - removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' 'powershell*' 'microsoft-edge-stable' 'mono-devel' ) - for pack in "${removePacks[@]}"; do - echo "REMOVING ${pack}" - sudo apt-get purge -y $pack || true - done - sudo apt-get autoremove -y - sudo apt-get clean - - run: df -h - - name: check packages - run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr - - name: remove dirs + df -h + ./.github/cli-space-cleanup.sh + df -h + - run: mkdir -p /opt/riscv + - run: sudo apt install -y python3 python3-pip python3-venv + - run: python3 -m venv /opt/riscv + - run: | + source /opt/riscv/bin/activate + pip install --upgrade pip + pip install -r requirements.txt + - name: make tests run: | - sudo rm -rf /usr/local/lib/android - sudo rm -rf /usr/share/dotnet - sudo rm -rf /usr/share/swift - sudo rm -rf /usr/share/miniconda - sudo rm -rf /usr/share/az* - sudo rm -rf /usr/share/gradle-* - sudo rm -rf /usr/share/sbt - sudo rm -rf /opt/ghc - sudo rm -rf /usr/local/.ghcup - sudo rm -rf /usr/local/share/powershell - sudo rm -rf /usr/local/lib/node_modules - sudo rm -rf /usr/local/julia* - sudo rm -rf /usr/local/share/chromium - sudo rm -rf /usr/local/share/vcpkg - sudo rm -rf /usr/local/games - sudo rm -rf /usr/local/sqlpackage - sudo rm -rf /usr/lib/google-cloud-sdk - sudo rm -rf /usr/lib/jvm - sudo rm -rf /usr/lib/mono - sudo rm -rf /usr/lib/R - sudo rm -rf /usr/lib/postgresql - sudo rm -rf /usr/lib/heroku - sudo rm -rf /usr/lib/llvm* - sudo rm -rf /usr/lib/firefox - sudo rm -rf /opt/hostedtoolcache - sudo docker image prune --all --force - - run: df -h + source setup.sh + source /opt/riscv/bin/activate + make || true - clean-rhel: - name: clean ${{ matrix.os }} + + rhel_family_install: + name: Test on ${{ matrix.os }} runs-on: ubuntu-latest - defaults: - run: - shell: bash container: image: ${{ matrix.os }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash strategy: fail-fast: false matrix: - os: ["rockylinux:8", "almalinux:8", "rockylinux:9", "almalinux:9"] + os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: - - run: dnf install -y sudo git + - name: Install dependencies + run: | + dnf install -y sudo git + dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - - run: df -h - - name: remove packages + with: + submodules: recursive + - run: dnf install -y python3.12 python3-pip + - run: mkdir -p /opt/riscv + - run: python3.12 -m venv /opt/riscv + - run: | + source /opt/riscv/bin/activate + pip install --upgrade pip + pip install -r requirements.txt + - name: make tests run: | - nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" - - run: df -h - - name: check packages - run: dpkg-query -Wf '${Installed-Size}\t${Package}\n' | sort -nr - - name: remove dirs + source setup.sh + source /opt/riscv/bin/activate + make || true + - name: regresssion run: | - sudo rm -rf host/usr/local/lib/android - sudo rm -rf host/usr/share/dotnet - sudo rm -rf host/usr/share/swift - sudo rm -rf host/usr/share/miniconda - sudo rm -rf host/usr/share/az* - sudo rm -rf host/usr/share/gradle-* - sudo rm -rf host/usr/share/sbt - sudo rm -rf host/opt/ghc - sudo rm -rf host/usr/local/.ghcup - sudo rm -rf host/usr/local/share/powershell - sudo rm -rf host/usr/local/lib/node_modules - sudo rm -rf host/usr/local/julia* - sudo rm -rf host/usr/local/share/chromium - sudo rm -rf host/usr/local/share/vcpkg - sudo rm -rf host/usr/local/games - sudo rm -rf host/usr/local/sqlpackage - sudo rm -rf host/usr/lib/google-cloud-sdk - sudo rm -rf host/usr/lib/jvm - sudo rm -rf host/usr/lib/mono - sudo rm -rf host/usr/lib/R - sudo rm -rf host/usr/lib/postgresql - sudo rm -rf host/usr/lib/heroku - sudo rm -rf host/usr/lib/llvm* - sudo rm -rf host/usr/lib/firefox - sudo rm -rf host/opt/hostedtoolcache - sudo docker image prune --all --force - - run: df -h + source setup.sh + regression-wally From 690326d6acedf2a413f030b9d7c43676fc3ec527 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 17 Jul 2024 21:34:55 -0700 Subject: [PATCH 097/232] Update shell --- .github/cli-space-cleanup.sh | 3 +- .github/workflows/install.yml | 4 ++- .github/workflows/test.yml | 64 +++++------------------------------ 3 files changed, 13 insertions(+), 58 deletions(-) diff --git a/.github/cli-space-cleanup.sh b/.github/cli-space-cleanup.sh index 27fb300d8..0f8de1619 100755 --- a/.github/cli-space-cleanup.sh +++ b/.github/cli-space-cleanup.sh @@ -30,7 +30,7 @@ # Remove unnecessary packages removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' ) for pack in "${removePacks[@]}"; do - sudo apt-get purge -y $pack || true + sudo apt-get purge -y "$pack" || true done sudo apt-get autoremove -y || true sudo apt-get clean || true @@ -58,7 +58,6 @@ sudo rm -rf /usr/lib/mono sudo rm -rf /usr/lib/R sudo rm -rf /usr/lib/postgresql sudo rm -rf /usr/lib/heroku -sudo rm -rf /usr/lib/llvm* sudo rm -rf /usr/lib/firefox sudo rm -rf /opt/hostedtoolcache diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0dd453b13..ec7a0cf34 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,6 +1,8 @@ name: Installation - on: [workflow_dispatch] +defaults: + run: + shell: bash jobs: ubuntu_install: diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 1343c6700..18f9cb34c 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -1,6 +1,8 @@ name: Test - on: [workflow_dispatch] +defaults: + run: + shell: bash jobs: ubuntu_install: @@ -12,58 +14,10 @@ jobs: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - uses: actions/checkout@v4 - with: - submodules: recursive - - name: Free up storage - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - run: mkdir -p /opt/riscv - - run: sudo apt install -y python3 python3-pip python3-venv - - run: python3 -m venv /opt/riscv + # with: + # submodules: recursive - run: | - source /opt/riscv/bin/activate - pip install --upgrade pip - pip install -r requirements.txt - - name: make tests - run: | - source setup.sh - source /opt/riscv/bin/activate - make || true - - - rhel_family_install: - name: Test on ${{ matrix.os }} - runs-on: ubuntu-latest - container: - image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash - strategy: - fail-fast: false - matrix: - os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] - steps: - - name: Install dependencies - run: | - dnf install -y sudo git - dnf install curl -y --allowerasing || true - - uses: actions/checkout@v4 - with: - submodules: recursive - - run: dnf install -y python3.12 python3-pip - - run: mkdir -p /opt/riscv - - run: python3.12 -m venv /opt/riscv - - run: | - source /opt/riscv/bin/activate - pip install --upgrade pip - pip install -r requirements.txt - - name: make tests - run: | - source setup.sh - source /opt/riscv/bin/activate - make || true - - name: regresssion - run: | - source setup.sh - regression-wally + df -h + ./.github/cli-space-cleanup.sh + df -h + - run: sudo ./bin/wally-package-install.sh From 60cc2be07fa2b91bd42b3248e1cba93b9ed66814 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 18 Jul 2024 23:36:11 -0700 Subject: [PATCH 098/232] Remove test.yml --- .github/workflows/test.yml | 23 ----------------------- 1 file changed, 23 deletions(-) delete mode 100644 .github/workflows/test.yml diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml deleted file mode 100644 index 18f9cb34c..000000000 --- a/.github/workflows/test.yml +++ /dev/null @@ -1,23 +0,0 @@ -name: Test -on: [workflow_dispatch] -defaults: - run: - shell: bash - -jobs: - ubuntu_install: - name: Test on ${{ matrix.os }} - runs-on: ${{ matrix.os }} - strategy: - fail-fast: false - matrix: - os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] - steps: - - uses: actions/checkout@v4 - # with: - # submodules: recursive - - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - run: sudo ./bin/wally-package-install.sh From 306e5d4042e9d6a2cbb59c38b092c74d78dbd648 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 19:00:14 -0700 Subject: [PATCH 099/232] Add clean + update checks --- .github/workflows/install.yml | 4 ++-- bin/wally-tool-chain-install.sh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index ec7a0cf34..52cb45f95 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -22,7 +22,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: make tests run: | source setup.sh @@ -56,7 +56,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: ./bin/wally-tool-chain-install.sh + run: ./bin/wally-tool-chain-install.sh --clean - name: make tests run: | source setup.sh diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..1905d484c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -72,7 +72,7 @@ logger() { cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true) } -set -e # break on error +set -ex # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages From 56c39e764c5bbce17d49ed1fceb1be2e75a7190c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 19:39:21 -0700 Subject: [PATCH 100/232] updates --- bin/wally-tool-chain-install.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 1905d484c..ad83f3f8f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -46,6 +46,7 @@ ENDC='\033[0m' # Reset to default color ## Helper functions # Error handler error() { + set +x echo -e "${FAIL_COLOR}Error: $STATUS installation failed" echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information." From 2cb5189db817569243274d4ff2cdf22da75fa45e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 20:47:58 -0700 Subject: [PATCH 101/232] no buildroot --- bin/regression-wally | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 16286c60b..a591aaf61 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -421,8 +421,8 @@ elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_fp, coveragesim) else: for sim in sims: - if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one - addTests(tests_buildrootshort, sim) + # if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one + # addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) From 60c92e99c763ceb75d8416dacefef2bbeaac7ff7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 22:50:43 -0700 Subject: [PATCH 102/232] Make all git directories safe in installation action --- .github/workflows/install.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 52cb45f95..4b207b9ad 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -50,6 +50,8 @@ jobs: - uses: actions/checkout@v4 with: submodules: recursive + - name: Fix git ownership + run: git config --global --add safe.directory '*' - name: Free up storage run: | df -h From 535ca9535bee4c2d6bdb643230c6bef38fdfb61a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 14:54:21 -0700 Subject: [PATCH 103/232] Manually run wsim --- .github/workflows/install.yml | 74 ++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4b207b9ad..2543d86f9 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -66,4 +66,76 @@ jobs: - name: regresssion run: | source setup.sh - regression-wally + lint-wally + wsim --sim verilator rv32e arch32e + wsim --sim verilator rv32i arch32i + wsim --sim verilator rv32imc arch32i + wsim --sim verilator rv32imc arch32c + wsim --sim verilator rv32imc arch32m + wsim --sim verilator rv32imc wally32periph + wsim --sim verilator rv32gc arch32f + wsim --sim verilator rv32gc arch32d + wsim --sim verilator rv32gc arch32f_fma + wsim --sim verilator rv32gc arch32d_fma + wsim --sim verilator rv32gc arch32f_divsqrt + wsim --sim verilator rv32gc arch32d_divsqrt + wsim --sim verilator rv32gc arch32i + wsim --sim verilator rv32gc arch32priv + wsim --sim verilator rv32gc arch32c + wsim --sim verilator rv32gc arch32m + wsim --sim verilator rv32gc arch32a_amo + wsim --sim verilator rv32gc arch32zifencei + wsim --sim verilator rv32gc arch32zicond + wsim --sim verilator rv32gc arch32zba + wsim --sim verilator rv32gc arch32zbb + wsim --sim verilator rv32gc arch32zbc + wsim --sim verilator rv32gc arch32zbs + wsim --sim verilator rv32gc arch32zfh + wsim --sim verilator rv32gc arch32zfh_fma + wsim --sim verilator rv32gc arch32zfh_divsqrt + wsim --sim verilator rv32gc arch32zfaf + wsim --sim verilator rv32gc arch32zfad + wsim --sim verilator rv32gc wally32a_lrsc + wsim --sim verilator rv32gc wally32priv + wsim --sim verilator rv32gc wally32periph + wsim --sim verilator rv32gc arch32zcb + wsim --sim verilator rv32gc arch32zbkb + wsim --sim verilator rv32gc arch32zbkc + wsim --sim verilator rv32gc arch32zbkx + wsim --sim verilator rv32gc arch32zknd + wsim --sim verilator rv32gc arch32zkne + wsim --sim verilator rv32gc arch32zknh + wsim --sim verilator rv64i arch64i + wsim --sim verilator rv64gc coverage64gc + wsim --sim verilator rv64gc arch64i + wsim --sim verilator rv64gc arch64priv + wsim --sim verilator rv64gc arch64c + wsim --sim verilator rv64gc arch64m + wsim --sim verilator rv64gc arch64zcb + wsim --sim verilator rv64gc arch64zifencei + wsim --sim verilator rv64gc arch64zicond + wsim --sim verilator rv64gc arch64a_amo + wsim --sim verilator rv64gc wally64a_lrsc + wsim --sim verilator rv64gc wally64periph + wsim --sim verilator rv64gc wally64priv + wsim --sim verilator rv64gc arch64zbkb + wsim --sim verilator rv64gc arch64zbkc + wsim --sim verilator rv64gc arch64zbkx + wsim --sim verilator rv64gc arch64zknd + wsim --sim verilator rv64gc arch64zkne + wsim --sim verilator rv64gc arch64zknh + wsim --sim verilator rv64gc arch64zba + wsim --sim verilator rv64gc arch64zbb + wsim --sim verilator rv64gc arch64zbc + wsim --sim verilator rv64gc arch64zbs + wsim --sim verilator rv64gc arch64f + wsim --sim verilator rv64gc arch64d + wsim --sim verilator rv64gc arch64zfh + wsim --sim verilator rv64gc arch64f_fma + wsim --sim verilator rv64gc arch64d_fma + wsim --sim verilator rv64gc arch64zfh_fma + wsim --sim verilator rv64gc arch64f_divsqrt + wsim --sim verilator rv64gc arch64d_divsqrt + wsim --sim verilator rv64gc arch64zfh_divsqrt + wsim --sim verilator rv64gc arch64zfaf + wsim --sim verilator rv64gc arch64zfad From 9b2aa1ae5f9f35bb94eeb4619d6f32059b28b653 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 11:52:37 -0700 Subject: [PATCH 104/232] Only build riscof tests in installation ci --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 2543d86f9..f5854ed72 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -26,7 +26,7 @@ jobs: - name: make tests run: | source setup.sh - make + make riscof - name: regresssion run: | source setup.sh @@ -62,7 +62,7 @@ jobs: - name: make tests run: | source setup.sh - make + make riscof - name: regresssion run: | source setup.sh From dfd27de6963b12c788274ac6e7b8a8de5e296949 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 18:01:39 -0700 Subject: [PATCH 105/232] Update install.yml --- .github/workflows/install.yml | 74 ++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index f5854ed72..cb7ac9002 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,7 +30,79 @@ jobs: - name: regresssion run: | source setup.sh - regression-wally + lint-wally + wsim --sim verilator rv32e arch32e + wsim --sim verilator rv32i arch32i + wsim --sim verilator rv32imc arch32i + wsim --sim verilator rv32imc arch32c + wsim --sim verilator rv32imc arch32m + wsim --sim verilator rv32imc wally32periph + wsim --sim verilator rv32gc arch32f + wsim --sim verilator rv32gc arch32d + wsim --sim verilator rv32gc arch32f_fma + wsim --sim verilator rv32gc arch32d_fma + wsim --sim verilator rv32gc arch32f_divsqrt + wsim --sim verilator rv32gc arch32d_divsqrt + wsim --sim verilator rv32gc arch32i + wsim --sim verilator rv32gc arch32priv + wsim --sim verilator rv32gc arch32c + wsim --sim verilator rv32gc arch32m + wsim --sim verilator rv32gc arch32a_amo + wsim --sim verilator rv32gc arch32zifencei + wsim --sim verilator rv32gc arch32zicond + wsim --sim verilator rv32gc arch32zba + wsim --sim verilator rv32gc arch32zbb + wsim --sim verilator rv32gc arch32zbc + wsim --sim verilator rv32gc arch32zbs + wsim --sim verilator rv32gc arch32zfh + wsim --sim verilator rv32gc arch32zfh_fma + wsim --sim verilator rv32gc arch32zfh_divsqrt + wsim --sim verilator rv32gc arch32zfaf + wsim --sim verilator rv32gc arch32zfad + wsim --sim verilator rv32gc wally32a_lrsc + wsim --sim verilator rv32gc wally32priv + wsim --sim verilator rv32gc wally32periph + wsim --sim verilator rv32gc arch32zcb + wsim --sim verilator rv32gc arch32zbkb + wsim --sim verilator rv32gc arch32zbkc + wsim --sim verilator rv32gc arch32zbkx + wsim --sim verilator rv32gc arch32zknd + wsim --sim verilator rv32gc arch32zkne + wsim --sim verilator rv32gc arch32zknh + wsim --sim verilator rv64i arch64i + wsim --sim verilator rv64gc coverage64gc + wsim --sim verilator rv64gc arch64i + wsim --sim verilator rv64gc arch64priv + wsim --sim verilator rv64gc arch64c + wsim --sim verilator rv64gc arch64m + wsim --sim verilator rv64gc arch64zcb + wsim --sim verilator rv64gc arch64zifencei + wsim --sim verilator rv64gc arch64zicond + wsim --sim verilator rv64gc arch64a_amo + wsim --sim verilator rv64gc wally64a_lrsc + wsim --sim verilator rv64gc wally64periph + wsim --sim verilator rv64gc wally64priv + wsim --sim verilator rv64gc arch64zbkb + wsim --sim verilator rv64gc arch64zbkc + wsim --sim verilator rv64gc arch64zbkx + wsim --sim verilator rv64gc arch64zknd + wsim --sim verilator rv64gc arch64zkne + wsim --sim verilator rv64gc arch64zknh + wsim --sim verilator rv64gc arch64zba + wsim --sim verilator rv64gc arch64zbb + wsim --sim verilator rv64gc arch64zbc + wsim --sim verilator rv64gc arch64zbs + wsim --sim verilator rv64gc arch64f + wsim --sim verilator rv64gc arch64d + wsim --sim verilator rv64gc arch64zfh + wsim --sim verilator rv64gc arch64f_fma + wsim --sim verilator rv64gc arch64d_fma + wsim --sim verilator rv64gc arch64zfh_fma + wsim --sim verilator rv64gc arch64f_divsqrt + wsim --sim verilator rv64gc arch64d_divsqrt + wsim --sim verilator rv64gc arch64zfh_divsqrt + wsim --sim verilator rv64gc arch64zfaf + wsim --sim verilator rv64gc arch64zfad rhel_family_install: name: Test installation on ${{ matrix.os }} From a9d2fbdedd34a6a35b123df2053c2a0ff46c4a56 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 23:16:35 -0700 Subject: [PATCH 106/232] Use regression-wally in install cli --- .github/workflows/install.yml | 150 +--------------------------------- 1 file changed, 3 insertions(+), 147 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index cb7ac9002..7b07c5636 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,79 +30,7 @@ jobs: - name: regresssion run: | source setup.sh - lint-wally - wsim --sim verilator rv32e arch32e - wsim --sim verilator rv32i arch32i - wsim --sim verilator rv32imc arch32i - wsim --sim verilator rv32imc arch32c - wsim --sim verilator rv32imc arch32m - wsim --sim verilator rv32imc wally32periph - wsim --sim verilator rv32gc arch32f - wsim --sim verilator rv32gc arch32d - wsim --sim verilator rv32gc arch32f_fma - wsim --sim verilator rv32gc arch32d_fma - wsim --sim verilator rv32gc arch32f_divsqrt - wsim --sim verilator rv32gc arch32d_divsqrt - wsim --sim verilator rv32gc arch32i - wsim --sim verilator rv32gc arch32priv - wsim --sim verilator rv32gc arch32c - wsim --sim verilator rv32gc arch32m - wsim --sim verilator rv32gc arch32a_amo - wsim --sim verilator rv32gc arch32zifencei - wsim --sim verilator rv32gc arch32zicond - wsim --sim verilator rv32gc arch32zba - wsim --sim verilator rv32gc arch32zbb - wsim --sim verilator rv32gc arch32zbc - wsim --sim verilator rv32gc arch32zbs - wsim --sim verilator rv32gc arch32zfh - wsim --sim verilator rv32gc arch32zfh_fma - wsim --sim verilator rv32gc arch32zfh_divsqrt - wsim --sim verilator rv32gc arch32zfaf - wsim --sim verilator rv32gc arch32zfad - wsim --sim verilator rv32gc wally32a_lrsc - wsim --sim verilator rv32gc wally32priv - wsim --sim verilator rv32gc wally32periph - wsim --sim verilator rv32gc arch32zcb - wsim --sim verilator rv32gc arch32zbkb - wsim --sim verilator rv32gc arch32zbkc - wsim --sim verilator rv32gc arch32zbkx - wsim --sim verilator rv32gc arch32zknd - wsim --sim verilator rv32gc arch32zkne - wsim --sim verilator rv32gc arch32zknh - wsim --sim verilator rv64i arch64i - wsim --sim verilator rv64gc coverage64gc - wsim --sim verilator rv64gc arch64i - wsim --sim verilator rv64gc arch64priv - wsim --sim verilator rv64gc arch64c - wsim --sim verilator rv64gc arch64m - wsim --sim verilator rv64gc arch64zcb - wsim --sim verilator rv64gc arch64zifencei - wsim --sim verilator rv64gc arch64zicond - wsim --sim verilator rv64gc arch64a_amo - wsim --sim verilator rv64gc wally64a_lrsc - wsim --sim verilator rv64gc wally64periph - wsim --sim verilator rv64gc wally64priv - wsim --sim verilator rv64gc arch64zbkb - wsim --sim verilator rv64gc arch64zbkc - wsim --sim verilator rv64gc arch64zbkx - wsim --sim verilator rv64gc arch64zknd - wsim --sim verilator rv64gc arch64zkne - wsim --sim verilator rv64gc arch64zknh - wsim --sim verilator rv64gc arch64zba - wsim --sim verilator rv64gc arch64zbb - wsim --sim verilator rv64gc arch64zbc - wsim --sim verilator rv64gc arch64zbs - wsim --sim verilator rv64gc arch64f - wsim --sim verilator rv64gc arch64d - wsim --sim verilator rv64gc arch64zfh - wsim --sim verilator rv64gc arch64f_fma - wsim --sim verilator rv64gc arch64d_fma - wsim --sim verilator rv64gc arch64zfh_fma - wsim --sim verilator rv64gc arch64f_divsqrt - wsim --sim verilator rv64gc arch64d_divsqrt - wsim --sim verilator rv64gc arch64zfh_divsqrt - wsim --sim verilator rv64gc arch64zfaf - wsim --sim verilator rv64gc arch64zfad + regression-wally rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -135,79 +63,7 @@ jobs: run: | source setup.sh make riscof - - name: regresssion + - name: regression run: | source setup.sh - lint-wally - wsim --sim verilator rv32e arch32e - wsim --sim verilator rv32i arch32i - wsim --sim verilator rv32imc arch32i - wsim --sim verilator rv32imc arch32c - wsim --sim verilator rv32imc arch32m - wsim --sim verilator rv32imc wally32periph - wsim --sim verilator rv32gc arch32f - wsim --sim verilator rv32gc arch32d - wsim --sim verilator rv32gc arch32f_fma - wsim --sim verilator rv32gc arch32d_fma - wsim --sim verilator rv32gc arch32f_divsqrt - wsim --sim verilator rv32gc arch32d_divsqrt - wsim --sim verilator rv32gc arch32i - wsim --sim verilator rv32gc arch32priv - wsim --sim verilator rv32gc arch32c - wsim --sim verilator rv32gc arch32m - wsim --sim verilator rv32gc arch32a_amo - wsim --sim verilator rv32gc arch32zifencei - wsim --sim verilator rv32gc arch32zicond - wsim --sim verilator rv32gc arch32zba - wsim --sim verilator rv32gc arch32zbb - wsim --sim verilator rv32gc arch32zbc - wsim --sim verilator rv32gc arch32zbs - wsim --sim verilator rv32gc arch32zfh - wsim --sim verilator rv32gc arch32zfh_fma - wsim --sim verilator rv32gc arch32zfh_divsqrt - wsim --sim verilator rv32gc arch32zfaf - wsim --sim verilator rv32gc arch32zfad - wsim --sim verilator rv32gc wally32a_lrsc - wsim --sim verilator rv32gc wally32priv - wsim --sim verilator rv32gc wally32periph - wsim --sim verilator rv32gc arch32zcb - wsim --sim verilator rv32gc arch32zbkb - wsim --sim verilator rv32gc arch32zbkc - wsim --sim verilator rv32gc arch32zbkx - wsim --sim verilator rv32gc arch32zknd - wsim --sim verilator rv32gc arch32zkne - wsim --sim verilator rv32gc arch32zknh - wsim --sim verilator rv64i arch64i - wsim --sim verilator rv64gc coverage64gc - wsim --sim verilator rv64gc arch64i - wsim --sim verilator rv64gc arch64priv - wsim --sim verilator rv64gc arch64c - wsim --sim verilator rv64gc arch64m - wsim --sim verilator rv64gc arch64zcb - wsim --sim verilator rv64gc arch64zifencei - wsim --sim verilator rv64gc arch64zicond - wsim --sim verilator rv64gc arch64a_amo - wsim --sim verilator rv64gc wally64a_lrsc - wsim --sim verilator rv64gc wally64periph - wsim --sim verilator rv64gc wally64priv - wsim --sim verilator rv64gc arch64zbkb - wsim --sim verilator rv64gc arch64zbkc - wsim --sim verilator rv64gc arch64zbkx - wsim --sim verilator rv64gc arch64zknd - wsim --sim verilator rv64gc arch64zkne - wsim --sim verilator rv64gc arch64zknh - wsim --sim verilator rv64gc arch64zba - wsim --sim verilator rv64gc arch64zbb - wsim --sim verilator rv64gc arch64zbc - wsim --sim verilator rv64gc arch64zbs - wsim --sim verilator rv64gc arch64f - wsim --sim verilator rv64gc arch64d - wsim --sim verilator rv64gc arch64zfh - wsim --sim verilator rv64gc arch64f_fma - wsim --sim verilator rv64gc arch64d_fma - wsim --sim verilator rv64gc arch64zfh_fma - wsim --sim verilator rv64gc arch64f_divsqrt - wsim --sim verilator rv64gc arch64d_divsqrt - wsim --sim verilator rv64gc arch64zfh_divsqrt - wsim --sim verilator rv64gc arch64zfaf - wsim --sim verilator rv64gc arch64zfad + regression-wally From d613a1b2f9ede52c456bcd7cf14470e25773f0d3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 21 Jul 2024 11:16:08 -0700 Subject: [PATCH 107/232] Upload logs --- .github/workflows/install.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 7b07c5636..8d6abfd2f 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -31,6 +31,11 @@ jobs: run: | source setup.sh regression-wally + - uses: actions/upload-artifact@v2 + if: always() + with: + name: regression-logs-${{ matrix.os }} + path: ${{ github.workspace }}/sim/verilator/logs/ rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -67,3 +72,8 @@ jobs: run: | source setup.sh regression-wally + - uses: actions/upload-artifact@v2 + if: always() + with: + name: regression-logs-${{ matrix.os }} + path: ${{ github.workspace }}/sim/verilator/logs/ From 864fb199f0bea8dcc55dbee256e21f796e55efc0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 21 Jul 2024 14:16:12 -0700 Subject: [PATCH 108/232] Update artifact upload --- .github/workflows/install.yml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 8d6abfd2f..b422ae762 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,5 +1,5 @@ name: Installation -on: [workflow_dispatch] +on: [workflow_dispatch, push] defaults: run: shell: bash @@ -31,7 +31,7 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 if: always() with: name: regression-logs-${{ matrix.os }} @@ -48,6 +48,11 @@ jobs: matrix: os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] steps: + - name: Unique name for Artifacts + id: prep_artifact_name + run: | + name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') + echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - name: Install dependencies run: | dnf install -y sudo git @@ -72,8 +77,8 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v2 + - uses: actions/upload-artifact@v4 if: always() with: - name: regression-logs-${{ matrix.os }} + name: regression-logs-${{ env.ARTIFACT_NAME }} path: ${{ github.workspace }}/sim/verilator/logs/ From 269399946c639165190aea082c4f9d1b83cf1bd5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 00:19:20 -0700 Subject: [PATCH 109/232] Save installation logs --- .github/workflows/install.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b422ae762..158113b25 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -36,6 +36,11 @@ jobs: with: name: regression-logs-${{ matrix.os }} path: ${{ github.workspace }}/sim/verilator/logs/ + - uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ matrix.os }} + path: /opt/riscv/logs/ rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -82,3 +87,8 @@ jobs: with: name: regression-logs-${{ env.ARTIFACT_NAME }} path: ${{ github.workspace }}/sim/verilator/logs/ + - uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ env.ARTIFACT_NAME }} + path: /opt/riscv/logs/ From 63b387619d5dd47184320b19d10e116777a4b441 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 02:00:27 -0700 Subject: [PATCH 110/232] Add buildroot to installation test --- .github/workflows/install.yml | 6 +++++- bin/regression-wally | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 158113b25..6b989b7ad 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -27,7 +27,11 @@ jobs: run: | source setup.sh make riscof - - name: regresssion + - name: make buildroot + run: | + source setup.sh + make -C linux + - name: regression run: | source setup.sh regression-wally diff --git a/bin/regression-wally b/bin/regression-wally index a591aaf61..16286c60b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -421,8 +421,8 @@ elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_fp, coveragesim) else: for sim in sims: - # if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one - # addTests(tests_buildrootshort, sim) + if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one + addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) From 84ee1f0b179898a4c9726faf8aa9769a17aaae19 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 15:57:30 -0700 Subject: [PATCH 111/232] Rhel buildroot --- .github/workflows/install.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 6b989b7ad..e97be456e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -82,6 +82,10 @@ jobs: run: | source setup.sh make riscof + - name: make buildroot + run: | + source setup.sh + make -C linux - name: regression run: | source setup.sh From f115ee9e722ef07529f7525e5e4a6c333d46768f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 23:35:11 -0700 Subject: [PATCH 112/232] Run make linux with sudo in installation test --- .github/workflows/install.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e97be456e..56b80f757 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,7 +30,7 @@ jobs: - name: make buildroot run: | source setup.sh - make -C linux + sudo make -C linux - name: regression run: | source setup.sh @@ -77,7 +77,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: ./bin/wally-tool-chain-install.sh --clean + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: make tests run: | source setup.sh @@ -85,7 +85,7 @@ jobs: - name: make buildroot run: | source setup.sh - make -C linux + sudo make -C linux - name: regression run: | source setup.sh From 50fc27cb454dc1a95f23eecf359f50eef2d66ada Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 12:36:33 -0700 Subject: [PATCH 113/232] Log buildroot test --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 56b80f757..c66187ff2 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -30,7 +30,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux + sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh @@ -85,7 +85,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux + sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From a4c585ca56c31bee48ac1a0879f7fa081fe8e288 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 19:51:31 -0700 Subject: [PATCH 114/232] Change number of riscof jobs in installation test action; restore default to 4 --- .github/workflows/install.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index c66187ff2..b63c57211 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -26,6 +26,7 @@ jobs: - name: make tests run: | source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: make buildroot run: | @@ -81,6 +82,7 @@ jobs: - name: make tests run: | source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: make buildroot run: | From f47fbdcb05b1eaf0c077a9d195e577f0ead532bc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 25 Jul 2024 22:41:13 -0700 Subject: [PATCH 115/232] Update install test to preserve variables for buildroot build --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b63c57211..03ed7a82c 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -31,7 +31,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh @@ -87,7 +87,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From 04ddfa0bd07b05e81773dcf00a98f6df974f0345 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 11:47:08 -0700 Subject: [PATCH 116/232] Update install test with buildroot changes --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 03ed7a82c..0788e9883 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -31,7 +31,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh @@ -87,7 +87,7 @@ jobs: - name: make buildroot run: | source setup.sh - sudo -E make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log + make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From 32522fcf3d0cc618885127b58e0b0b49893b5f03 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 12:42:15 -0700 Subject: [PATCH 117/232] Switch test install to use buildroot from install script --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0788e9883..4e7cfdc9e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -23,15 +23,15 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean + - name: check buildroot + run: | + source setup.sh + ls $RISCV/linux-testvectors - name: make tests run: | source setup.sh sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - - name: make buildroot - run: | - source setup.sh - make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From d528eddab5a6fb51d3a9a7928fc7d1c90e7eacc3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 15:21:43 -0700 Subject: [PATCH 118/232] Switch rhel installation test to use install script buildroot --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 4e7cfdc9e..b300044f8 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -79,15 +79,15 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean + - name: check buildroot + run: | + source setup.sh + ls $RISCV/linux-testvectors - name: make tests run: | source setup.sh sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - - name: make buildroot - run: | - source setup.sh - make -C linux 2>&1 | tee -a $RISCV/logs/buildroot.log - name: regression run: | source setup.sh From 62157df494b905f212fef660e930fae6e3af42fc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 17:26:24 -0700 Subject: [PATCH 119/232] Turn off debugging messages --- bin/wally-tool-chain-install.sh | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index ad83f3f8f..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -46,7 +46,6 @@ ENDC='\033[0m' # Reset to default color ## Helper functions # Error handler error() { - set +x echo -e "${FAIL_COLOR}Error: $STATUS installation failed" echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information." @@ -73,7 +72,7 @@ logger() { cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true) } -set -ex # break on error +set -e # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages From 5f9e34788a14bd3654e7ec2822f9d69e93046a8d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 7 Aug 2024 22:02:33 -0700 Subject: [PATCH 120/232] Update installation test logging --- .github/workflows/install.yml | 106 +++++++++++++++++++++++++++++----- 1 file changed, 90 insertions(+), 16 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b300044f8..74a9f58b1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -23,10 +23,12 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: check buildroot - run: | - source setup.sh - ls $RISCV/linux-testvectors + - name: Upload installation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ matrix.os }} + path: /opt/riscv/logs/ - name: make tests run: | source setup.sh @@ -36,16 +38,12 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v4 + - name: Upload regression logs + uses: actions/upload-artifact@v4 if: always() with: name: regression-logs-${{ matrix.os }} path: ${{ github.workspace }}/sim/verilator/logs/ - - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-${{ matrix.os }} - path: /opt/riscv/logs/ rhel_family_install: name: Test installation on ${{ matrix.os }} @@ -79,10 +77,12 @@ jobs: df -h - name: install run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: check buildroot - run: | - source setup.sh - ls $RISCV/linux-testvectors + - name: Upload installation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-${{ env.ARTIFACT_NAME }} + path: /opt/riscv/logs/ - name: make tests run: | source setup.sh @@ -92,12 +92,86 @@ jobs: run: | source setup.sh regression-wally - - uses: actions/upload-artifact@v4 + - name: Upload regression logs + uses: actions/upload-artifact@v4 if: always() with: name: regression-logs-${{ env.ARTIFACT_NAME }} path: ${{ github.workspace }}/sim/verilator/logs/ - - uses: actions/upload-artifact@v4 + + + user_install: + name: Test installation with user permissions + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + submodules: recursive + - name: Free up storage + run: | + df -h + ./.github/cli-space-cleanup.sh + df -h + - name: install packages with sudo + run: sudo ./bin/wally-package-install.sh + - name: install + run: ./bin/wally-tool-chain-install.sh --clean + - name: Upload installation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-user-install + path: ~/riscv/logs/ + - name: make tests + run: | + source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini + make riscof + - name: regression + run: | + source setup.sh + regression-wally + - name: Upload regression logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: regression-logs-user-install + path: ${{ github.workspace }}/sim/verilator/logs/ + + + custom_location_install: + name: Test installation with custom location + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + submodules: recursive + - name: Free up storage + run: | + df -h + ./.github/cli-space-cleanup.sh + df -h + - name: install + run: sudo ./bin/wally-tool-chain-install.sh --clean /home/riscv + - name: Upload instalation logs + uses: actions/upload-artifact@v4 + if: always() + with: + name: installation-logs-custom-location-install + path: /home/riscv/logs/ + - name: Update setup.sh with new $RISCV location + run: sed -i 's,/opt/riscv,/home/riscv,g' setup.sh + - name: make tests + run: | + source setup.sh + sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini + make riscof + - name: regression + run: | + source setup.sh + regression-wally + - name: Upload regression logs + uses: actions/upload-artifact@v4 if: always() with: name: installation-logs-${{ env.ARTIFACT_NAME }} From 521633698ca8a967e2fdf76b13a1d6c295effb5f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 7 Aug 2024 22:11:40 -0700 Subject: [PATCH 121/232] Add non-sudo and custom location installation tests --- .github/workflows/install.yml | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 74a9f58b1..a653fac5c 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -140,9 +140,18 @@ jobs: custom_location_install: - name: Test installation with custom location + name: Test installation with custom location ${{ matrix.path }} runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + path: ["/home/riscv"] steps: + - name: Unique name for Artifacts + id: prep_artifact_name + run: | + name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') + echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - uses: actions/checkout@v4 with: submodules: recursive @@ -152,15 +161,15 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean /home/riscv + run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} - name: Upload instalation logs uses: actions/upload-artifact@v4 if: always() with: - name: installation-logs-custom-location-install - path: /home/riscv/logs/ + name: installation-logs-custom-location-install-${{ env.ARTIFACT_NAME }} + path: ${{ matrix.path }}/logs/ - name: Update setup.sh with new $RISCV location - run: sed -i 's,/opt/riscv,/home/riscv,g' setup.sh + run: sed -i 's,exit 1,export RISCV=${{ matrix.path }},g' setup.sh - name: make tests run: | source setup.sh @@ -174,5 +183,5 @@ jobs: uses: actions/upload-artifact@v4 if: always() with: - name: installation-logs-${{ env.ARTIFACT_NAME }} - path: /opt/riscv/logs/ + name: regression-logs-custom-location-install-${{ env.ARTIFACT_NAME }} + path: ${{ github.workspace }}/sim/verilator/logs/ From 59ee4cf7e4d0b5979cf1449653d520db2349fa57 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 17 Aug 2024 09:43:18 -0700 Subject: [PATCH 122/232] Switch to new RISCOF humber of jobs in install test --- .github/workflows/install.yml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index a653fac5c..771255ff7 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -32,7 +32,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | @@ -86,7 +85,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | @@ -125,7 +123,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | @@ -173,7 +170,6 @@ jobs: - name: make tests run: | source setup.sh - sed -i 's,jobs=4,jobs=3,g' "$WALLY"/tests/riscof/config.ini make riscof - name: regression run: | From 905521ef0ffbd2ad16ec66bbfd2b85106aeb494e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 30 Sep 2024 08:07:35 -0700 Subject: [PATCH 123/232] Update ci to use make --jobs --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 771255ff7..a84f93866 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -32,7 +32,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh @@ -85,7 +85,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh @@ -123,7 +123,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh @@ -170,7 +170,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: regression run: | source setup.sh From 76503e517e8dec21049ffbac8f0cd94e2945bb2a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 8 Oct 2024 15:20:02 -0700 Subject: [PATCH 124/232] Running out of space --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index a84f93866..b0e5255a8 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -32,7 +32,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof --jobs $(nproc --ignore 1) + make riscof - name: regression run: | source setup.sh From e50d85aa729885fa2cb1eba360734da391a0f6a1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 10 Oct 2024 13:59:36 -0700 Subject: [PATCH 125/232] Trying to track down storage issue --- .github/workflows/install.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b0e5255a8..25762b4e1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -171,6 +171,10 @@ jobs: run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: regression run: | source setup.sh From d389bb547fd795136a9d9b5e8f97f7ace8693431 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 11 Oct 2024 21:54:28 -0700 Subject: [PATCH 126/232] Add storage checks --- .github/workflows/install.yml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 25762b4e1..5f58eef31 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -29,10 +29,18 @@ jobs: with: name: installation-logs-${{ matrix.os }} path: /opt/riscv/logs/ + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: make tests run: | source setup.sh make riscof + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: regression run: | source setup.sh @@ -82,10 +90,18 @@ jobs: with: name: installation-logs-${{ env.ARTIFACT_NAME }} path: /opt/riscv/logs/ + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: make tests run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + - name: check storage + run: | + df -h + du -h --max-depth=1 - name: regression run: | source setup.sh From 7d6e283e041f3952da106f708fe16dc14fb547ce Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 20:41:00 -0700 Subject: [PATCH 127/232] Use precompiled riscv-gnu-toolchain binary for faster test --- bin/wally-tool-chain-install.sh | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..ba51ab5dc 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -230,19 +230,20 @@ section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then - cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout b488ddb #&& git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - if [ "$clean" ]; then - cd "$RISCV" - rm -rf riscv-gnu-toolchain - fi +curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-20.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 +# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then +# cd riscv-gnu-toolchain +# git reset --hard && git clean -f && git checkout b488ddb #&& git pull +# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] +# if [ "$clean" ]; then +# cd "$RISCV" +# rm -rf riscv-gnu-toolchain +# fi echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -else - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -fi +# else +# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +# fi # elf2hex (https://github.com/sifive/elf2hex) From 19e15aee12db0cdf0ea676017caeab829de2363c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:17:20 -0700 Subject: [PATCH 128/232] Only clone needed submodules --- .github/workflows/install.yml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 5f58eef31..fea433ce1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -14,8 +14,8 @@ jobs: os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] steps: - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -73,8 +73,8 @@ jobs: dnf install -y sudo git dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Fix git ownership run: git config --global --add safe.directory '*' - name: Free up storage @@ -119,8 +119,8 @@ jobs: runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -166,8 +166,8 @@ jobs: name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - uses: actions/checkout@v4 - with: - submodules: recursive + - name: Clone Necessary Submodules + run: git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h From ec3907bfd75ea7ea3cf1c4093b830f9a6f3a4d4e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:30:18 -0700 Subject: [PATCH 129/232] Revert "Use precompiled riscv-gnu-toolchain binary for faster test" This reverts commit af480292f355e82c6bdc4cef040bdedc52dfd8fd. --- bin/wally-tool-chain-install.sh | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index ba51ab5dc..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -230,20 +230,19 @@ section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-20.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 -# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then -# cd riscv-gnu-toolchain -# git reset --hard && git clean -f && git checkout b488ddb #&& git pull -# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] -# if [ "$clean" ]; then -# cd "$RISCV" -# rm -rf riscv-gnu-toolchain -# fi +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then + cd riscv-gnu-toolchain + git reset --hard && git clean -f && git checkout b488ddb #&& git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + if [ "$clean" ]; then + cd "$RISCV" + rm -rf riscv-gnu-toolchain + fi echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -# else -# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -# fi +else + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +fi # elf2hex (https://github.com/sifive/elf2hex) From 77ed0b4ca5f2b50914092d6c6779efef6f01fd9f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 21:48:00 -0700 Subject: [PATCH 130/232] Fix git permissions --- .github/workflows/install.yml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index fea433ce1..d742b0ce4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -15,7 +15,9 @@ jobs: steps: - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -74,9 +76,9 @@ jobs: dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test - - name: Fix git ownership - run: git config --global --add safe.directory '*' + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -120,7 +122,9 @@ jobs: steps: - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h @@ -167,7 +171,9 @@ jobs: echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - uses: actions/checkout@v4 - name: Clone Necessary Submodules - run: git submodule update --init addins/riscv-arch-test + run: | + git config --global --add safe.directory '*' + git submodule update --init addins/riscv-arch-test - name: Free up storage run: | df -h From 62743d8237f9c7661683179f1943936265932bf9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 13 Oct 2024 23:30:37 -0700 Subject: [PATCH 131/232] No buildroot and use precompiled gcc --- .github/workflows/install.yml | 8 ++++---- bin/wally-tool-chain-install.sh | 31 ++++++++++++++++--------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index d742b0ce4..37eeda1ae 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -24,7 +24,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean + run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -85,7 +85,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean + run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -133,7 +133,7 @@ jobs: - name: install packages with sudo run: sudo ./bin/wally-package-install.sh - name: install - run: ./bin/wally-tool-chain-install.sh --clean + run: ./bin/wally-tool-chain-install.sh --clean --no-buildroot - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -180,7 +180,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} + run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot ${{ matrix.path }} - name: Upload instalation logs uses: actions/upload-artifact@v4 if: always() diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fdb9d6e4f..59e26eb66 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -228,21 +228,22 @@ fi # This book is tested with GCC 13.2.0 section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" -cd "$RISCV" -# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then - cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout b488ddb #&& git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] - if [ "$clean" ]; then - cd "$RISCV" - rm -rf riscv-gnu-toolchain - fi - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -else - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -fi +curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 +# cd "$RISCV" +# # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. +# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then +# cd riscv-gnu-toolchain +# git reset --hard && git clean -f && git checkout b488ddb #&& git pull +# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] +# if [ "$clean" ]; then +# cd "$RISCV" +# rm -rf riscv-gnu-toolchain +# fi +# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" +# else +# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +# fi # elf2hex (https://github.com/sifive/elf2hex) From 361b4835a783152c9b7c835d91b8958ba201b24e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 00:23:07 -0700 Subject: [PATCH 132/232] revert precompiled gcc --- bin/wally-tool-chain-install.sh | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 59e26eb66..fdb9d6e4f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -228,22 +228,21 @@ fi # This book is tested with GCC 13.2.0 section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" -curl --location https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 -# cd "$RISCV" -# # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -# if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then -# cd riscv-gnu-toolchain -# git reset --hard && git clean -f && git checkout b488ddb #&& git pull -# ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -# make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] -# if [ "$clean" ]; then -# cd "$RISCV" -# rm -rf riscv-gnu-toolchain -# fi -# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" -# else -# echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" -# fi +cd "$RISCV" +# Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then + cd riscv-gnu-toolchain + git reset --hard && git clean -f && git checkout b488ddb #&& git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + if [ "$clean" ]; then + cd "$RISCV" + rm -rf riscv-gnu-toolchain + fi + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" +else + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" +fi # elf2hex (https://github.com/sifive/elf2hex) From 86d0e13330c046475845a1a29605a592ffc28a8d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 00:48:39 -0700 Subject: [PATCH 133/232] Update submodules that are checked out --- .github/workflows/install.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 37eeda1ae..cfbb3a4d4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -17,7 +17,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h @@ -78,7 +78,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h @@ -124,7 +124,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h @@ -173,7 +173,7 @@ jobs: - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test + git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free up storage run: | df -h From 732f5a932607dadec32fffcf7221c1525f76125a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 07:47:45 -0700 Subject: [PATCH 134/232] Add buildroot back to installation test --- .github/workflows/install.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index cfbb3a4d4..9b150f793 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -24,7 +24,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -38,7 +38,7 @@ jobs: - name: make tests run: | source setup.sh - make riscof + make riscof --jobs $(nproc --ignore 1) - name: check storage run: | df -h @@ -85,7 +85,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot + run: sudo ./bin/wally-tool-chain-install.sh --clean - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -133,7 +133,7 @@ jobs: - name: install packages with sudo run: sudo ./bin/wally-package-install.sh - name: install - run: ./bin/wally-tool-chain-install.sh --clean --no-buildroot + run: ./bin/wally-tool-chain-install.sh --clean - name: Upload installation logs uses: actions/upload-artifact@v4 if: always() @@ -180,7 +180,7 @@ jobs: ./.github/cli-space-cleanup.sh df -h - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean --no-buildroot ${{ matrix.path }} + run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} - name: Upload instalation logs uses: actions/upload-artifact@v4 if: always() From 4a337bf1d86d5afe15bb4efcc280ef042ba92699 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 22:34:16 -0700 Subject: [PATCH 135/232] Remove buildroot/output/build to save save in installation test --- .github/workflows/install.yml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 9b150f793..7e912fb46 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -41,8 +41,8 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: check storage run: | + sudo rm -rf /opt/riscv/buildroot/output/build df -h - du -h --max-depth=1 - name: regression run: | source setup.sh @@ -102,8 +102,8 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: check storage run: | + sudo rm -rf /opt/riscv/buildroot/output/build df -h - du -h --max-depth=1 - name: regression run: | source setup.sh @@ -144,6 +144,10 @@ jobs: run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + - name: check storage + run: | + sudo rm -rf /opt/riscv/buildroot/output/build + df -h - name: regression run: | source setup.sh @@ -195,8 +199,8 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: check storage run: | + sudo rm -rf ${{ matrix.path }}/buildroot/output/build df -h - du -h --max-depth=1 - name: regression run: | source setup.sh From f6d6537c7b673bb0caba4940a8ff2485dde2c69d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:11:17 -0700 Subject: [PATCH 136/232] Combine Ubuntu and Red Hat test installation workflows --- .github/workflows/install.yml | 124 ++++++++++++++-------------------- 1 file changed, 51 insertions(+), 73 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 7e912fb46..359868b3a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -5,106 +5,84 @@ defaults: shell: bash jobs: - ubuntu_install: - name: Test installation on ${{ matrix.os }} - runs-on: ${{ matrix.os }} + installation_test: + name: Test installation for ${{ matrix.name }} strategy: fail-fast: false matrix: - os: ["ubuntu-20.04", "ubuntu-22.04", "ubuntu-24.04"] + include: + # Ubuntu Installations + - name: ubuntu-20.04 + os: ubuntu-20.04 + container: null + - name: ubuntu-22.04 + os: ubuntu-22.04 + container: null + - name: ubuntu-24.04 + os: ubuntu-24.04 + container: null + # Red Hat Installations + - name: rocky-8 + os: ubuntu-latest + image: rockylinux:8 + - name: rocky-9 + os: ubuntu-latest + image: rockylinux:9 + - name: almalinux-8 + os: ubuntu-latest + image: almalinux:8 + - name: almalinux-9 + os: ubuntu-latest + image: almalinux:9 + + runs-on: ${{ matrix.os }} + container: + image: ${{ matrix.image }} + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: + - name: Install Dependencies for Red Hat + if: ${{ matrix.image }} != null + run: | + dnf install -y sudo git + dnf install curl -y --allowerasing || true - uses: actions/checkout@v4 - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage + - name: Free Up Storage for Ubuntu + if: ${{ matrix.image }} == null run: | df -h ./.github/cli-space-cleanup.sh df -h - - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: Upload installation logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-${{ matrix.os }} - path: /opt/riscv/logs/ - - name: check storage - run: | - df -h - du -h --max-depth=1 - - name: make tests - run: | - source setup.sh - make riscof --jobs $(nproc --ignore 1) - - name: check storage - run: | - sudo rm -rf /opt/riscv/buildroot/output/build - df -h - - name: regression - run: | - source setup.sh - regression-wally - - name: Upload regression logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: regression-logs-${{ matrix.os }} - path: ${{ github.workspace }}/sim/verilator/logs/ - - rhel_family_install: - name: Test installation on ${{ matrix.os }} - runs-on: ubuntu-latest - container: - image: ${{ matrix.os }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash - strategy: - fail-fast: false - matrix: - os: ["rockylinux:8", "rockylinux:9", "almalinux:8", "almalinux:9"] - steps: - - name: Unique name for Artifacts - id: prep_artifact_name - run: | - name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') - echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - - name: Install dependencies - run: | - dnf install -y sudo git - dnf install curl -y --allowerasing || true - - uses: actions/checkout@v4 - - name: Clone Necessary Submodules - run: | - git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage + - name: Free Up Storage for Red Hat + if: ${{ matrix.image }} != null run: | df -h nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" df -h - - name: install + - name: Install run: sudo ./bin/wally-tool-chain-install.sh --clean - - name: Upload installation logs + - name: Set Environment Variables + run: | + source setup.sh + echo "RISCV=$RISCV" >> "$GITHUB_ENV" + - name: Upload Installation Logs uses: actions/upload-artifact@v4 if: always() with: - name: installation-logs-${{ env.ARTIFACT_NAME }} - path: /opt/riscv/logs/ - - name: check storage - run: | - df -h - du -h --max-depth=1 + name: installation-logs-${{ matrix.name }} + path: $RISCV/logs/ - name: make tests run: | source setup.sh make riscof --jobs $(nproc --ignore 1) - - name: check storage + - name: Remove Buildroot to Save Space run: | sudo rm -rf /opt/riscv/buildroot/output/build df -h - - name: regression + - name: Regression run: | source setup.sh regression-wally @@ -112,7 +90,7 @@ jobs: uses: actions/upload-artifact@v4 if: always() with: - name: regression-logs-${{ env.ARTIFACT_NAME }} + name: regression-logs-${{ matrix.name }} path: ${{ github.workspace }}/sim/verilator/logs/ From 204661e286f61e8dc2f145678d1b5d61e59ad152 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:23:40 -0700 Subject: [PATCH 137/232] Fix github action syntax --- .github/workflows/install.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 359868b3a..e23e35d0a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -41,7 +41,7 @@ jobs: options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: - name: Install Dependencies for Red Hat - if: ${{ matrix.image }} != null + if: ${{ matrix.image != null }} run: | dnf install -y sudo git dnf install curl -y --allowerasing || true @@ -51,13 +51,13 @@ jobs: git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - name: Free Up Storage for Ubuntu - if: ${{ matrix.image }} == null + if: ${{ matrix.image == null }} run: | df -h ./.github/cli-space-cleanup.sh df -h - name: Free Up Storage for Red Hat - if: ${{ matrix.image }} != null + if: ${{ matrix.image != null }} run: | df -h nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" From f01a410cd50b89d97d4ea865b5ed89a14d9d490d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:37:18 -0700 Subject: [PATCH 138/232] Test variables --- .github/workflows/install.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e23e35d0a..a149c9750 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -40,6 +40,11 @@ jobs: image: ${{ matrix.image }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: + - name: Echo Variables + run: | + echo ${{ matrix.name }} + echo ${{ matrix.os }} + echo ${{ matrix.image }} - name: Install Dependencies for Red Hat if: ${{ matrix.image != null }} run: | From 53d40869478fb2fbbb12c6dc854d9a0dc290b014 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 14 Oct 2024 23:51:23 -0700 Subject: [PATCH 139/232] Combine storage clean up steps --- .github/workflows/install.yml | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index a149c9750..0956ef23b 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -40,11 +40,6 @@ jobs: image: ${{ matrix.image }} options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash steps: - - name: Echo Variables - run: | - echo ${{ matrix.name }} - echo ${{ matrix.os }} - echo ${{ matrix.image }} - name: Install Dependencies for Red Hat if: ${{ matrix.image != null }} run: | @@ -55,17 +50,14 @@ jobs: run: | git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free Up Storage for Ubuntu - if: ${{ matrix.image == null }} + - name: Free Up Storage run: | df -h - ./.github/cli-space-cleanup.sh - df -h - - name: Free Up Storage for Red Hat - if: ${{ matrix.image != null }} - run: | - df -h - nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" + if [ -z ${{ matrix.image }} ]; then + ./.github/cli-space-cleanup.sh + else + nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" + fi df -h - name: Install run: sudo ./bin/wally-tool-chain-install.sh --clean From 10f0e5eeeecac5336024ebdfcef35934b4f85a4d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 00:11:09 -0700 Subject: [PATCH 140/232] Combine remaining install tests --- .github/workflows/install.yml | 120 ++++++---------------------------- 1 file changed, 21 insertions(+), 99 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0956ef23b..9441215a8 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -34,6 +34,16 @@ jobs: - name: almalinux-9 os: ubuntu-latest image: almalinux:9 + # User level installation + - name: user-install + os: ubuntu-latest + image: null + user: true + # Custom location installation + - name: custom-install + os: ubuntu-latest + image: null + riscv_path: /home/riscv runs-on: ${{ matrix.os }} container: @@ -60,9 +70,18 @@ jobs: fi df -h - name: Install - run: sudo ./bin/wally-tool-chain-install.sh --clean + run: | + if [ -z ${{ matrix.user }} ]; then + sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + else + sudo ./bin/wally-package-install.sh + . /bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + fi - name: Set Environment Variables run: | + if [ ! -z ${{ matrix.riscv_path }} ]; then + sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh + fi source setup.sh echo "RISCV=$RISCV" >> "$GITHUB_ENV" - name: Upload Installation Logs @@ -77,7 +96,7 @@ jobs: make riscof --jobs $(nproc --ignore 1) - name: Remove Buildroot to Save Space run: | - sudo rm -rf /opt/riscv/buildroot/output/build + sudo rm -rf $RISCV/buildroot/output/build df -h - name: Regression run: | @@ -89,100 +108,3 @@ jobs: with: name: regression-logs-${{ matrix.name }} path: ${{ github.workspace }}/sim/verilator/logs/ - - - user_install: - name: Test installation with user permissions - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - name: Clone Necessary Submodules - run: | - git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - name: install packages with sudo - run: sudo ./bin/wally-package-install.sh - - name: install - run: ./bin/wally-tool-chain-install.sh --clean - - name: Upload installation logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-user-install - path: ~/riscv/logs/ - - name: make tests - run: | - source setup.sh - make riscof --jobs $(nproc --ignore 1) - - name: check storage - run: | - sudo rm -rf /opt/riscv/buildroot/output/build - df -h - - name: regression - run: | - source setup.sh - regression-wally - - name: Upload regression logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: regression-logs-user-install - path: ${{ github.workspace }}/sim/verilator/logs/ - - - custom_location_install: - name: Test installation with custom location ${{ matrix.path }} - runs-on: ubuntu-latest - strategy: - fail-fast: false - matrix: - path: ["/home/riscv"] - steps: - - name: Unique name for Artifacts - id: prep_artifact_name - run: | - name=$(echo -n "${{ matrix.os }}" | sed -e 's/[ \t:\/\\"<>|*?]/-/g' -e 's/--*/-/g') - echo "ARTIFACT_NAME=$name" >> $GITHUB_ENV - - uses: actions/checkout@v4 - - name: Clone Necessary Submodules - run: | - git config --global --add safe.directory '*' - git submodule update --init addins/riscv-arch-test addins/verilog-ethernet - - name: Free up storage - run: | - df -h - ./.github/cli-space-cleanup.sh - df -h - - name: install - run: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.path }} - - name: Upload instalation logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: installation-logs-custom-location-install-${{ env.ARTIFACT_NAME }} - path: ${{ matrix.path }}/logs/ - - name: Update setup.sh with new $RISCV location - run: sed -i 's,exit 1,export RISCV=${{ matrix.path }},g' setup.sh - - name: make tests - run: | - source setup.sh - make riscof --jobs $(nproc --ignore 1) - - name: check storage - run: | - sudo rm -rf ${{ matrix.path }}/buildroot/output/build - df -h - - name: regression - run: | - source setup.sh - regression-wally - - name: Upload regression logs - uses: actions/upload-artifact@v4 - if: always() - with: - name: regression-logs-custom-location-install-${{ env.ARTIFACT_NAME }} - path: ${{ github.workspace }}/sim/verilator/logs/ From 43b2737a0357eacf30f6210dd1ed417102b8c9c8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 00:29:05 -0700 Subject: [PATCH 141/232] Fix typo --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 9441215a8..0b462ab9e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -75,7 +75,7 @@ jobs: sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} else sudo ./bin/wally-package-install.sh - . /bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} + ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} fi - name: Set Environment Variables run: | From 8fea89ac8758cce7655821d5c8ce7a277ffc2cc9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 19:30:05 -0700 Subject: [PATCH 142/232] Fix installation log path --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0b462ab9e..13ebaadc4 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -89,7 +89,7 @@ jobs: if: always() with: name: installation-logs-${{ matrix.name }} - path: $RISCV/logs/ + path: ${{ env.RISCV }}/logs/ - name: make tests run: | source setup.sh From 58b4ecc211e0fa9c8c37eb0c0262721c4bdc7494 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 19:30:44 -0700 Subject: [PATCH 143/232] Skip regression for ubuntu 20.04 and red hat 8 because of broken verilator --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 13ebaadc4..62faca3dd 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -99,6 +99,7 @@ jobs: sudo rm -rf $RISCV/buildroot/output/build df -h - name: Regression + if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}} run: | source setup.sh regression-wally From 771ed52c951774bc895a40c164c3b139c3c30bcd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 19:48:24 -0700 Subject: [PATCH 144/232] Add schedule to run weekly --- .github/workflows/install.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 62faca3dd..9c7f31a58 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,9 +1,12 @@ name: Installation -on: [workflow_dispatch, push] +on: + workflow_dispatch: + push: + schedule: + - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays defaults: run: shell: bash - jobs: installation_test: name: Test installation for ${{ matrix.name }} From bad3c7ab2efe700890d071e78ff8ec60f202deec Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 20:27:44 -0700 Subject: [PATCH 145/232] Only run installation test workflow for PRs that edit the installation scripts --- .github/workflows/install.yml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 9c7f31a58..d93cd7811 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,7 +1,13 @@ name: Installation on: workflow_dispatch: - push: + pull_request: + branches: + - main + paths: + - 'bin/wally-tool-chain-install.sh' + - 'bin/wally-distro-check.sh' + - 'wally-package-install.sh' schedule: - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays defaults: From b0bc463c65bd2906e421e8aa69f783ec82a59433 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:05:35 -0700 Subject: [PATCH 146/232] Update gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 6aacdec2e..6afe74a2a 100644 --- a/.gitignore +++ b/.gitignore @@ -14,6 +14,7 @@ *.list # General directories to ignore +!.github/ .vscode/ __pycache__/ **/work* From af2edac7be4cd2ca400ff91f65fe65121b3e19f0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:06:39 -0700 Subject: [PATCH 147/232] Update gitignore for real --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 6afe74a2a..114d669ef 100644 --- a/.gitignore +++ b/.gitignore @@ -14,7 +14,7 @@ *.list # General directories to ignore -!.github/ +!.github/workflows/* .vscode/ __pycache__/ **/work* From ba243c8dbe82cfa21aa3232a9b4a58ff21e6b3c4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:07:17 -0700 Subject: [PATCH 148/232] Try updating gitignore again --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 114d669ef..f09faa3c0 100644 --- a/.gitignore +++ b/.gitignore @@ -14,10 +14,10 @@ *.list # General directories to ignore -!.github/workflows/* .vscode/ __pycache__/ **/work* +!.github/workflows/* /**/obj_dir* /**/gmon* From 7de44871ef7744a8529803843462d925f7535688 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:08:03 -0700 Subject: [PATCH 149/232] Finally got gitignore --- .gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index f09faa3c0..31db4f885 100644 --- a/.gitignore +++ b/.gitignore @@ -17,7 +17,7 @@ .vscode/ __pycache__/ **/work* -!.github/workflows/* +!.github/* /**/obj_dir* /**/gmon* From b4447b393c3cf8fb20e1d4fe78e0ed334857d888 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:08:18 -0700 Subject: [PATCH 150/232] Add header to install.yml --- .github/workflows/install.yml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index d93cd7811..e761fd2a3 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -1,3 +1,12 @@ +################################## +# install.yml +# jcarlin@hmc.edu October 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# GitHub Action to test the wally-tool-chain-install.sh script for all supported linux distributions +# and configurations. Runs weekly and on pull requests that modify the installation scripts. +################################## + name: Installation on: workflow_dispatch: From ffee13625b3b2ae0da3de7ea25084ed6fc8e5873 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 21:16:21 -0700 Subject: [PATCH 151/232] Add comments --- .github/workflows/install.yml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e761fd2a3..c0e1d6506 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -8,6 +8,8 @@ ################################## name: Installation + +# Run on PR that modifies the installation scripts, weekly, or manually on: workflow_dispatch: pull_request: @@ -19,9 +21,12 @@ on: - 'wally-package-install.sh' schedule: - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays + +# Use bash shell with extra GitHub Actions options for all jobs defaults: run: shell: bash + jobs: installation_test: name: Test installation for ${{ matrix.name }} @@ -63,21 +68,26 @@ jobs: image: null riscv_path: /home/riscv + # run on selected version of ubuntu or on ubuntu-latest with docker image runs-on: ${{ matrix.os }} container: image: ${{ matrix.image }} - options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash + options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash # Allow for connection with host + steps: + # Docker images need git installed or the checkout action fails - name: Install Dependencies for Red Hat if: ${{ matrix.image != null }} run: | dnf install -y sudo git dnf install curl -y --allowerasing || true + # Only clone submodules needed for standard tests/regression to save space - uses: actions/checkout@v4 - name: Clone Necessary Submodules run: | git config --global --add safe.directory '*' git submodule update --init addins/riscv-arch-test addins/verilog-ethernet + # Free up space on the host machine, either from the container or the host - name: Free Up Storage run: | df -h @@ -87,6 +97,7 @@ jobs: nsenter -t 1 -m -u -n -i bash -c "$(cat .github/cli-space-cleanup.sh)" fi df -h + # Run main tool chain installation script, either as a user or system wide - name: Install run: | if [ -z ${{ matrix.user }} ]; then @@ -95,6 +106,7 @@ jobs: sudo ./bin/wally-package-install.sh ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }} fi + # Set environment variables for the rest of the job - name: Set Environment Variables run: | if [ ! -z ${{ matrix.riscv_path }} ]; then @@ -102,25 +114,30 @@ jobs: fi source setup.sh echo "RISCV=$RISCV" >> "$GITHUB_ENV" + # Upload installation logs for debugging - name: Upload Installation Logs uses: actions/upload-artifact@v4 if: always() with: name: installation-logs-${{ matrix.name }} path: ${{ env.RISCV }}/logs/ + # Make riscof only as that is the only testsuite used by standard regression - name: make tests run: | source setup.sh make riscof --jobs $(nproc --ignore 1) + # Only the linux-testvectors are needed, so remove the rest of the buildroot to save space - name: Remove Buildroot to Save Space run: | sudo rm -rf $RISCV/buildroot/output/build df -h + # Run standard regression, skipping distros that are known to be broken with Verilator - name: Regression if: ${{ matrix.name != 'ubuntu-20.04' && matrix.name != 'rocky-8' && matrix.name != 'almalinux-8'}} run: | source setup.sh regression-wally + # Upload regression logs for debugging - name: Upload regression logs uses: actions/upload-artifact@v4 if: always() From df86ecf128cecb8cb31771de9bed75560d30abc1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 22:01:28 -0700 Subject: [PATCH 152/232] Fix installation CI timezone --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index c0e1d6506..dfa449526 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -20,7 +20,7 @@ on: - 'bin/wally-distro-check.sh' - 'wally-package-install.sh' schedule: - - cron: "0 0 * * 3" # Run at 12:00 AM on Wednesdays + - cron: "0 7 * * 3" # Run at 12:00 AM Pacific Time on Wednesdays # Use bash shell with extra GitHub Actions options for all jobs defaults: From a0245622dc5b351ec78838dc654545acf415c211 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 22:26:27 -0700 Subject: [PATCH 153/232] Make zsbl in Installation CI because it is used in standard regression tests --- .github/workflows/install.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index dfa449526..15f41b36b 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -121,11 +121,11 @@ jobs: with: name: installation-logs-${{ matrix.name }} path: ${{ env.RISCV }}/logs/ - # Make riscof only as that is the only testsuite used by standard regression + # Make riscof and zsbl only as that is the only testsuite used by standard regression - name: make tests run: | source setup.sh - make riscof --jobs $(nproc --ignore 1) + make riscof zsbl --jobs $(nproc --ignore 1) # Only the linux-testvectors are needed, so remove the rest of the buildroot to save space - name: Remove Buildroot to Save Space run: | From 658a57a2dde99cc76d2cd04f6e9e77c285ccd20b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 15 Oct 2024 22:44:19 -0700 Subject: [PATCH 154/232] Run lint for distros that Verilator fails sim in Installation CI --- .github/workflows/install.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 15f41b36b..e80bb4ef1 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -137,6 +137,11 @@ jobs: run: | source setup.sh regression-wally + - name: Lint Only (for distros with broken Verilator sim) + if: ${{ matrix.name == 'ubuntu-20.04' || matrix.name == 'rocky-8' || matrix.name == 'almalinux-8'}} + run: | + source setup.sh + lint-wally # Upload regression logs for debugging - name: Upload regression logs uses: actions/upload-artifact@v4 From 2e774aa0558a6395eb027b62dc63d298a2851f47 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 16 Oct 2024 00:47:26 -0700 Subject: [PATCH 155/232] Run wsim on broken distros --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e80bb4ef1..6ada085c7 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -142,6 +142,7 @@ jobs: run: | source setup.sh lint-wally + wsim rv32i arch32i --sim verilator # Upload regression logs for debugging - name: Upload regression logs uses: actions/upload-artifact@v4 From 2f22b236fcfd749899a86f48c6cfca438ecb9027 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 16 Oct 2024 00:48:27 -0700 Subject: [PATCH 156/232] Save wsim to log --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 6ada085c7..0c4f5d2d3 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -142,7 +142,7 @@ jobs: run: | source setup.sh lint-wally - wsim rv32i arch32i --sim verilator + wsim rv32i arch32i --sim verilator | tee $WALLY/sim/verilator/logs/rv32i_arch32i.log # Upload regression logs for debugging - name: Upload regression logs uses: actions/upload-artifact@v4 From a9e41c1a7c20602beb3562436218a3a7026b4d26 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Wed, 16 Oct 2024 07:14:11 -0700 Subject: [PATCH 157/232] Improving the priv func cov flow to run with --fcovpriv flag --- bin/regression-wally | 23 ++++++-------------- bin/wsim | 14 ++++++------ config/rv64gc/coverage.svh | 10 ++++----- sim/Makefile | 10 +-------- sim/questa/wally.do | 44 +++++++++++++++++++++----------------- 5 files changed, 44 insertions(+), 57 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 67cd4815b..73f3cde93 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -366,7 +366,7 @@ defaultsim = "verilator" # Default simulator for all other tests parser = argparse.ArgumentParser() parser.add_argument("--ccov", help="Code Coverage", action="store_true") parser.add_argument("--fcov", help="Functional Coverage", action="store_true") -parser.add_argument("--fcovrvvi", help="Functional Coverage RVVI", action="store_true") +parser.add_argument("--fcovpriv", help="Privilege Functional Coverage", action="store_true") parser.add_argument("--nightly", help="Run large nightly regression", action="store_true") parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") @@ -385,8 +385,8 @@ if (args.ccov): # only run RV64GC tests in coverage mode coverStr = '--ccov' elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode coverStr = '--fcov' -elif (args.fcovrvvi): # only run RV64GC tests in rvvi coverage mode - coverStr = '--fcovrvvi' +elif (args.fcovrvvi): # only run RV64GC tests in lockstep in coverage mode + coverStr = '--fcovpriv' else: coverStr = '' @@ -412,14 +412,10 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): addTests(tests64gc_fp, coveragesim) -elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode +elif (args.fcov or args.fcovpriv): # only run RV64GC tests on Questa in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) # addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) -elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode - addTests(tests64gc_nofp, coveragesim) - if (args.fp): - addTests(tests64gc_fp, coveragesim) else: for sim in sims: if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one @@ -511,10 +507,7 @@ def main(): if args.ccov: TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') - elif args.fcovrvvi: - TIMEOUT_DUR = 20*60 - os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') - elif args.fcov: + elif args.fcov or args.fcovpriv: TIMEOUT_DUR = 2*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: @@ -529,7 +522,7 @@ def main(): # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system # right now fcov, ccov, nightly all use Imperas - if (args.ccov or args.fcov or args.nightly): + if (args.ccov or args.fcov or args.fcovpriv or args.nightly): ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses else: ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests @@ -548,10 +541,8 @@ def main(): # Coverage report if args.ccov: os.system('make QuestaCodeCoverage') - if args.fcov: + if args.fcov or args.fcovpriv: os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge') - if args.fcovrvvi: - os.system('make QuestaFunctCoverageRvvi') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/bin/wsim b/bin/wsim index 481e8674c..dc2122d34 100755 --- a/bin/wsim +++ b/bin/wsim @@ -29,7 +29,7 @@ parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true" parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true") parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") -parser.add_argument("--fcovrvvi", "-fr", help="Functional Coverage RVVI", action="store_true") +parser.add_argument("--fcovpriv", "-fpriv", help="Privileged Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") @@ -71,7 +71,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf')): exit(1) # Validate arguments -if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovrvvi or args.lockstep or args.lockstepverbose): +if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovpriv or args.lockstep or args.lockstepverbose): if args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") exit(1) @@ -89,7 +89,7 @@ if (args.tb == "testbench_fp"): if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 prefix = "" -if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): +if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp or args.fcovpriv): if (args.sim == "questa" or args.sim == "vcs"): prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" if (args.sim == "questa"): @@ -104,7 +104,7 @@ if (args.lockstep or args.lockstepverbose): else: EnableLog = 0 ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr suffix = "" - if(args.fcov): + if(args.fcov or args.fcovpriv): CovEnableStr = "1" if int(args.covlog) > 0 else "0"; if(args.covlog >= 1): EnableLog = 1 else: EnableLog = 0 @@ -129,12 +129,12 @@ if (args.fcov): flags += " --fcov" if (args.fcovimp): flags += " --fcovimp" -if (args.fcovrvvi): - flags += "--fcovrvvi" +if (args.fcovpriv): + flags += "--fcovpriv" # create the output sub-directories. regressionDir = WALLY + '/sim/' -for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb", "fcovrvvi", "fcovrvvi_ucdb"]: +for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: try: os.mkdir(regressionDir+args.sim+"/"+d) except: diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d1bbaedbb..46f9c4f26 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,11 +9,11 @@ `include "RV64M_coverage.svh" `include "RV64F_coverage.svh" `include "RV64Zfh_coverage.svh" -// `include "RV64VM_coverage.svh" -// `include "RV64VM_PMP_coverage.svh" -// `include "RV64CBO_VM_coverage.svh" -// `include "RV64CBO_PMP_coverage.svh" -// `include "RV64Zicbom_coverage.svh" +`include "RV64VM_coverage.svh" +`include "RV64VM_PMP_coverage.svh" +`include "RV64CBO_VM_coverage.svh" +`include "RV64CBO_PMP_coverage.svh" +`include "RV64Zicbom_coverage.svh" `include "RV64Zicond_coverage.svh" `include "RV64Zca_coverage.svh" `include "RV64Zcb_coverage.svh" diff --git a/sim/Makefile b/sim/Makefile index 5f225584e..d94936381 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -27,7 +27,7 @@ deriv: -.PHONY: QuestaCodeCoverage QuestaFunctCoverageRvvi collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov +.PHONY: QuestaCodeCoverage collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log @@ -51,14 +51,6 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb # vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb -QuestaFunctCoverageRvvi: ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb - vcover merge -out ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_*.ucdb -logfile ${SIM}/questa/fcovrvvi/log - vcover report -details -html ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb - vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.log - vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -testdetails -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.testdetails.log - vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcovrvvi/fcovrvvi.summary.log - grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcovrvvi/fcovrvvi.log - collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov riscvdv_functcov: diff --git a/sim/questa/wally.do b/sim/questa/wally.do index d147080f3..15a4fef4c 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -51,8 +51,6 @@ if [file exists ${WKDIR}] { vdel -lib ${WKDIR} -all } vlib ${WKDIR} -# Create directory for functional coverage data -mkdir -p ${FCRVVI} set PlusArgs "" set ParamArgs "" @@ -62,10 +60,8 @@ set ccov 0 set CoverageVoptArg "" set CoverageVsimArg "" -set FuncCovRVVI 0 -set FCdefineRVVI_COVERAGE "" - set FunctCoverage 0 +set FCpriv 0 set FCvlog "" set FCvopt "" set FCdefineCOVER_EXTS {} @@ -108,10 +104,18 @@ if {[lcheck lst "--ccov"]} { set CoverageVsimArg "-coverage" } -# if --fcovrvvi found set flag and remove from list -if {[lcheck lst "--fcovrvvi"]} { - set FuncCovRVVI 1 - set FCdefineRVVI_COVERAGE "+define+RVVI_COVERAGE" +# if --fcovpriv found set flag and remove from list +if {[lcheck lst "--fcovpriv"]} { + set FunctCoverage 1 + set FCpriv 1 + set FCvlog "+define+INCLUDE_TRACE2COV \ + +define+IDV_INCLUDE_TRACE2COV \ + +define+COVER_BASE_RV32I \ + +define+COVER_PRIV \ + +incdir+$env(WALLY)/addins/riscvISACOV/source \ + " + + set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" } # if --fcovimp found set flag and remove from list @@ -138,11 +142,12 @@ if {[lcheck lst "--fcovimp"]} { if {[lcheck lst "--fcov"]} { set FunctCoverage 1 # COVER_BASE_RV32I is just needed to keep riscvISACOV happy, but no longer affects tests - set FCvlog "+define+INCLUDE_TRACE2COV \ + set FCvlog "+define+INCLUDE_TRACE2COV \ +define+IDV_INCLUDE_TRACE2COV \ +define+COVER_BASE_RV32I \ +incdir+$env(WALLY)/addins/riscvISACOV/source \ " + set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" } @@ -181,7 +186,6 @@ if {$DEBUG > 0} { echo "GUI = $GUI" echo "ccov = $ccov" echo "lockstep = $lockstep" - echo "FuncCovRVVI = $FuncCovRVVI" echo "FunctCoverage = $FunctCoverage" echo "remaining list = $lst" echo "Extra +args = $PlusArgs" @@ -192,9 +196,9 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals @@ -216,13 +220,13 @@ if { ${GUI} } { } if {$FunctCoverage} { - set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb - coverage save -onexit ${UCDB} -} - -if {$FuncCovRVVI} { - set UCDB ${WALLY}/addins/cvw-arch-verif/work/${CFG}_${TESTSUITE}.ucdb - coverage save -onexit ${UCDB} + if {$FCpriv} { + set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.priv.ucdb + coverage save -onexit ${UCDB} + } else { + set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb + coverage save -onexit ${UCDB} + } } run -all From 0429058bef1944c5caee2a72577333b04ea49954 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Wed, 16 Oct 2024 07:39:09 -0700 Subject: [PATCH 158/232] running separate regressions with --fcov and --focvpriv flags --- bin/regression-wally | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 73f3cde93..dc96766a0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -385,7 +385,7 @@ if (args.ccov): # only run RV64GC tests in coverage mode coverStr = '--ccov' elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode coverStr = '--fcov' -elif (args.fcovrvvi): # only run RV64GC tests in lockstep in coverage mode +elif (args.fcovpriv): # only run RV64GC tests in lockstep in coverage mode coverStr = '--fcovpriv' else: coverStr = '' @@ -412,10 +412,12 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): addTests(tests64gc_fp, coveragesim) -elif (args.fcov or args.fcovpriv): # only run RV64GC tests on Questa in lockstep in functional coverage mode +elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) - # addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) +elif (args.fcovpriv): # only run RV64GC tests on Questa in lockstep in functional coverage mode + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) + else: for sim in sims: if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one @@ -507,9 +509,12 @@ def main(): if args.ccov: TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') - elif args.fcov or args.fcovpriv: + elif args.fcov: TIMEOUT_DUR = 2*60 - os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') + os.system('rm -f questa/fcov_ucdb/*.elf.ucdb questa/fcov_logs/* questa/fcov/*') + elif args.fcovpriv: + TIMEOUT_DUR = 2*60 + os.system('rm -f questa/fcov_ucdb/*.elf.priv.ucdb questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day elif args.testfloat: From 7bed187e8d1681bbf367910179c23c03d04c3491 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Wed, 16 Oct 2024 09:44:34 -0700 Subject: [PATCH 159/232] Combinin fcov and fcovpriv --- bin/regression-wally | 15 ++++----------- bin/wsim | 9 +++------ sim/questa/wally.do | 24 ++---------------------- 3 files changed, 9 insertions(+), 39 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index dc96766a0..7d719dd6a 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -366,7 +366,6 @@ defaultsim = "verilator" # Default simulator for all other tests parser = argparse.ArgumentParser() parser.add_argument("--ccov", help="Code Coverage", action="store_true") parser.add_argument("--fcov", help="Functional Coverage", action="store_true") -parser.add_argument("--fcovpriv", help="Privilege Functional Coverage", action="store_true") parser.add_argument("--nightly", help="Run large nightly regression", action="store_true") parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") @@ -385,8 +384,6 @@ if (args.ccov): # only run RV64GC tests in coverage mode coverStr = '--ccov' elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode coverStr = '--fcov' -elif (args.fcovpriv): # only run RV64GC tests in lockstep in coverage mode - coverStr = '--fcovpriv' else: coverStr = '' @@ -415,8 +412,7 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) -elif (args.fcovpriv): # only run RV64GC tests on Questa in lockstep in functional coverage mode - addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) + #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) else: for sim in sims: @@ -511,10 +507,7 @@ def main(): os.system('rm -f questa/cov/*.ucdb') elif args.fcov: TIMEOUT_DUR = 2*60 - os.system('rm -f questa/fcov_ucdb/*.elf.ucdb questa/fcov_logs/* questa/fcov/*') - elif args.fcovpriv: - TIMEOUT_DUR = 2*60 - os.system('rm -f questa/fcov_ucdb/*.elf.priv.ucdb questa/fcov_logs/* questa/fcov/*') + os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day elif args.testfloat: @@ -527,7 +520,7 @@ def main(): # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system # right now fcov, ccov, nightly all use Imperas - if (args.ccov or args.fcov or args.fcovpriv or args.nightly): + if (args.ccov or args.fcov or args.nightly): ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses else: ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests @@ -546,7 +539,7 @@ def main(): # Coverage report if args.ccov: os.system('make QuestaCodeCoverage') - if args.fcov or args.fcovpriv: + if args.fcov: os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge') # Count the number of failures if num_fail: diff --git a/bin/wsim b/bin/wsim index dc2122d34..3f6cbaaae 100755 --- a/bin/wsim +++ b/bin/wsim @@ -29,7 +29,6 @@ parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true" parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true") parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") -parser.add_argument("--fcovpriv", "-fpriv", help="Privileged Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") @@ -71,7 +70,7 @@ if(args.lockstep and not args.testsuite.endswith('.elf')): exit(1) # Validate arguments -if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovpriv or args.lockstep or args.lockstepverbose): +if (args.gui or args.ccov or args.fcov or args.fcovimp or args.lockstep or args.lockstepverbose): if args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") exit(1) @@ -89,7 +88,7 @@ if (args.tb == "testbench_fp"): if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 prefix = "" -if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp or args.fcovpriv): +if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): if (args.sim == "questa" or args.sim == "vcs"): prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" if (args.sim == "questa"): @@ -104,7 +103,7 @@ if (args.lockstep or args.lockstepverbose): else: EnableLog = 0 ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr suffix = "" - if(args.fcov or args.fcovpriv): + if(args.fcov): CovEnableStr = "1" if int(args.covlog) > 0 else "0"; if(args.covlog >= 1): EnableLog = 1 else: EnableLog = 0 @@ -129,8 +128,6 @@ if (args.fcov): flags += " --fcov" if (args.fcovimp): flags += " --fcovimp" -if (args.fcovpriv): - flags += "--fcovpriv" # create the output sub-directories. regressionDir = WALLY + '/sim/' diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 15a4fef4c..d712d60ad 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -61,7 +61,6 @@ set CoverageVoptArg "" set CoverageVsimArg "" set FunctCoverage 0 -set FCpriv 0 set FCvlog "" set FCvopt "" set FCdefineCOVER_EXTS {} @@ -104,20 +103,6 @@ if {[lcheck lst "--ccov"]} { set CoverageVsimArg "-coverage" } -# if --fcovpriv found set flag and remove from list -if {[lcheck lst "--fcovpriv"]} { - set FunctCoverage 1 - set FCpriv 1 - set FCvlog "+define+INCLUDE_TRACE2COV \ - +define+IDV_INCLUDE_TRACE2COV \ - +define+COVER_BASE_RV32I \ - +define+COVER_PRIV \ - +incdir+$env(WALLY)/addins/riscvISACOV/source \ - " - - set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1" -} - # if --fcovimp found set flag and remove from list if {[lcheck lst "--fcovimp"]} { set FunctCoverage 1 @@ -220,13 +205,8 @@ if { ${GUI} } { } if {$FunctCoverage} { - if {$FCpriv} { - set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.priv.ucdb - coverage save -onexit ${UCDB} - } else { - set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb - coverage save -onexit ${UCDB} - } + set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb + coverage save -onexit ${UCDB} } run -all From 01805d9fb11784dfc9af437145f1fdc43df92eee Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Oct 2024 13:26:20 -0700 Subject: [PATCH 160/232] Corrected RV32gc imperas configuration --- config/rv32gc/imperas.ic | 5 ----- 1 file changed, 5 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 9e9eef55f..eb4039216 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -63,9 +63,6 @@ --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T -# nonratified mnosie register not implemented ---override cpu/mnoise_undefined=T - # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 --override cpu/ecode_mask=0x800000000000000F # for RV64 @@ -73,8 +70,6 @@ # Debug mode not yet supported --override cpu/debug_mode=none -# Zkr entropy source and seed register not supported. ---override cpu/Zkr=F --override cpu/reset_address=0x80000000 From 4bdc6749edb782e7ef1989c988cd76a5f36109c6 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 16 Oct 2024 18:23:03 -0700 Subject: [PATCH 161/232] Added flush to run_test_case regression-wally to ensure results are printed to stdout for regression-wally. --- bin/regression-wally | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 16286c60b..3b256182a 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -338,14 +338,15 @@ def run_test_case(config): grepfile = config.grepfile cmd = config.cmd os.chdir(regressionDir) - # print(" run_test_case invoking %s" % cmd) + # print(" run_test_case invoking %s" % cmd, flush=True) os.system(cmd) if search_log_for_text(config.grepstr, grepfile): -# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) - print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd)) + # Flush is needed to flush output to stdout when running in multiprocessing Pool +# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name), flush=True) + print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd), flush=True) return 0 else: - print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd)) + print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd), flush=True) print(" Check %s" % grepfile) return 1 From d21e2fa99711d2d4e72765226bc298f5f54fa5e4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Oct 2024 21:41:14 -0700 Subject: [PATCH 162/232] Increased timeout on regression-wally to avoid floating-point fcov runs from failing --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 67cd4815b..1c9e09bfe 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -515,7 +515,7 @@ def main(): TIMEOUT_DUR = 20*60 os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') elif args.fcov: - TIMEOUT_DUR = 2*60 + TIMEOUT_DUR = 4*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day From 9dcc0435b8a77fa95311424e790d400faa984605 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Oct 2024 21:47:04 -0700 Subject: [PATCH 163/232] Increased timeout on regression-wally to avoid floating-point fcov runs from failing --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 1c9e09bfe..a76836eea 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -515,7 +515,7 @@ def main(): TIMEOUT_DUR = 20*60 os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') elif args.fcov: - TIMEOUT_DUR = 4*60 + TIMEOUT_DUR = 8*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day From 9d941b7f2eab23819d10ab45652cadfb9bae0754 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 00:22:51 -0700 Subject: [PATCH 164/232] Fix missing directory in installation CI --- .github/workflows/install.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 0c4f5d2d3..8a7733c2e 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -137,10 +137,11 @@ jobs: run: | source setup.sh regression-wally - - name: Lint Only (for distros with broken Verilator sim) + - name: Lint + wsim Test Only (for distros with broken Verilator sim) if: ${{ matrix.name == 'ubuntu-20.04' || matrix.name == 'rocky-8' || matrix.name == 'almalinux-8'}} run: | source setup.sh + mkdir -p $WALLY/sim/verilator/logs/ lint-wally wsim rv32i arch32i --sim verilator | tee $WALLY/sim/verilator/logs/rv32i_arch32i.log # Upload regression logs for debugging From b10f46713ee86e0b73a8d3e0729c72d786efc386 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 00:27:47 -0700 Subject: [PATCH 165/232] Add installation status badge to README --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index f5dfe0f47..b77024a5b 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,4 @@ +![Installation CI](https://github.com/jordancarlin/cvw/actions/workflows/install.yml/badge.svg?branch=main) # core-v-wally Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores. From 58e093c9be824344cba9014902e2b5f1dabbce77 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 00:33:28 -0700 Subject: [PATCH 166/232] Add warning regarding broken Verilator on Ubuntu 20.04 and Red Hat 8 to compatibility section of README --- README.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index b77024a5b..a1dca4fd1 100644 --- a/README.md +++ b/README.md @@ -66,7 +66,11 @@ This section describes the open source toolchain installation. ### Compatibility The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9). -NOTE: Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. +> [!WARNING] +> Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. + +> [!WARNING] +> Verilator currently fails to simulate correctly on Ubuntu 20.04 LTS and Red Hat/Rocky/AlmaLinux 8. ### Overview The toolchain installation script installs the following tools: @@ -75,7 +79,6 @@ The toolchain installation script installs the following tools: - [QEMU](https://www.qemu.org/docs/master/system/target-riscv.html): emulator - [Spike](https://github.com/riscv-software-src/riscv-isa-sim): functional RISC-V model - [Verilator](https://github.com/verilator/verilator): open-source Verilog simulator - - NOTE: Verilator does not currently work reliably for simulating Wally on Ubuntu 20.04 LTS and Red Hat 8 - [RISC-V Sail Model](https://github.com/riscv/sail-riscv): golden reference model for RISC-V - [OSU Skywater 130 cell library](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12): standard cell library - [RISCOF](https://github.com/riscv-software-src/riscof.git): RISC-V compliance test framework From aa4304cb6c08d744fc02bd3cfa52e1a93f5420f5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 00:34:49 -0700 Subject: [PATCH 167/232] Document --no-buildroot flag for installation script --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a1dca4fd1..e4f7602e2 100644 --- a/README.md +++ b/README.md @@ -83,7 +83,7 @@ The toolchain installation script installs the following tools: - [OSU Skywater 130 cell library](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12): standard cell library - [RISCOF](https://github.com/riscv-software-src/riscof.git): RISC-V compliance test framework -Additionally, Buildroot Linux is built for Wally and linux test-vectors are generated for simulation. See the [Linux README](linux/README.md) for more details. +Additionally, Buildroot Linux is built for Wally and linux test-vectors are generated for simulation. See the [Linux README](linux/README.md) for more details. This can be skipped using the `--no-buildroot` flag. ### Installation From 055bcc5f97b85d8148aad14fb596370947f7a77c Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 9 Sep 2024 12:43:58 -0700 Subject: [PATCH 168/232] Changed make names to match new Linux makefile. Removed --buildroot option from regression call. --- bin/nightly_build.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 629da074e..0770de66f 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -751,8 +751,7 @@ def main(): # Compile Linux for local testing test_runner.set_env_var("RISCV",str(test_runner.cvw)) linux_path = test_runner.cvw / "linux" - test_runner.execute_makefile(target = "all_nosudo", makefile_path=linux_path) - test_runner.execute_makefile(target = "dumptvs_nosudo", makefile_path=linux_path) + test_runner.execute_makefile(target = "all", makefile_path=linux_path) ############################################# # RUN TESTS # From 25da694a2403c5c37cc8b32dffa0e7359e80aad9 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 11 Sep 2024 12:18:57 -0700 Subject: [PATCH 169/232] Laid out new CSV daily tracker and emailsender classes. --- bin/nightly_build.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 0770de66f..7d0dcefbe 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -794,8 +794,8 @@ def main(): logger.info(f"The total sucesses for all tests ran are: {total_number_success}") logger.info(f"The total failures for all tests ran are: {total_number_failures}") - # Copy actual test logs from sim/questa, sim/verilator - test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs"]) + # Copy actual test logs from sim/questa, sim/verilator, sim/vcs + test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs", test_runner.cvw / "sim/vcs/logs"]) ############################################# # FORMAT TESTS # From 35fa3ff461b3335f2372c8b96addef850d9336cf Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 26 Sep 2024 19:58:24 -0700 Subject: [PATCH 170/232] Fixed ERROR versus error bug in logger, fixed error in failed lint tests. Labeled lint tests in regression output. Changed test run directory to call direct location rather than calling unknown regression script --- bin/nightly_build.py | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 7d0dcefbe..b8bce5982 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -409,16 +409,16 @@ class TestRunner: if "Success" in line: passed_configs.append(line.split(':')[0].strip()) elif "passed lint" in line: - passed_configs.append(line.split(' ')[0].strip()) + passed_configs.append(f"Lint: {line.split(' ')[0].strip()}") #passed_configs.append(line) # potentially use a space elif "failed lint" in line: - failed_configs.append(line.split(' ')[0].strip(), "no log file") + failed_configs.append([f"Lint: {line.split(' ')[0].strip()}", "No Log File"]) #failed_configs.append(line) elif "Failures detected in output" in line: try: config_name = line.split(':')[0].strip() - log_file = os.path.abspath("logs/"+config_name+".log") + log_file = os.path.abspath(os.path.join("logs", config_name, ".log")) failed_configs.append((config_name, log_file)) except: failed_configs.append((config_name, "Log file not found")) @@ -619,7 +619,7 @@ class TestRunner: # check if there are any emails if not receiver_emails: - self.logger.ERROR("No receiver emails provided.") + self.logger.error("No receiver emails provided.") return # grab the html file @@ -777,7 +777,7 @@ def main(): passed, failed = test_runner.clean_format_output(input_file = output_location) logger.info(f"{test_name} has been formatted to markdown") except: - logger.ERROR(f"Error occured with formatting {test_name}") + logger.error(f"Error occured with formatting {test_name}") logger.info(f"The # of failures are for {test_name}: {len(failed)}") total_number_failures+= len(failed) @@ -787,15 +787,19 @@ def main(): total_number_success += len(passed) total_success.append(passed) test_runner.rewrite_to_markdown(test_name, passed, failed) + + newlinechar = "\n" + logger.info(f"Failed tests: \n{newlinechar.join([x[0] for x in failed])}") except Exception as e: - logger.error("There was an error in running the tests: {e}") + logger.error(f"There was an error in running the tests: {e}") logger.info(f"The total sucesses for all tests ran are: {total_number_success}") logger.info(f"The total failures for all tests ran are: {total_number_failures}") # Copy actual test logs from sim/questa, sim/verilator, sim/vcs - test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs", test_runner.cvw / "sim/vcs/logs"]) + if not args.tests == "test_lint": + test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs", test_runner.cvw / "sim/vcs/logs"]) ############################################# # FORMAT TESTS # From e4b4cff270eb95a09a3e18fb4ee347bbd6475f75 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 16 Oct 2024 18:48:08 -0700 Subject: [PATCH 171/232] Changed nightly_build.py to allow for nightly and buildroot to be passed as arguments --- bin/nightly_build.py | 50 +++++++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index b8bce5982..506a0e997 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -84,7 +84,7 @@ from pathlib import Path class FolderManager: """A class for managing folders and repository cloning.""" - def __init__(self): + def __init__(self, basedir): """ Initialize the FolderManager instance. @@ -92,8 +92,12 @@ class FolderManager: base_dir (str): The base directory where folders will be managed and repository will be cloned. """ env_extract_var = 'WALLY' - self.base_dir = os.environ.get(env_extract_var) - self.base_parent_dir = os.path.dirname(self.base_dir) + if os.environ.get(env_extract_var): + self.base_dir = os.environ.get(env_extract_var) + self.base_parent_dir = os.path.dirname(self.base_dir) + else: + self.base_dir = basedir + self.base_parent_dir = os.path.dirname(self.base_dir) # logger.info(f"Base directory: {self.base_dir}") # logger.info(f"Parent Base directory: {self.base_parent_dir}") @@ -313,7 +317,7 @@ class TestRunner: self.logger.error(f"Error making the tests. Target: {target}") return False - def run_tests(self, test_type=None, test_name=None, test_extension=None): + def run_tests(self, test_type=None, test_name=None, test_extensions=None): """ Run a script through the terminal and save the output to a file. @@ -329,12 +333,12 @@ class TestRunner: output_file = self.log_dir.joinpath(f"{test_name}-output.log") os.chdir(self.sim_dir) - if test_extension: - command = [test_type, test_name, test_extension] - self.logger.info(f"Command used to run tests: {test_type} {test_name} {test_extension}") + if test_extensions: + command = [test_type, test_name] + test_extensions + self.logger.info(f"Command used to run tests in directory {self.sim_dir}: {test_type} {test_name} {' '.join(test_extensions)}") else: command = [test_type, test_name] - self.logger.info(f"Command used to run tests: {test_type} {test_name}") + self.logger.info(f"Command used to run tests in directory {self.sim_dir}: {test_type} {test_name}") # Execute the command using subprocess and save the output into a file @@ -348,10 +352,10 @@ class TestRunner: self.logger.error("There was an error in running the tests in the run_tests function: {e}") # Check if the command executed successfuly if result.returncode or result.returncode == 0: - self.logger.info(f"Test ran successfuly. Test type: {test_type}, test name: {test_name}, test extention: {test_extension}") + self.logger.info(f"Test ran successfuly. Test type: {test_type}, test name: {test_name}, test extension: {' '.join(test_extensions)}") return True, output_file else: - self.logger.error(f"Error making test. Test type: {test_type}, test name: {test_name}, test extention: {test_extension}") + self.logger.error(f"Error making test. Test type: {test_type}, test name: {test_name}, test extension: {' '.join(test_extensions)}") return False, output_file @@ -535,7 +539,7 @@ class TestRunner: md_file.write(f"\n**Total failed tests: {total_number_failures}**") for (test_item, item) in zip(test_list, failed_tests): md_file.write(f"\n\n### {test_item[1]} test") - md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {test_item[2]}\n\n") + md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {' '.join(test_item[2])}\n\n") md_file.write(f"**Failed Tests:**\n") @@ -558,7 +562,7 @@ class TestRunner: md_file.write(f"\n**Total successful tests: {total_number_success}**") for (test_item, item) in zip(test_list, passed_tests): md_file.write(f"\n\n### {test_item[1]} test") - md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {test_item[2]}\n\n") + md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {' '.join(test_item[2])}\n\n") md_file.write(f"\n**Successful Tests:**\n") @@ -682,7 +686,7 @@ def main(): log_file_path = log_path.joinpath("nightly_build.log") previous_cvw_path = Path.home().joinpath(args.path,f"{yesterday}/cvw") # creates the object - folder_manager = FolderManager() + folder_manager = FolderManager(basedir=args.path) # setting the path on where to clone new repositories of cvw folder_manager.create_folders([cvw_path, results_path, log_path]) @@ -691,14 +695,18 @@ def main(): folder_manager.clone_repository(cvw_path, args.repository) # Define tests that we can run + # + # flags are a list + if (args.tests == "all"): + test_list = [["python", "./regression-wally", ["--nightly", "--buildroot"]]] if (args.tests == "nightly"): - test_list = [["python", "regression-wally", "--nightly --buildroot"]] - elif (args.tests == "test"): - test_list = [["python", "regression-wally", ""]] - elif (args.tests == "test_lint"): - test_list = [["bash", "lint-wally", "-nightly"]] + test_list = [["python", "./regression-wally", ["--nightly"]]] + elif (args.tests == "regression"): + test_list = [["python", "./regression-wally", []]] + elif (args.tests == "lint"): + test_list = [["bash", "./lint-wally", ["--nightly"]]] else: - print(f"Error: Invalid test '"+args.test+"' specified") + print(f"Error: Invalid test {args.tests} specified") raise SystemExit ############################################# @@ -765,9 +773,9 @@ def main(): total_failures = [] total_success = [] - for test_type, test_name, test_extension in test_list: + for test_type, test_name, test_extensions in test_list: - check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_extension=test_extension) + check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_extensions=test_extensions) try: if check: # this checks if the test actually ran successfuly output_log_list.append(output_location) From 0830cbb8d151e73135203017348671c376678939 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 02:14:37 -0700 Subject: [PATCH 172/232] README formatting updates --- README.md | 204 +++++++++++++++++++++++++++++++----------------------- 1 file changed, 119 insertions(+), 85 deletions(-) diff --git a/README.md b/README.md index e4f7602e2..631949463 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,5 @@ ![Installation CI](https://github.com/jordancarlin/cvw/actions/workflows/install.yml/badge.svg?branch=main) + # core-v-wally Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores. @@ -15,62 +16,66 @@ Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibi New users may wish to do the following setup to access the server via a GUI and use a text editor. - Git started with Git configuration and authentication: B.1 (replace with your name and email) - $ git config --global user.name "Ben Bitdiddle" - $ git config --global user.email "ben_bitdiddle@wally.edu" - $ git config --global pull.rebase false - Optional: Download and install x2go - A.1.1 - Optional: Download and install VSCode - A.4.2 - Optional: Make sure you can log into your server via x2go and via a terminal - Terminal on Mac, cmd on Windows, xterm on Linux - See A.1 about ssh -Y login from a terminal +- Git started with Git configuration and authentication: B.1 (replace with your name and email) + ```bash + $ git config --global user.name "Ben Bitdiddle" + $ git config --global user.email "ben_bitdiddle@wally.edu" + $ git config --global pull.rebase false + ``` +- Optional: Download and install x2go - A.1.1 +- Optional: Download and install VSCode - A.4.2 +- Optional: Make sure you can log into your server via x2go and via a terminal + - Terminal on Mac, cmd on Windows, xterm on Linux + - See A.1 about ssh -Y login from a terminal Then fork and clone the repo, source setup, make the tests and run regression - If you don't already have a Github account, create one - In a web browser, visit https://github.com/openhwgroup/cvw - In the upper right part of the screen, click on Fork - Create a fork, choosing the owner as your github account - and the repository as cvw. - - On the Linux computer where you will be working, log in - -Clone your fork of the repo. Change `` to your github id. - +1. If you don't already have a Github account, create one +2. In a web browser, visit https://github.com/openhwgroup/cvw +3. In the upper right part of the screen, click on Fork +4. Create a fork, choosing the owner as your github account and the repository as cvw. +5. On the Linux computer where you will be working, log in. +6. Clone your fork of the repo. Change `` to your github id. + ```bash $ git clone --recurse-submodules https://github.com//cvw $ cd cvw $ git remote add upstream https://github.com/openhwgroup/cvw + ``` -If you are installing on a new system without any tools installed, please jump to the next section, Toolchain Installation then come back here. +> [!NOTE] +> If you are installing on a new system without any tools installed, please jump to the next section, [Toolchain Installation](#toolchain-installation-and-configuration-sys-admin), then come back here. -Run the setup script to update your `PATH` and activate the python virtual environment. +7. Run the setup script to update your `PATH` and activate the python virtual environment. + ```bash $ source ./setup.sh + ``` -Add the following lines to your `.bashrc` or `.bash_profile` to run the setup script each time you log in. +8. Add the following lines to your `.bashrc` or `.bash_profile` to run the setup script each time you log in. + ```bash if [ -f ~/cvw/setup.sh ]; then source ~/cvw/setup.sh fi + ``` +9. Build the tests and run a regression simulation to prove everything is installed. Building tests may take a while. -Build the tests and run a regression simulation to prove everything is installed. Building tests will take a while. - + ```bash $ make --jobs $ regression-wally + ``` # Toolchain Installation and Configuration (Sys Admin) -This section describes the open source toolchain installation. +> This section describes the open source toolchain installation. ### Compatibility The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9). > [!WARNING] -> Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. - -> [!WARNING] -> Verilator currently fails to simulate correctly on Ubuntu 20.04 LTS and Red Hat/Rocky/AlmaLinux 8. +> - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. +> - Verilator currently fails to simulate correctly on Ubuntu 20.04 LTS and Red Hat/Rocky/AlmaLinux 8. ### Overview The toolchain installation script installs the following tools: @@ -89,21 +94,27 @@ Additionally, Buildroot Linux is built for Wally and linux test-vectors are gene The tools can be installed by running - $ $WALLY/bin/wally-tool-chain-install.sh - +```bash +$ $WALLY/bin/wally-tool-chain-install.sh +``` If this script is run as root or using `sudo`, it will also install all of the prerequisite packages using the system package manager. The default installation directory when run in this manner is `/opt/riscv`. If a user-level installation is desired, the script can instead be run by any user without `sudo` and the installation directory will be `~/riscv`. In this case, the prerequisite packages must first be installed by running - $ sudo $WALLY/bin/wally-package-install.sh +```bash +$ sudo $WALLY/bin/wally-package-install.sh +``` In either case, the installation directory can be overridden by passing the desired directory as the last argument to the installation script. For example, - $ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv +```bash +$ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv +``` See `wally-tool-chain-install.sh` for a detailed description of each component, or to issue the commands one at a time to install on the command line. -**NOTE:** The complete installation process requires ~55 GB of free space. If the `--clean` flag is passed as the first argument to the installation script then the final consumed space is only ~26 GB, but upgrading the tools requires reinstalling from scratch. +> [!NOTE] +> The complete installation process requires ~55 GB of free space. If the `--clean` flag is passed to the installation script then the final consumed space is only ~26 GB, but upgrading the tools will reinstall everything from scratch. ### Configuration `$WALLY/setup.sh` sources `$RISCV/site-setup.sh`. If the toolchain was installed in either of the default locations (`/opt/riscv` or `~/riscv`), `$RISCV` will automatically be set to the correct path when `setup.sh` is run. If a custom installation directory was used, then `$WALLY/setup.sh` must be modified to set the correct path. @@ -112,12 +123,13 @@ See `wally-tool-chain-install.sh` for a detailed description of each component, Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler and VCS installations and license servers. If you only have Questa or VCS, you can still simulate but cannot run logic synthesis. If Questa, VSC, or Design Compiler are already setup on this system then don't set these variables. - export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server - export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server - export QUESTA_HOME=.. # Change this for your path to Questa - export DC_HOME=.. # Change this for your path to Synopsys Design Compiler - export VCS_HOME=.. # Change this for your path to Synopsys VCS - +```bash +export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server +export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server +export QUESTA_HOME=.. # Change this for your path to Questa +export DC_HOME=.. # Change this for your path to Synopsys Design Compiler +export VCS_HOME=.. # Change this for your path to Synopsys VCS +``` # Installing EDA Tools @@ -131,39 +143,48 @@ Although most EDA tools are Linux-friendly, they tend to have issues when not in ### Siemens Questa -Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to -https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. +Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. ### Synopsys Design Compiler (DC) -Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer +Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer. - $ firefox & -Navigate to https://solvnet.synopsys.com -Log in with your institution’s username and password -Click on Downloads, then scroll down to Synopsys Installer -Select the latest version (currently 5.4). Click Download Here, agree, -Click on SynopsysInstaller_v5.4.run -Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want. - Click on all parts and the .spf file, then click Download Files near the top -move the SynopsysInstaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, -move other files into /cad/synopsys/downloads and work as user cad from here on +```bash +$ firefox & +``` - $ cd /cad/synopsys/installer_5.4 - $ ./SynopsysInstaller_v5.4.run - Accept default installation directory - $ ./installer - Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys - When prompted, enter your site ID - Follow prompts +- Navigate to https://solvnet.synopsys.com +- Log in with your institution’s username and password +- Click on Downloads, then scroll down to Synopsys Installer +- Select the latest version (currently 5.4). Click Download Here, agree, +- Click on SynopsysInstaller_v5.4.run +- Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want. +- Click on all parts and the .spf file, then click Download Files near the top +- Move the SynopsysInstaller into `/cad/synopsys/Installer_5.4` with 755 permission for cad, +- move other files into `/cad/synopsys/downloads` and work as user cad from here on + +```bash +$ cd /cad/synopsys/installer_5.4 +$ ./SynopsysInstaller_v5.4.run +``` +- Accept default installation directory +```bash +$ ./installer +``` +- Enter source path as `/cad/synopsys/downloads`, and installation path as `/cad/synopsys` +- When prompted, enter your site ID +- Follow prompts Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. -The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation: +The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify `/import/programs/synopsys` as the target directory, your installation directory structure might look like this after installation: - /import/programs/synopsys/syn/S-2021.06-SP1 +```bash +/import/programs/synopsys/syn/S-2021.06-SP1 +``` -Note: Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. +> [!Note] +> Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. @@ -178,7 +199,7 @@ If you want to add a cronjob you can do the following: 1) Set up the email client `mutt` for your distribution 2) Enter `crontab -e` into a terminal 3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day -``` +```bash 30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com" ``` @@ -186,44 +207,57 @@ If you want to add a cronjob you can do the following: wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file. The general syntax is -wsim [--options] +`wsim [--options]` Parameters and options: - -h, --help show this help message and exit - --sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator - --tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench - --gui, -g Simulate with GUI - --coverage, -c Code & Functional Coverage - --fcov, -f Code & Functional Coverage - --args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs - --vcd, -v Generate testbench.vcd - --lockstep, -l Run ImperasDV lock, step, and compare. - --locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging. - --covlog COVLOG, -d COVLOG Log coverage after n instructions. - --elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension +``` +-h, --help show this help message and exit +--sim {questa,verilator,vcs}, -s {questa,verilator,vcs} Simulator +--tb {testbench,testbench_fp}, -t {testbench,testbench_fp} Testbench +--gui, -g Simulate with GUI +--coverage, -c Code & Functional Coverage +--fcov, -f Code & Functional Coverage +--args ARGS, -a ARGS Optional arguments passed to simulator via $value$plusargs +--vcd, -v Generate testbench.vcd +--lockstep, -l Run ImperasDV lock, step, and compare. +--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG Retired instruction number to be begin logging. +--covlog COVLOG, -d COVLOG Log coverage after n instructions. +--elfext ELFEXT, -e ELFEXT When searching for elf files only includes ones which end in this extension +``` Run basic test with questa - wsim rv64gc arch64i +```bash +wsim rv64gc arch64i +``` Run Questa with gui - wsim rv64gc wally64priv --gui +```bash +wsim rv64gc wally64priv --gui +``` -Run lockstep against ImperasDV with a single elf file in the --gui. Lockstep requires single elf. +Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf. - wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui +```bash +wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui +``` Run lockstep against ImperasDV with a single elf file. Compute coverage. - wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage +```bash +wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage +``` Run lockstep against ImperasDV with directory file. - wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep +```bash +wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep +``` Run lockstep against ImperasDV with directory file and specify specific extension. - wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf - +```bash +wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf +``` From 336a178da0429c43be8904f45b5a49fe2c253e5b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 02:15:45 -0700 Subject: [PATCH 173/232] Fix appendix refs --- README.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 631949463..62a59d5a2 100644 --- a/README.md +++ b/README.md @@ -16,17 +16,17 @@ Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibi New users may wish to do the following setup to access the server via a GUI and use a text editor. -- Git started with Git configuration and authentication: B.1 (replace with your name and email) +- Git started with Git configuration and authentication: C.1 (replace with your name and email) ```bash $ git config --global user.name "Ben Bitdiddle" $ git config --global user.email "ben_bitdiddle@wally.edu" $ git config --global pull.rebase false ``` -- Optional: Download and install x2go - A.1.1 -- Optional: Download and install VSCode - A.4.2 +- Optional: Download and install x2go - B.1.1 +- Optional: Download and install VSCode - B.4.2 - Optional: Make sure you can log into your server via x2go and via a terminal - Terminal on Mac, cmd on Windows, xterm on Linux - - See A.1 about ssh -Y login from a terminal + - See B.1 about ssh -Y login from a terminal Then fork and clone the repo, source setup, make the tests and run regression From 05d86fc6cee21dfbfd20684d24bb9dd5cfac4a7f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 15:08:32 -0700 Subject: [PATCH 174/232] Update fpga README formatting --- fpga/README.md | 52 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/fpga/README.md b/fpga/README.md index 236bc7ddb..249df565b 100644 --- a/fpga/README.md +++ b/fpga/README.md @@ -6,29 +6,39 @@ Wally supports the following boards # Quick Start -## build FPGA +## Build FPGA -`cd generator -make ` +```bash +cd generator +make +``` -example -`make vcu108` +Example: +```bash +make vcu108 +``` ## Make flash card image -ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have. -Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1). +`ls /dev/sd*` or `ls /dev/mmc*` to see which flash card devices you have. +Insert the flash card into the reader and `ls /dev/sd*` or `/dev/mmc*` again. The new device is the one you want to use. Make sure you select the root device (i.e. `/dev/sdb`) not the partition (i.e. `/dev/sdb1`). -`cd $WALLY/linux/sd-card` +```bash +cd $WALLY/linux/sd-card +``` This following script requires root. -`./flash-sd.sh -b -d ` +```bash +./flash-sd.sh -b -d +``` -example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc +Example with vcu108, buildroot installed to `/opt/riscv/buildroot`, and the flash card is device `/dev/sdc` -`./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc` +```bash +./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc +``` -Wait until the the script completes then remove the car. +Wait until the the script completes then remove the card. ## FPGA setup @@ -36,22 +46,26 @@ For the Arty A7 insert the PMOD daughter board into the right most slot and inse For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards. -Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch. +Power on the boards. For Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch. The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead. -`cd $WALLY/fpga/generator -vivado &` +```bash +cd $WALLY/fpga/generator +vivado & +``` -open the design in the current directory WallyFPGA.xpr. +Open the design in the current directory `WallyFPGA.xpr`. Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device. ## Connect to UART -In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. +In another terminal `ls /dev/ttyUSB*`. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times. -`screen /dev/ttyUSB1 115200` +```bash +screen /dev/ttyUSB1 115200 +``` -Swap out the USB1 for USB0 or USB1 as needed. +Swap out the `USB1` for `USB0` or `USB1` as needed. From c69f83224d7e87cbd072f5ab6183faa8de9118e6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 15:18:04 -0700 Subject: [PATCH 175/232] Update SynthDC README formatting --- synthDC/README.md | 85 +++++++++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 43 deletions(-) diff --git a/synthDC/README.md b/synthDC/README.md index 30a98a76b..f0177d369 100644 --- a/synthDC/README.md +++ b/synthDC/README.md @@ -1,42 +1,39 @@ -Synthesis for RISC-V Microprocessor System-on-Chip Design +# Synthesis for RISC-V Microprocessor System-on-Chip Design This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in -scripts/synth.tcl. +`scripts/synth.tcl`. -Example Usage +## Example Usage +```bash make synth DESIGN=wallypipelinedcore FREQ=500 CONFIG=rv32e +``` -environment variables +## Environment Variables -DESIGN - Design provides the name of the output log. Default is synth. +- `DESIGN` + - Design provides the name of the output log. Default is synth. +- `FREQ` + - Frequency in MHz. Default is 500 +- `CONFIG` + - The Wally configuration file. The default is rv32e. + - Examples: rv32e, rv64gc, rv32gc +- `TECH` + - The target standard cell library. The default is sky130. + - Options: + - sky90: skywater 90nm TT 25C + - sky130: skywater 130nm TT 25C +- `SAIFPOWER` + - Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. + - Options: + - 0: switching factor power analysis + - 1: RTL simulation driven power analysis. -FREQ - Frequency in MHz. Default is 500 - -CONFIG - The Wally configuration file. The default is rv32e. - Examples: rv32e, rv64gc, rv32gc - -TECH - The target standard cell library. The default is sky130. - sky90: skywater 90nm TT 25C - sky130: skywater 130nm TT 25C - -SAIFPOWER - Controls if power analysis is driven by switching factor or - RTL modelsim simulation. When enabled requires a saif file - named power.saif. The default is 0. - 0: switching factor power analysis - 1: RTL simulation driven power analysis. - ------ -Extra Tool (PPA) +## Extra Tool (PPA) To run ppa analysis that hones into target frequency, you can type: -python3 ppa/ppaSynth.py from the synthDC directory. This runs a sweep -across all modules listed at the bottom of the ppaSynth.py file. +`python3 ppa/ppaSynth.py` from the synthDC directory. This runs a sweep +across all modules listed at the bottom of the `ppaSynth.py` file. Two options for running the sweep. The first run runs all modules for all techs around a given frequency (i.e., freqs). The second option @@ -44,19 +41,21 @@ will run all designs for the specific module based on bestSynths.csv values. Since the second option is 2nd, it has priority. If the second set of values is commented out, it will run all widths. -WARNING: The first option may runs lots of runs that could expend all -the licenses available for a license. Therefore, care must be taken -to be sure that enough licenses are available for this first option. +**WARNING:** The first option may runs lots of runs that could expend all the licenses available for a license. Therefore, care must be taken to be sure that enough licenses are available for this first option. -##### Run specific syntheses - widths = [8, 16, 32, 64, 128] - modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8'] - techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn'] - freqs = [5000] - synthsToRun = allCombos(widths, modules, techs, freqs) +### Run specific syntheses +```python +widths = [8, 16, 32, 64, 128] +modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8'] +techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn'] +freqs = [5000] +synthsToRun = allCombos(widths, modules, techs, freqs) +``` -##### Run a sweep based on best delay found in existing syntheses - module = 'adder' - width = 32 - tech = 'tsmc28psyn' - synthsToRun = freqSweep(module, width, tech) \ No newline at end of file +### Run a sweep based on best delay found in existing syntheses +```python +module = 'adder' +width = 32 +tech = 'tsmc28psyn' +synthsToRun = freqSweep(module, width, tech) +``` From 1e204f3c1223889dc19a4315cdfae8a30104d662 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 15:21:37 -0700 Subject: [PATCH 176/232] Update testfloat README formatting --- tests/fp/README.md | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/tests/fp/README.md b/tests/fp/README.md index 440f5eea8..c4cd2b97b 100644 --- a/tests/fp/README.md +++ b/tests/fp/README.md @@ -1,7 +1,7 @@ -james.stine@okstate.edu 14 Jan 2022 +james.stine@okstate.edu 14 Jan 2022\ jcarlin@hmc.edu Sept 2024 -## TestFloat for CVW +# TestFloat for CVW The CVW floating point unit is tested using testvectors from the Berkeley TestFloat suite, written originally by John Hauser. @@ -9,7 +9,7 @@ TestFloat and SoftFloat can be found as submodules in the addins directory, and - TestFloat: https://github.com/ucb-bar/berkeley-testfloat-3 - SoftFloat: https://github.com/ucb-bar/berkeley-softfloat-3 -### Compiling SoftFloat/TestFloat and Generating Testvectors +## Compiling SoftFloat/TestFloat and Generating Testvectors The entire testvector generation process can be performed by running make in this directory. @@ -17,7 +17,7 @@ The entire testvector generation process can be performed by running make in thi make --jobs ``` -This compiles SoftFloat for an x86_64 environment in its build/Linux-x86_64-GCC directory using the `SPECIALIZE_TYPE=RISCV` flag to get RISC-V behavior. TestFloat is then compiled in its build/Linux-x86_64-GCC directory using this SoftFloat library. +This compiles SoftFloat for an x86_64 environment in its `build/Linux-x86_64-GCC` directory using the `SPECIALIZE_TYPE=RISCV` flag to get RISC-V behavior. TestFloat is then compiled in its `build/Linux-x86_64-GCC` directory using this SoftFloat library. The Makefile in the vectors subdirectory of this directory is then called to generate testvectors for each rounding mode and operation. It also puts an underscore between each vector instead of a space to allow SystemVerilog `$readmemh` to read correctly. @@ -25,7 +25,7 @@ Testvectors for the combined integer floating-point divider are also generated. Although not needed, a `case.sh` script is included to change the case of the hex output. This is for those that do not like to see hexadecimal capitalized :P. -### Running TestFloat Vectors on Wally +## Running TestFloat Vectors on Wally TestFloat is run using the standard Wally simulation commands. @@ -40,15 +40,15 @@ wsim --tb testbench_fp ``` The choices for `` are as follows: ->cvtint - test integer conversion unit (fcvtint) -cvtfp - test floating-point conversion unit (fcvtfp) -cmp - test comparison unit's LT, LE, EQ opperations (fcmp) -add - test addition -fma - test fma -mul - test mult with fma -sub - test subtraction -div - test division -sqrt - test square root + cvtint - test integer conversion unit (fcvtint) + cvtfp - test floating-point conversion unit (fcvtfp) + cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + add - test addition + fma - test fma + mul - test mult with fma + sub - test subtraction + div - test division + sqrt - test square root Any config that includes floating point support can be used. Each test will test all its vectors for all precisions supported by the given config. From 6d00ae98ea93aaa0cf066addede417bcf222be69 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 15:29:39 -0700 Subject: [PATCH 177/232] Update linux README formatting --- linux/README.MD | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/linux/README.MD b/linux/README.MD index ba7fb8dd4..7eb50dd9f 100644 --- a/linux/README.MD +++ b/linux/README.MD @@ -14,21 +14,27 @@ In order to generate the Linux and boot stage binaries compatible with Wally, Bu To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well. This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). To install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, generate test-vectors for simulation, and install the buildroot package needed to build the SD card driver for Linux, run: - $ make +```bash +$ make +``` This installs to the `$RISCV` directory. Buildroot itself is installed to `$RISCV/buildroot` and the test-vectors are installed to `$RISCV/linux-testvectors`. Optionally, you can override the `BUILDROOT` variable to install a different buildroot source directory. - $ make install BUILDROOT=path/to/buildroot +``` +$ make install BUILDROOT= +``` ## Generating Device Tree Binaries -The device tree files for the various FPGA's Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process. +The device tree files for the various FPGAs Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process. They are built automatically using the main `make` command. To build the device tree binaries (.dtb) from the device tree sources (.dts) separately, we can build all of them at once using: - $ make generate #optionally override BUILDROOT +```bash +$ make generate # optionally override BUILDROOT +``` The .dts files will end up in the `/output/images` folder of your chosen buildroot directory. @@ -38,23 +44,30 @@ By using the `riscv64-unknown-elf-objdump` utility, we can disassemble the binar The disassembled binaries are built automatically using the main `make` command. To create the disassembled binaries separately, run: - $ make disassemble #optionally override BUILDROOT +```bash +$ make disassemble # optionally override BUILDROOT +``` You'll find the resulting disassembled files in `/output/images/disassembly`. ## Generate Memory Files for Linux Boot -Running a linux boot simulation uses a preloaded bootrom and ram memory. We use QEMU to generate these preloaded memory files. The files are output to $RISCV/linux-testvectors. The memory files are generated automatically when using the main `make` command. Alternatively, they can be generated by running +Running a linux boot simulation uses a preloaded bootrom and ram memory. We use QEMU to generate these preloaded memory files. The files are output to `$RISCV/linux-testvectors`. The memory files are generated automatically when using the main `make` command. Alternatively, they can be generated by running - make dumptvs +```bash +$ make dumptvs +``` ## Creating a Bootable SD Card To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `$RISCV` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type: - $ cd sdcard - $ ./flash-sd.sh -b -d +```bash +$ cd sdcard +$ ./flash-sd.sh -b -d +``` for example - - $ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb +```bash +$ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb +``` From 13520b64143f2f8787ae6a14185ffb170c03549d Mon Sep 17 00:00:00 2001 From: Mysterio-Abdullah Date: Thu, 17 Oct 2024 15:31:09 -0700 Subject: [PATCH 178/232] Enabling RV64ZcbZb.a --- config/rv64gc/coverage.svh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 46f9c4f26..5b11b5a22 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -18,4 +18,5 @@ `include "RV64Zca_coverage.svh" `include "RV64Zcb_coverage.svh" `include "RV64ZcbM_coverage.svh" -`include "RV64ZcbZbb_coverage.svh" \ No newline at end of file +`include "RV64ZcbZbb_coverage.svh" +`include "RV64ZcbZba_coverage.svh" \ No newline at end of file From 34ccd5a3912db43b84cdf4c5deb5d22d6612a24f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 17 Oct 2024 15:38:58 -0700 Subject: [PATCH 179/232] Update and combine Linux READMEs --- docs/README-linux.md | 41 ----------------------------------------- linux/README.MD | 6 ++++-- 2 files changed, 4 insertions(+), 43 deletions(-) delete mode 100644 docs/README-linux.md diff --git a/docs/README-linux.md b/docs/README-linux.md deleted file mode 100644 index 63a3f5e2b..000000000 --- a/docs/README-linux.md +++ /dev/null @@ -1,41 +0,0 @@ -### Cross-Compile Buildroot Linux - -Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. - -Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. - -To configure and build Buildroot: - - $ cd $RISCV - $ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now - $ git clone https://github.com/buildroot/buildroot.git - $ cd buildroot - $ git checkout 2021.05 # last tested working version - $ cp -r $WALLY/linux/buildroot-config-src/wally ./board - $ cp ./board/wally/main.config .config - $ make --jobs - -To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. -Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories. - -$ source ~/riscv-wally/setup.sh -$ cd $WALLY/linux/buildroot-scripts -$ make all - -Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. - -### Generate load images for linux boot - -The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors - - cd cvw/linux/testvector-generation - ./genInitMem.sh - -This may require changing file permissions to the linux-testvectors directory. - -### Generate QEMU linux trace - -The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours. - - cd cvw/linux/testvector-generation - ./genTrace.sh diff --git a/linux/README.MD b/linux/README.MD index 7eb50dd9f..b7a031ce6 100644 --- a/linux/README.MD +++ b/linux/README.MD @@ -12,7 +12,9 @@ In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation. -To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well. This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). To install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, generate test-vectors for simulation, and install the buildroot package needed to build the SD card driver for Linux, run: +To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well. + +This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). The main Wally installation script (`bin/wally-tool-chain-install.sh`) runs this by default, so buildroot is likely already setup. Otherwise, to install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, and generate testvectors for simulation run: ```bash $ make @@ -22,7 +24,7 @@ This installs to the `$RISCV` directory. Buildroot itself is installed to `$RISC Optionally, you can override the `BUILDROOT` variable to install a different buildroot source directory. -``` +```bash $ make install BUILDROOT= ``` From 4867a4a3370e0212ef7fd645d3c5684cbcff0b8c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 02:38:53 -0700 Subject: [PATCH 180/232] Use gcc 14 --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index d27e2a392..c722abf81 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -230,9 +230,9 @@ section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. -if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2" "b488ddb"; then +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout b488ddb #&& git pull + git reset --hard && git clean -f && git checkout master && git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then From 4a81327b04f0bf92b7e261c000dc5819fc5166ca Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 08:41:08 -0700 Subject: [PATCH 181/232] Use assembler instead of compiler for coverage tests --- tests/coverage/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index e09d17fa3..232bc053c 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,8 +17,7 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany \ - -nostartfiles -T../../examples/link/link.ld $< + riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< riscv64-unknown-elf-objdump -S -D $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump From 638591e1ddf47f0ecf5282637881b5915c84d35a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 08:42:16 -0700 Subject: [PATCH 182/232] Update coverage test files. Assembler is picky and only accepts # comments and needs newlines --- tests/coverage/WALLY-init-lib.h | 86 ++++---- tests/coverage/amoAccessFault.S | 54 ++--- tests/coverage/csrwrites.S | 54 ++--- tests/coverage/dcache1.S | 16 +- tests/coverage/dcache1.py | 24 +-- tests/coverage/dcache2.S | 64 +++--- tests/coverage/ebu.S | 72 +++---- tests/coverage/floatmisc.S | 18 +- tests/coverage/fpu.S | 138 ++++++------ tests/coverage/fround.S | 2 +- tests/coverage/gshare.S | 101 +++++---- tests/coverage/hptwAccessFault.S | 72 +++---- tests/coverage/ieu.S | 107 +++++----- tests/coverage/ifu.S | 124 +++++------ tests/coverage/ifuCamlineWrite.S | 76 +++---- tests/coverage/lsu.S | 56 ++--- tests/coverage/nonleafpbmtfault.S | 74 +++---- tests/coverage/pmp.S | 340 +++++++++++++++--------------- tests/coverage/pmpadrdecs.S | 12 +- tests/coverage/pmpcbo.S | 14 +- tests/coverage/pmpcfg.S | 16 +- tests/coverage/pmpcfg1.S | 16 +- tests/coverage/pmpcfg2.S | 14 +- tests/coverage/pmppriority.S | 71 +++---- tests/coverage/priv.S | 89 ++++---- tests/coverage/tlbASID.S | 112 +++++----- tests/coverage/tlbGLB.S | 154 +++++++------- tests/coverage/tlbGP.S | 185 ++++++++-------- tests/coverage/tlbKP.S | 66 +++--- tests/coverage/tlbM3.S | 68 +++--- tests/coverage/tlbMP.S | 195 +++++++++-------- tests/coverage/tlbMisaligned.S | 70 +++--- tests/coverage/tlbNAPOT.S | 73 ++++--- tests/coverage/tlbTP.S | 66 +++--- tests/coverage/tlbmisc.S | 107 +++++----- tests/coverage/vm64check.S | 82 +++---- 36 files changed, 1433 insertions(+), 1455 deletions(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 7e2aee771..f03fb6d1c 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -1,32 +1,32 @@ -/////////////////////////////////////////// -// WALLY-init-lib.h -// -// Written: David_Harris@hmc.edu 21 March 2023 -// -// Purpose: Initialize stack, handle interrupts, terminate test case -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# WALLY-init-lib.h +# +# Written: David_Harris@hmc.edu 21 March 2023 +# +# Purpose: Initialize stack, handle interrupts, terminate test case +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate -// The PMP tests are sensitive to the exact addresses in this code, so unfortunately -// modifying anything breaks those tests. +# load code to initalize stack, handle interrupts, terminate +# The PMP tests are sensitive to the exact addresses in this code, so unfortunately +# modifying anything breaks those tests. .section .text.init .global rvtest_entry_point @@ -41,21 +41,21 @@ rvtest_entry_point: csrw medeleg, zero # Don't delegate exceptions # li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again # li t1, 0x02004000 # MTIMECMP in CLINT -# sd t0, 0(t1) - li t0, 0x80 -# li t0, 0x00 +# sd t0, 0(t1) + li t0, 0x80 +# li t0, 0x00 csrw mie, t0 # Enable machine timer interrupt - la t0, topoftrapstack + la t0, topoftrapstack csrw mscratch, t0 # MSCRATCH holds trap stack pointer csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable # set up PMP so user and supervisor mode can access full address space csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF + li t0, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses j main # Call main function in user test program done: - li a0, 4 # argument to finish program + li a0, 4 # argument to finish program ecall # system call to finish program j self_loop # wait forever (not taken) @@ -69,11 +69,11 @@ trap_handler: csrr t1, mtval # And the trap value bgez t0, exception # if msb is clear, it is an exception -interrupt: # must be a timer interrupt +interrupt: # must be a timer interrupt li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again li t1, 0x02004000 # MTIMECMP in CLIN - sd t0, 0(t1) - csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt + sd t0, 0(t1) + csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt li t0, 32 csrc sip, t0 # clears stimer interrupt j trap_return # clean up and return @@ -99,7 +99,7 @@ changeprivilege: trap_return: # return from trap handler csrr t0, mepc # get address of instruction that caused exception - li t1, 0x20000 + li t1, 0x20000 csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped lh t0, 0(t0) # get instruction that caused exception csrc mstatus, t1 # clear mprv bit to restore normal operation @@ -128,7 +128,7 @@ write_tohost: self_loop: j self_loop # wait -// utility routines +# utility routines # put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 setmsb: @@ -139,8 +139,8 @@ setmsb: slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 setmsbdone: ret # return to calller - -.section .tohost + +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -148,7 +148,7 @@ fromhost: .EQU XLEN,64 begin_signature: - .fill 6*(XLEN/32),4,0xdeadbeef # + .fill 6*(XLEN/32),4,0xdeadbeef # end_signature: scratch: @@ -159,7 +159,7 @@ scratch: .space 512 topofstack: # And another stack for the trap handler -.bss +.bss .space 512 topoftrapstack: diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index a8ecf5f0d..45350a0e8 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// hptwAccessFault.S -// -// Written: Rose Thompson rose@rosethompson.net -// -// Purpose: Checks that only Store/AMO access faults are generated on AMO operations -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# hptwAccessFault.S +# +# Written: Rose Thompson rose@rosethompson.net +# +# Purpose: Checks that only Store/AMO access faults are generated on AMO operations +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://#github.com/openhwgroup/cvw +# +# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://#solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################### -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -40,7 +40,7 @@ main: li t2, 2 li t3, 3 amoadd.d t3, t2, (t1) - + fence.I finished: diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index aa3cc438f..d21463ef9 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// csrwrites.S -// -// Written: David_Harris@hmc.edu 21 March 2023 -// -// Purpose: Test writes to CSRs -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# csrwrites.S +# +# Written: David_Harris@hmc.edu 21 March 2023 +# +# Purpose: Test writes to CSRs +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -44,7 +44,7 @@ main: li a0, 1 ecall # enter supervisor mode - li a0, 0 + li a0, 0 ecall # enter user mode li a0, 1 diff --git a/tests/coverage/dcache1.S b/tests/coverage/dcache1.S index 4a9b3de15..7703e4a54 100644 --- a/tests/coverage/dcache1.S +++ b/tests/coverage/dcache1.S @@ -1,9 +1,9 @@ #include "WALLY-init-lib.h" main: - // start way test #1 + # start way test #1 li t0, 0x80100000 .align 6 - // i$ boundary, way test #1 + # i$ boundary, way test #1 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -20,10 +20,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - // start way test #2 + # start way test #2 li t0, 0x80101000 .align 6 - // i$ boundary, way test #2 + # i$ boundary, way test #2 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -40,10 +40,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - // start way test #3 + # start way test #3 li t0, 0x80102000 .align 6 - // i$ boundary, way test #3 + # i$ boundary, way test #3 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -60,10 +60,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - // start way test #4 + # start way test #4 li t0, 0x80103000 .align 6 - // i$ boundary, way test #4 + # i$ boundary, way test #4 .word 0x00000013 .word 0x00000013 .word 0x00000013 diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py index 59259567b..350fe348a 100644 --- a/tests/coverage/dcache1.py +++ b/tests/coverage/dcache1.py @@ -4,23 +4,23 @@ # Written: avercruysse@hmc.edu 18 April 2023 # # Purpose: Test Coverage for D$ -# (For each way, trigger a CacheDataMem write enable while chip enable is low) +# (For each way, trigger a CacheDataMem write enable while chip enable is low) # # A component of the CORE-V-WALLY configurable RISC-V project. -# +# # Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University # # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You # may obtain a copy of the License at # # https://solderpad.org/licenses/SHL-2.1/ # -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions # and limitations under the License. ################################################ @@ -28,7 +28,7 @@ import os test_name = "dcache1.S" dcache_num_ways = 4 -dcache_way_size_in_bytes = 4096 +dcache_way_size_in_bytes = 4096 # warning i$ line size is not currently parameterized. # arbitrary start location of where I send stores to. @@ -44,11 +44,11 @@ def wl(line="", comment=None, fname=test_name): ".align" in line or "# include" in line) else True indent = 6 if instr else 0 - comment = "// " + comment if comment is not None else "" + comment = "# " + comment if comment is not None else "" to_write = " " * indent + line + comment + "\n" f.write(to_write) - + def write_repro_instrs(): """ Assumes that the store location has been fetched to d$, and is in t0. @@ -72,7 +72,7 @@ if __name__ == "__main__": wl(comment="This file is generated by dcache1.py (run that script manually)") wl('#include "WALLY-init-lib.h"') wl('main:') - + # excercise all 4 D$ ways. If they're not all full, it uses the first empty. # So we are sure all 4 ways are exercised. for i in range(dcache_num_ways): @@ -82,5 +82,5 @@ if __name__ == "__main__": wl(comment=f"i$ boundary, way test #{i+1}") write_repro_instrs() mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way. - + wl("j done") diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index 7d5905288..d94a05821 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -1,50 +1,50 @@ -/////////////////////////////////////////// -// dcache2.S -// -// Written: avercruysse@hmc.edu 18 April 2023 -// -// Purpose: Test Coverage for D$ -// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# dcache2.S +# +# Written: avercruysse@hmc.edu 18 April 2023 +# +# Purpose: Test Coverage for D$ +# (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## #include "WALLY-init-lib.h" main: - // way 0 + # way 0 li t0, 0x80100770 sd zero, 0(t0) sd zero, 1(t0) - // way 1 + # way 1 li t0, 0x80101770 sd zero, 0(t0) sd zero, 1(t0) - // way 2 + # way 2 li t0, 0x80102770 - sd zero, 0(t0) + sd zero, 0(t0) sd zero, 1(t0) - // way 3 + # way 3 li t0, 0x80103770 sd zero, 0(t0) sd zero, 1(t0) - + j done diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index fa7927d95..fd888e3d1 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// ebu.S -// -// Written: David_Harris@hmc.edu 21 January 2024 -// -// Purpose: Test coverage for EBU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# ebu.S +# +# Written: David_Harris@hmc.edu 21 January 2024 +# +# Purpose: Test coverage for EBU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -36,22 +36,22 @@ main: csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1 # Page table root address at 0x80010000; SV48 - li t5, 0x9000000000080010 + li t5, 0x9000000000080010 csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - # + # # Tricky case to cover. I$ miss concurrent with DTLB miss. HPTW has to hit the first # access in the cache and miss a later one. Trigger this by doing a load that touches # a page not in the DTLB but where the top-level PTE is already there. Has to happen # near the end of the 16-instruction I$ line. -# +# # Condition Coverage for instance /core/ebu/ebu/ebufsmarb -- # # File ../src/ebu/ebufsmarb.sv @@ -66,8 +66,8 @@ main: # LSUReq N '_1' not hit Hit '_1' # IFUReq N No hits Hit '_0' and '_1' # -# Rows: Hits FEC Target Non-masking condition(s) -# --------- --------- -------------------- ------------------------- +# Rows: Hits FEC Target Non-masking condition(s) +# --------- --------- -------------------- ------------------------- # Row 1: 2 HREADY_0 ((LSUReq ~& IFUReq) && FinalBeatD) # Row 2: 14 HREADY_1 ((LSUReq ~& IFUReq) && FinalBeatD) # Row 3: 1 FinalBeatD_0 ((LSUReq ~& IFUReq) && HREADY) @@ -78,7 +78,7 @@ main: # Row 8: ***0*** IFUReq_1 ((HREADY & FinalBeatD) && LSUReq) - li a0, 0x80000000 + li a0, 0x80000000 li a1, 0x80A00000 j label1 @@ -166,7 +166,7 @@ label1: .align 16 # root Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 @@ -175,7 +175,7 @@ pagetable: .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 - + # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 @@ -260,7 +260,7 @@ pagetable: .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF - + .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF diff --git a/tests/coverage/floatmisc.S b/tests/coverage/floatmisc.S index d91229dac..fc43ecd8a 100644 --- a/tests/coverage/floatmisc.S +++ b/tests/coverage/floatmisc.S @@ -1,12 +1,12 @@ -// debug.S -// David_Harris@hmc.edu 4 February 2023 -// Small code snippets for the purpose of debugging issues -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# debug.S +# David_Harris@hmc.edu 4 February 2023 +# Small code snippets for the purpose of debugging issues +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 .global rvtest_entry_point rvtest_entry_point: lui t0, 0x02 # turn on Floating point and XS - csrs mstatus, t0 + csrs mstatus, t0 la a6, begin_signature la a7, rvtest_data @@ -53,9 +53,9 @@ write_tohost: self_loop: j self_loop # wait - + .align 6 -.section .tohost +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -75,10 +75,10 @@ rvtest_data: .EQU XLEN,64 begin_signature: - .fill 8*(XLEN/32),4,0xdeadbeef # + .fill 8*(XLEN/32),4,0xdeadbeef # end_signature: # Initialize stack with room for 512 bytes .bss .space 512 -topofstack: \ No newline at end of file +topofstack: diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 497ba0207..2767b5fe1 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// fpu.S -// -// Written: David_Harris@hmc.edu 28 March 2023 -// -// Purpose: Test coverage for FPU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# fpu.S +# +# Written: David_Harris@hmc.edu 28 March 2023 +# +# Purpose: Test coverage for FPU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -48,9 +48,9 @@ main: fcvt.h.q fs1, fs0 fcvt.s.q fs1, fs0 # round for now because these tests are excluded from Zfa until rounding is implemented - fround.s fs1, fs0 + fround.s fs1, fs0 froundnx.s fs1, fs0 - fround.d fs1, fs0 + fround.d fs1, fs0 froundnx.d fs1, fs0 fround.h fs1, fs0 froundnx.h fs1, fs0 @@ -120,9 +120,9 @@ main: fcvt.s.l ft0, t0 fcvt.s.lu ft0, t0 - // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc - # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 - // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc + # Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc + # fcvt.h.d ft3, ft0 # Somehow this instruction is taking the route on line 124 + # idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc # fcvt.h.w ft3, a0 # fcvt.w.h a0, ft0 # fcvt.q.w ft3, a0 @@ -131,12 +131,12 @@ main: # half-precision NaN boxing la t0, TestData3 - fld ft2, 0(t0) // bad NaN-boxed number - fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing - fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing + fld ft2, 0(t0) # bad NaN-boxed number + fmadd.h ft1, ft2, ft2, ft2 # Test NaN boxing + fmadd.s ft1, ft2, ft2, ft2 # Test NaN boxing - // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) - // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. + # fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) + # This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. li t0, 0x3F812345 # random value slightly bigger than 1 li t1, 0x3F823456 fmv.w.x ft0, t0 # move int to fp register @@ -146,7 +146,7 @@ main: sd t0, 0(t1) csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE li t1, 0x0200bff8 # read MTIME in CLINT - ld t0, 0(t1) + ld t0, 0(t1) addi t0, t0, 11 li t1, 0x02004000 # MTIMECMP in CLINT sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency @@ -155,44 +155,44 @@ main: csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE # Completing branch coverage in fctrl.sv - .word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011 - .word 0x40000053 // Line 145 All False Test case - illegal instruction? - .word 0xd0400053 // Line 156 All False Test case - illegal instruction? - .word 0xc0400053 // Line 162 All False Test case - illegal instruction? - .word 0xd2400053 // Line 168 All False Test case - illegal instruction? - .word 0xc2400053 // Line 174 All False Test case - illegal instruction? + .word 0x38007553 # Testing the all False case for 119 - funct7 under, op = 101 0011 + .word 0x40000053 # Line 145 All False Test case - illegal instruction? + .word 0xd0400053 # Line 156 All False Test case - illegal instruction? + .word 0xc0400053 # Line 162 All False Test case - illegal instruction? + .word 0xd2400053 # Line 168 All False Test case - illegal instruction? + .word 0xc2400053 # Line 174 All False Test case - illegal instruction? # Increasing conditional coverage in fctrl.sv - .word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to - .word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) - .word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) - .word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. - .word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl. - .word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr - .word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr + .word 0xc5000007 # Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to + .word 0xe0101053 # toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) + .word 0xe0100053 # toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) + .word 0x40D00053 # toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. + .word 0x40300053 # toggling SupportFmt2 to 0 on line 145 in fctrl. + .word 0x42100053 # toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr + .word 0xf0100053 # toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr # Test illegal instructions are detected - .word 0x00000007 // illegal floating-point load (bad Funct3) - .word 0x00000027 // illegal floating-point store (bad Funct3) - .word 0x58F00053 // illegal fsqrt (bad Rs2D) - .word 0x20007053 // illegal fsgnj (bad Funct3) - .word 0x28007053 // illegal fmin/max (bad Funct3) - .word 0xA0007053 // illegal fcmp (bad Funct3) - .word 0xE0007053 // illegal fclass/fmv (bad Funct3) - .word 0xF0007053 // illegal fmv (bad Funct3) - .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) - .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) - .word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D) - .word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D) - .word 0x04000043 // illegal fmadd.h (h not supported) - .word 0xC2800053 // illegal fcvtmod.w.d with rm rne - .word 0xF0101053 // illegal fli with Funct3D not 0 - .word 0xF0400053 // illegal fli with Rs2D not 1 - .word 0x44200053 // illegal instruction for f.cvt.h.h + .word 0x00000007 # illegal floating-point load (bad Funct3) + .word 0x00000027 # illegal floating-point store (bad Funct3) + .word 0x58F00053 # illegal fsqrt (bad Rs2D) + .word 0x20007053 # illegal fsgnj (bad Funct3) + .word 0x28007053 # illegal fmin/max (bad Funct3) + .word 0xA0007053 # illegal fcmp (bad Funct3) + .word 0xE0007053 # illegal fclass/fmv (bad Funct3) + .word 0xF0007053 # illegal fmv (bad Funct3) + .word 0x43007053 # illegal fcvt.d.* (bad Rs2D) + .word 0x42207053 # illegal fcvt.d.* (bad Rs2D[1]) + .word 0xD5F00053 # illegal fcvt.h.* (bad Rs2D) + .word 0xC5F00053 # illegal fcvt.*.h (bad Rs2D) + .word 0x04000043 # illegal fmadd.h (h not supported) + .word 0xC2800053 # illegal fcvtmod.w.d with rm rne + .word 0xF0101053 # illegal fli with Funct3D not 0 + .word 0xF0400053 # illegal fli with Rs2D not 1 + .word 0x44200053 # illegal instruction for f.cvt.h.h - // Test divide by zero with rounding mode toward zero + # Test divide by zero with rounding mode toward zero li t0, 1 - csrw frm, t0 // set rounding mode = 1 + csrw frm, t0 # set rounding mode = 1 li t0, 0x3f800000 fcvt.s.w ft1, t0 fcvt.s.w ft2, zero diff --git a/tests/coverage/fround.S b/tests/coverage/fround.S index 7d469d773..76d4c683c 100644 --- a/tests/coverage/fround.S +++ b/tests/coverage/fround.S @@ -1,4 +1,4 @@ -// fround.s +# fround.s #include "WALLY-init-lib.h" diff --git a/tests/coverage/gshare.S b/tests/coverage/gshare.S index 788b7743d..0b213ba34 100644 --- a/tests/coverage/gshare.S +++ b/tests/coverage/gshare.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// gshare.S -// -// Written: Rose Thompson rose@rosethompson.net -// -// Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection. -// TODO: *** Automate checking prediction accuracy. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# gshare.S +# +# Written: Rose Thompson rose@rosethompson.net +# +# Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection. +# TODO: *** Automate checking prediction accuracy. +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -41,7 +41,7 @@ main: jal ra, global_hist_2_space_test jal ra, global_hist_1_space_test jal ra, global_hist_0_space_test - + fence.I finished: @@ -100,7 +100,7 @@ oneLoopTest5: # instruction addi t3, t3, 1 bne t3, t4, oneLoopTest5 # this branch toggles between taken and not taken. - + ret .section .text @@ -116,10 +116,10 @@ loop_6: # instruction addi t3, t3, 1 addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_6 # this branch toggles between taken and not taken. li t4, 0 j one_6 @@ -129,12 +129,12 @@ zero_6: addi t3, t3, 1 addi t3, t3, 1 add t1, t1, t4 - + one_6: - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 addi t2, t2, -1 bnez t2, loop_6 @@ -153,8 +153,8 @@ loop_4: # instruction addi t3, t3, 1 addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_4 # this branch toggles between taken and not taken. li t4, 0 j one_4 @@ -162,9 +162,9 @@ zero_4: li t4, 1 addi t3, t3, 1 add t1, t1, t4 - + one_4: - addi t3, t3, 1 + addi t3, t3, 1 addi t2, t2, -1 bnez t2, loop_4 @@ -183,8 +183,8 @@ loop_3: # instruction addi t3, t3, 1 addi t3, t3, 1 - addi t3, t3, 1 - addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_3 # this branch toggles between taken and not taken. li t4, 0 j one_3 @@ -192,9 +192,9 @@ zero_3: li t4, 1 addi t3, t3, 1 add t1, t1, t4 - + one_3: - addi t3, t3, 1 + addi t3, t3, 1 addi t2, t2, -1 bnez t2, loop_3 @@ -220,7 +220,7 @@ loop_2: zero_2: li t4, 1 add t1, t1, t4 - + one_2: addi t2, t2, -1 bnez t2, loop_2 @@ -245,13 +245,13 @@ loop_1: zero_1: li t4, 1 add t1, t1, t4 - + one_1: addi t2, t2, -1 bnez t2, loop_1 ret - + .section .text .globl global_hist_0_space_test .type global_hist_0_space_test, @function @@ -269,10 +269,9 @@ loop_0: zero_0: li t4, 1 add t1, t1, t4 - + one_0: addi t2, t2, -1 bnez t2, loop_0 ret - diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index e1a2ea49c..dc7e43dd1 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// hptwAccessFault.S -// -// Written: Rose Thompson rose@rosethompson.net -// -// Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker -// generate access faults. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# hptwAccessFault.S +# +# Written: Rose Thompson rose@rosethompson.net +# +# Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker +# generate access faults. +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -39,20 +39,20 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t5, 0 li t2, 0x1000 - li t0, 0x8000001000 + li t0, 0x8000001000 lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault - add t0, t0, t2 + add t0, t0, t2 sw t1, 0(t0) j jumppoint -jumppoint: +jumppoint: .align 6 # aligns to cache line size sw t1, 0(t0) sw t1, 4(t0) @@ -74,7 +74,7 @@ jumppoint: lw t3, 8(t0) lw t3, 12(t0) lw t3, 16(t0) - + fence.I finished: @@ -84,15 +84,15 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 +pagetable: + .8byte 0x200044C1 .8byte 0x300044C1 # point to invalid region of physical memory .align 12 .8byte 0x00000040200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -138,7 +138,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 7ec318632..252488779 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// ieu.S -// -// Written: David_Harris@hmc.edu 21 March 2023 -// -// Purpose: Test coverage for IEU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# ieu.S +# +# Written: David_Harris@hmc.edu 21 March 2023 +# +# Purpose: Test coverage for IEU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -53,34 +53,34 @@ main: ori x0, x0, 1 ori x0, x0, 2 ori x0, x0, 3 - + # Test illegal instructions are detected - .word 0x80000033 // illegal R-type instruction - .word 0x00007003 // illegal Load instruction - .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 - .word 0x00000000 // illegal instruction - .word 0x0000701B // Illegal IW instruction - .word 0x00004023 // Illegal store instruction - .word 0x0400003B // Illegal RW or MulDivW instruction - .word 0x00007067 // Illegal JALR instruction - .word 0x00002063 // Illegal branch instruction - .word 0x60F01013 // Illegal BMU sign extend / count instruction - .word 0x60801013 // Illegal BMU sign extend / count instruction - .word 0x60301013 // Illegal BMU sign extend / count instruction - .word 0x6BF05013 // Illegal BMU similar to rev8 - .word 0x69805013 // Illegal BMU similar to rev8 - .word 0x28F05013 // Illegal BMU similar to or.c - .word 0x60F0101B // Illegal BMU similar to count word - .word 0x6080101B // Illegal BMU similar to count word - .word 0x6030101B // Illegal BMU similar to count word - .word 0x0000202F // Illegal similar to LR - .word 0x1010202F // Illegal similar to LR - .word 0x00402003 // illegal similar to CMO - .word 0x00202003 // illegal similar to CMO - .word 0xFF00302F // illegal Atomic instruction - .word 0xFF00402F // illegal Atomic instruction - .word 0x00000873 // illegal CSR instruction + .word 0x80000033 # illegal R-type instruction + .word 0x00007003 # illegal Load instruction + .word 0x80005013 # illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 + .word 0x00000000 # illegal instruction + .word 0x0000701B # Illegal IW instruction + .word 0x00004023 # Illegal store instruction + .word 0x0400003B # Illegal RW or MulDivW instruction + .word 0x00007067 # Illegal JALR instruction + .word 0x00002063 # Illegal branch instruction + .word 0x60F01013 # Illegal BMU sign extend / count instruction + .word 0x60801013 # Illegal BMU sign extend / count instruction + .word 0x60301013 # Illegal BMU sign extend / count instruction + .word 0x6BF05013 # Illegal BMU similar to rev8 + .word 0x69805013 # Illegal BMU similar to rev8 + .word 0x28F05013 # Illegal BMU similar to or.c + .word 0x60F0101B # Illegal BMU similar to count word + .word 0x6080101B # Illegal BMU similar to count word + .word 0x6030101B # Illegal BMU similar to count word + .word 0x0000202F # Illegal similar to LR + .word 0x1010202F # Illegal similar to LR + .word 0x00402003 # illegal similar to CMO + .word 0x00202003 # illegal similar to CMO + .word 0xFF00302F # illegal Atomic instruction + .word 0xFF00402F # illegal Atomic instruction + .word 0x00000873 # illegal CSR instruction # Illegal CMO instructions because envcfg is 0 and system is in user Mode li a0, 0 @@ -100,9 +100,8 @@ main: cbo.inval (x2) cbo.clean (x3) cbo.flush (x1) - + j done - diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 4b085d845..08a527f94 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// ifu.S -// -// Written: sriley@g.hmc.edu 28 March 2023 -// -// Purpose: Test coverage for IFU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# ifu.S +# +# Written: sriley@g.hmc.edu 28 March 2023 +# +# Purpose: Test coverage for IFU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -33,48 +33,48 @@ main: csrs mstatus, t0 # calling compressed floating point load double instruction - //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op - // binary version 0000 0000 0000 0000 0010 0000 0000 0000 + #.hword 0x2000 # CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op + # binary version 0000 0000 0000 0000 0010 0000 0000 0000 mv s0, sp - c.fld fs0, 0(s0) // Previously uncovered instructions - c.fsd fs0, 0(s0) - .hword 0x2002 // c.fldsp fs0, 0 - .hword 0xA002 // c.fsdsp fs0, 0 - .hword 0x9C41 // line 134 Illegal compressed instruction + c.fld fs0, 0(s0) # Previously uncovered instructions + c.fsd fs0, 0(s0) + .hword 0x2002 # c.fldsp fs0, 0 + .hword 0xA002 # c.fsdsp fs0, 0 + .hword 0x9C41 # line 134 Illegal compressed instruction # Zcb coverage tests # could restore assembly language versions when GCC supports Zcb mv s0, sp - #c.lbu s1, 0(s0) // exercise c.lbu - .hword 0x8004 // c.lbu s1, 0(s0) - #c.lh s1, 0(s0) // exercise c.lh - .hword 0x8444 // c.lh s1, 0(s0) - #c.lhu s1, 0(s0) // exercise c.lhu - .hword 0x8404 // c.lhu s1, 0(s0) - #c.sb s1, 0(s0) // exercise c.sb - .hword 0x8804 // c.sb s1, 0(s0) - #c.sh s1, 0(s0) // exercise c.sh - .hword 0x8C04 // c.sh s1, 0(s0) + #c.lbu s1, 0(s0) # exercise c.lbu + .hword 0x8004 # c.lbu s1, 0(s0) + #c.lh s1, 0(s0) # exercise c.lh + .hword 0x8444 # c.lh s1, 0(s0) + #c.lhu s1, 0(s0) # exercise c.lhu + .hword 0x8404 # c.lhu s1, 0(s0) + #c.sb s1, 0(s0) # exercise c.sb + .hword 0x8804 # c.sb s1, 0(s0) + #c.sh s1, 0(s0) # exercise c.sh + .hword 0x8C04 # c.sh s1, 0(s0) - .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction - .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction + .hword 0x8C44 # Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction + .hword 0x9C00 # Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction li s0, 0xFF - # c.zext.b s0 // exercise c.zext.b - .hword 0x9C61 // c.zext.b s0 - # c.sext.b s0 // exercise c.sext.b - .hword 0x9C65 // c.sext.b s0 - # c.zext.h s0 // exercise c.zext.h - .hword 0x9C69 // c.zext.h s0 - # c.sext.h s0 // exercise c.sext.h - .hword 0x9C6D // c.sext.h s0 - # c.zext.w s0 // exercise c.zext.w - .hword 0x9C71 // c.zext.w s0 - # c.not s0 // exercise c.not - .hword 0x9C75 // c.not s0 - - .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else - + # c.zext.b s0 # exercise c.zext.b + .hword 0x9C61 # c.zext.b s0 + # c.sext.b s0 # exercise c.sext.b + .hword 0x9C65 # c.sext.b s0 + # c.zext.h s0 # exercise c.zext.h + .hword 0x9C69 # c.zext.h s0 + # c.sext.h s0 # exercise c.sext.h + .hword 0x9C6D # c.sext.h s0 + # c.zext.w s0 # exercise c.zext.w + .hword 0x9C71 # c.zext.w s0 + # c.not s0 # exercise c.not + .hword 0x9C75 # c.not s0 + + .hword 0x9C7D # Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else + # exercise all the cache ways j way0code @@ -100,6 +100,6 @@ way3code: .align 12 way00code: ret - - + + j done diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index db873dec4..f32ecd97d 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -1,33 +1,33 @@ -/////////////////////////////////////////// -// ifuCamlineWrite.S -// -// Written: Miles Cook and Kevin Box 4/17 -// -// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza -// and Noah Limpert. -// -// Purpose: Test coverage for TLBCamlines in IFU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# ifuCamlineWrite.S +# +# Written: Miles Cook and Kevin Box 4/17 +# +# Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza +# and Noah Limpert. +# +# Purpose: Test coverage for TLBCamlines in IFU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,10 +38,10 @@ main: csrw satp, t5 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t0, 0x80015000 # base addr + li t0, 0x80015000 # base addr li t2, 0 # i = 0 li t3, 33 # Max amount of Loops = 32 @@ -49,9 +49,9 @@ main: loop: bge t2, t3, finished # exit loop if i >= loops li t4, 0x1000 li t1, 0x00008067 # load in jalr - sw t1, 0 (t0) + sw t1, 0 (t0) fence.I - jalr t0 + jalr t0 add t0, t0, t4 addi t2, t2, 1 j loop @@ -63,18 +63,18 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong +pagetable: + .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 - //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 @@ -117,7 +117,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index 0e065010e..f0c0494b7 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -1,37 +1,37 @@ -/////////////////////////////////////////// -// lsu.S -// -// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 -// -// Purpose: Test coverage for lsu -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# lsu.S +# +# Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 +# +# Purpose: Test coverage for lsu +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: - sfence.vma x0, x0 // sfence.vma to assert TLBFlush + sfence.vma x0, x0 # sfence.vma to assert TLBFlush li a0, 0x80000001 # misaligned address amoadd.w t0, a0, (a0) # amo access to misaligned address - j done \ No newline at end of file + j done diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S index 8a580ce02..3ad0b914d 100644 --- a/tests/coverage/nonleafpbmtfault.S +++ b/tests/coverage/nonleafpbmtfault.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// hptwAccessFault.S -// -// Written: Rose Thompson rose@rosethompson.net -// -// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate -// a load or store/amo page fault based on the original access type. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# hptwAccessFault.S +# +# Written: Rose Thompson rose@rosethompson.net +# +# Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate +# a load or store/amo page fault based on the original access type. +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -39,17 +39,17 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t5, 0 li t2, 0x1000 - li t0, 0x8000001000 + li t0, 0x8000001000 lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. - li t1, 0x00008067 - add t0, t0, t2 + li t1, 0x00008067 + add t0, t0, t2 sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table. - + fence.I finished: @@ -59,15 +59,15 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 - .8byte 0x200044C1 +pagetable: + .8byte 0x200044C1 + .8byte 0x200044C1 .align 12 .8byte 0x40000040200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 @@ -113,7 +113,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/pmp.S b/tests/coverage/pmp.S index ab5a60ccc..b4c13527d 100644 --- a/tests/coverage/pmp.S +++ b/tests/coverage/pmp.S @@ -1,20 +1,20 @@ -/////////////////////////////////////////// -// /content/sample_data/PMPConfigregs.S -// Kevin Box, kbox@hmc.edu -// Created 2023-04-09 23:20:54.863039 -/////////////////////////////////////////// +########################################## +# /content/sample_data/PMPConfigregs.S +# Kevin Box, kbox@hmc.edu +# Created 2023-04-09 23:20:54.863039 +########################################## - - - -#include "WALLY-init-lib.h" + + + +#include "WALLY-init-lib.h" main: -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 0 -// -// Configuration +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 0 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |0 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -107,16 +107,16 @@ li t4, 1733894653101739012 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 0 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 1 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 0 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 1 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |1 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -209,16 +209,16 @@ li t4, 1155173425015948313 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 1 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 2 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 1 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 2 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |2 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -311,16 +311,16 @@ li t4, 576491624729942289 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 2 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 3 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 2 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 3 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |3 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -413,16 +413,16 @@ li t4, 7903341188813065 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 3 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 4 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 3 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 4 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |4 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -515,16 +515,16 @@ li t4, 2023255344336144641 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 4 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 5 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 4 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 5 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |5 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -617,16 +617,16 @@ li t4, 1444534086185583003 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 5 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 6 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 5 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 6 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |6 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -719,16 +719,16 @@ li t4, 865844589318216595 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 6 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 7 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 6 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 7 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |7 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -821,16 +821,16 @@ li t4, 295285980948829067 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 7 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 8 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 7 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 8 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |8 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -923,16 +923,16 @@ li t4, 1806234828062034819 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 8 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 9 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 8 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 9 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |9 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1025,16 +1025,16 @@ li t4, 1227514141142123288 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 9 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 10 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 9 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 10 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |10 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1127,16 +1127,16 @@ li t4, 648970879321184272 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 10 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 11 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 10 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 11 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |11 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1229,16 +1229,16 @@ li t4, 115848442837209096 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 11 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 12 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 11 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 12 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |12 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1331,16 +1331,16 @@ li t4, 11210457292615976960 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 12 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 13 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 12 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 13 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |13 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1433,16 +1433,16 @@ li t4, 10631735484709601308 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 13 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 14 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 13 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 14 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |14 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1535,16 +1535,16 @@ li t4, 10052905250353847316 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 14 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// BEGIN Configuration and Testing Starting at Register: 15 -// -// Configuration +# Testing + +# END Configuration and Testing Starting at Register: 14 +###########################################################################################################/ + + +###########################################################################################################/ +# BEGIN Configuration and Testing Starting at Register: 15 +# +# Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |15 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1637,10 +1637,10 @@ li t4, 9446317844957238284 csrw pmpcfg2, t4 -// Testing - -// END Configuration and Testing Starting at Register: 15 -///////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - - j done \ No newline at end of file +# Testing + +# END Configuration and Testing Starting at Register: 15 +###########################################################################################################/ + + + j done diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S index 51ca4d148..5b9992931 100644 --- a/tests/coverage/pmpadrdecs.S +++ b/tests/coverage/pmpadrdecs.S @@ -1,9 +1,9 @@ -// pmpadrdecs -// Liam Chalk, lchalk@hmc.edu, 4/27/2023 -// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] +# pmpadrdecs +# Liam Chalk, lchalk@hmc.edu, 4/27/2023 +# Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: # Writing values to pmpcfg0 to change AdrMode to 2 or 3 # pmpadrdec[0] @@ -19,4 +19,4 @@ main: li t0, 0x1000000000 csrw pmpcfg0, t0 - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S index 2e7eab642..25f16fdaa 100644 --- a/tests/coverage/pmpcbo.S +++ b/tests/coverage/pmpcbo.S @@ -1,15 +1,15 @@ -// pmpcbo.S -// David_Harris@hmc.edu 1/21/24 -// Cover PMP checks of cache management instructions +# pmpcbo.S +# David_Harris@hmc.edu 1/21/24 +# Cover PMP checks of cache management instructions -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: # set up PMP so user and supervisor mode can access partial address space li t0, 0x080F; # li t0, 0x0808; csrw pmpcfg0, t0 # configure PMP0 to TOR RWX and PMP1 to TOR no access - li t0, 0x2003FFFF + li t0, 0x2003FFFF li t1, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses csrw pmpaddr1, t1 # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above @@ -28,4 +28,4 @@ main: cbo.zero (a0) cbo.inval (a0) - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S index bcc8f3950..22cb7a223 100644 --- a/tests/coverage/pmpcfg.S +++ b/tests/coverage/pmpcfg.S @@ -1,11 +1,11 @@ -// pmpcfg part 1 -// Kevin Wan, kewan@hmc.edu, 4/18/2023 -// Liam Chalk, lchalk@hmc.edu, 4/25/2023 -// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. -// See the next part in pmpcfg1.S +# pmpcfg part 1 +# Kevin Wan, kewan@hmc.edu, 4/18/2023 +# Liam Chalk, lchalk@hmc.edu, 4/25/2023 +# locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +# See the next part in pmpcfg1.S -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t0, 0x90000000 csrw pmpaddr0, t0 @@ -103,4 +103,4 @@ main: li t0, 0x8800 csrw pmpcfg0, t0 - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcfg1.S b/tests/coverage/pmpcfg1.S index 96264c55f..b91400ef2 100644 --- a/tests/coverage/pmpcfg1.S +++ b/tests/coverage/pmpcfg1.S @@ -1,12 +1,12 @@ -// another set of pmpcfg tests. A new file is made because pmpcfg register fields are -// locked forever after writing 1 to the lock bit for the first time. +# another set of pmpcfg tests. A new file is made because pmpcfg register fields are +# locked forever after writing 1 to the lock bit for the first time. -// Kevin Wan, kewan@hmc.edu, 4/13/2023 -// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. -// for the other part of the tests, see pmpcfg.S +# Kevin Wan, kewan@hmc.edu, 4/13/2023 +# This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. +# for the other part of the tests, see pmpcfg.S -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t0, 0x800 csrw pmpcfg0, t0 li t0, 0x8000000 @@ -45,4 +45,4 @@ main: - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmpcfg2.S b/tests/coverage/pmpcfg2.S index 5966e3cdc..ffc380438 100644 --- a/tests/coverage/pmpcfg2.S +++ b/tests/coverage/pmpcfg2.S @@ -1,12 +1,12 @@ -// pmpcfg part 3 -// Kevin Wan, kewan@hmc.edu, 4/18/2023 -// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. -// See the next part in pmpcfg1.S +# pmpcfg part 3 +# Kevin Wan, kewan@hmc.edu, 4/18/2023 +# locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +# See the next part in pmpcfg1.S -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: li t0, 0x80 csrw pmpcfg0, t0 - j done \ No newline at end of file + j done diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S index da2f0f40c..ac8e65c63 100644 --- a/tests/coverage/pmppriority.S +++ b/tests/coverage/pmppriority.S @@ -1,92 +1,92 @@ -// pmppriority test cases -// Kevin Wan kewan@hmc.edu 4/27/2023 -// want memory ranges to match: -// 1. only the most significant address and none of the lower ones, -// 2. the most significant address and ANY of the lower ones. +# pmppriority test cases +# Kevin Wan kewan@hmc.edu 4/27/2023 +# want memory ranges to match: +# 1. only the most significant address and none of the lower ones, +# 2. the most significant address and ANY of the lower ones. -#include "WALLY-init-lib.h" -main: +#include "WALLY-init-lib.h" +main: - li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. - csrw pmpaddr0, t1 + li t1, 0x21FFFFFF # start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. + csrw pmpaddr0, t1 csrw pmpaddr1, t1 - csrw pmpaddr2, t1 + csrw pmpaddr2, t1 csrw pmpaddr3, t1 - csrw pmpaddr4, t1 + csrw pmpaddr4, t1 csrw pmpaddr5, t1 csrw pmpaddr6, t1 csrw pmpaddr7, t1 csrw pmpaddr8, t1 csrw pmpaddr9, t1 - csrw pmpaddr10, t1 + csrw pmpaddr10, t1 csrw pmpaddr11, t1 - csrw pmpaddr12, t1 + csrw pmpaddr12, t1 csrw pmpaddr13, t1 csrw pmpaddr14, t1 csrw pmpaddr15, t1 li t0, 0x1F - csrw pmpcfg0, t0 //set to XWR and NAPOT + csrw pmpcfg0, t0 #set to XWR and NAPOT sw zero, 0(sp) li t0, 0x1F00 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F0000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F00000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F0000000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F000000000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x1F00000000000000 - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) - + li t0, 0x1F1F1F1F1F1F1F1F - csrw pmpcfg0, t0 + csrw pmpcfg0, t0 sw zero, 0(sp) li t0, 0x0 @@ -156,6 +156,3 @@ main: j done - - - \ No newline at end of file diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 105a61e11..61417e83e 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// priv.S -// -// Written: David_Harris@hmc.edu 23 March 2023 -// -// Purpose: Test coverage for EBU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# priv.S +# +# Written: David_Harris@hmc.edu 23 March 2023 +# +# Purpose: Test coverage for EBU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -33,26 +33,26 @@ main: csrw sepc, t1 sret sretdone: - addi t2, x0, 42 + addi t2, x0, 42 # switch to user mode - li a0, 0 + li a0, 0 ecall sret #should be treated as illegal instruction mret #mret in user mode and should be illegal # switch to supervisor mode - li a0, 1 + li a0, 1 ecall # Test read to stimecmp fails when MCOUNTEREN_TM is not set li t1, -3 csrw stimecmp, t1 - csrr t0, stimecmp + csrr t0, stimecmp # satp write with mstatus.TVM = 1 - bseti t0, zero, 20 + bseti t0, zero, 20 csrs mstatus, t0 csrw satp, zero @@ -62,7 +62,7 @@ sretdone: ecall # starts in M-mode li t1, -3 csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately - li t0, 2 + li t0, 2 csrs mstatus, t0 # enables sie li t0, 32 csrs sie, t0 # enables sie.stie @@ -111,7 +111,7 @@ sretdone: csrw fcsr, t0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs @@ -125,8 +125,8 @@ sretdone: # Switch to machine mode - li a0, 3 - ecall + li a0, 3 + ecall # Write to MCOUNTINHIBIT CSR csrw mcountinhibit, t0 @@ -149,7 +149,7 @@ sretdone: csrw 2828, t0 csrw 2829, t0 csrw 2830, t0 - csrw 2831, t0 + csrw 2831, t0 csrw 2832, t0 csrw 2833, t0 csrw 2834, t0 @@ -165,7 +165,7 @@ sretdone: csrw 2844, t0 csrw 2845, t0 csrw 2846, t0 - csrw 2847, t0 + csrw 2847, t0 # Testing the HPMCOUNTERM performance counter: reading csrr t0, 2817 @@ -181,7 +181,7 @@ sretdone: csrw 958, t0 - # Testing writes to MTVAL, MCAUSE + # Testing writes to MTVAL, MCAUSE li t0, 0 csrw mtval, t0 csrw mcause, t0 @@ -195,7 +195,7 @@ sretdone: # Test writes to floating point CSRs csrw frm, t0 csrw fflags, t0 - + # CSRC MCOUNTEREN Register # Go to machine mode li a0, 3 @@ -228,7 +228,7 @@ sretdone: li a0, 0 ecall #set status TVM to 0 by writing to bit 20 of mstatus as 0 - #bseti t0, zero, 20 + #bseti t0, zero, 20 sfence.vma zero, zero # Go to supervisor mode @@ -241,7 +241,7 @@ sretdone: ecall # Write to satp when status.TVM is 1 from machine mode - bseti t0, zero, 20 + bseti t0, zero, 20 csrs mstatus, t0 csrw satp, t0 @@ -315,15 +315,12 @@ sretdone: ecall # enter machine mode bseti t0, zero, 17 csrs mstatus, t0 # set MPRV - li t1, 0x00001800 + li t1, 0x00001800 csrs mstatus, t1 # set MPP=3 la t1, finished - csrr t0, mepc + csrr t0, mepc csrw mepc, t1 # set mepc for mret to jump to mret finished: j done - - - diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index 25cf650ca..f7fc56e74 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -1,53 +1,53 @@ -/////////////////////////////////////////// -// tlbASID.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// -// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd -// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbASID.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# +# Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd +# numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 // try making asid = 0. + li t5, 0x9000000000080080 # try making asid = 0. csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t0, 0xC0000000 li t2, 0 # i = 0 - li t5, 0 # j = 0 // now use as a counter for new asid loop + li t5, 0 # j = 0 # now use as a counter for new asid loop li t3, 32 # Max amount of Loops = 32 loop: bge t2, t3, finished # exit loop if i >= loops @@ -56,78 +56,76 @@ loop: bge t2, t3, finished # exit loop if i >= loops sw t1, 0(t0) fence.I jalr t0 - li t5, 0x9001000000080080 // try making asid = 1 + li t5, 0x9001000000080080 # try making asid = 1 csrw satp, t5 jalr t0 - li t5, 0x9000000000080080 // try making asid = 0 + li t5, 0x9000000000080080 # try making asid = 0 csrw satp, t5 li t4, 0x1000 add t0, t0, t4 addi t2, t2, 1 j loop - + finished: j done .data .align 19 # level 3 Page table situated at 0x8008 0000, should point to 8008,1000 -pagetable: +pagetable: .8byte 0x200204C1 - -.align 12 // level 2 page table, contains direction to a gigapage - .8byte 0x0 - .8byte 0x0 - .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208C1 // pointer to next page table entry at 8008 2000 -.align 12 // level 1 page table, points to level 0 page table +.align 12 # level 2 page table, contains direction to a gigapage + .8byte 0x0 + .8byte 0x0 + .8byte 0x200000CF # gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208C1 # pointer to next page table entry at 8008 2000 + +.align 12 # level 1 page table, points to level 0 page table .8byte 0x20020CC1 -.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000CF // access xC000 0000 - .8byte 0x200004CF // access xC000 1000 - .8byte 0x200008CF // access xC000 2000 - .8byte 0x20000CCF // access xC000 3000 +.align 12 # level 0 page table, points to address C000 0000 # FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 + .8byte 0x200000CF # access xC000 0000 + .8byte 0x200004CF # access xC000 1000 + .8byte 0x200008CF # access xC000 2000 + .8byte 0x20000CCF # access xC000 3000 - .8byte 0x200010CF // access xC000 4000 + .8byte 0x200010CF # access xC000 4000 .8byte 0x200014CF .8byte 0x200018CF .8byte 0x20001CCF - .8byte 0x200020CF // access xC000 8000 + .8byte 0x200020CF # access xC000 8000 .8byte 0x200024CF .8byte 0x200028CF .8byte 0x20002CCF - .8byte 0x200030CF // access xC000 C000 + .8byte 0x200030CF # access xC000 C000 .8byte 0x200034CF .8byte 0x200038CF .8byte 0x20003CCF - .8byte 0x200040CF // access xC001 0000 + .8byte 0x200040CF # access xC001 0000 .8byte 0x200044CF .8byte 0x200048CF .8byte 0x20004CCF - .8byte 0x200050CF // access xC001 4000 + .8byte 0x200050CF # access xC001 4000 .8byte 0x200054CF .8byte 0x200058CF .8byte 0x20005CCF - .8byte 0x200060CF // access xC001 8000 + .8byte 0x200060CF # access xC001 8000 .8byte 0x200064CF .8byte 0x200068CF .8byte 0x20006CCF - .8byte 0x200070CF // access xC001 C000 + .8byte 0x200070CF # access xC001 C000 .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - .8byte 0x200080CF // access xC002 0000 + .8byte 0x200080CF # access xC002 0000 .8byte 0x200084CF .8byte 0x200088CF .8byte 0x20008CCF - - diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index de1541610..523b02718 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -1,40 +1,40 @@ -/////////////////////////////////////////// -// tlbGLB.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// Modified: kevin.j.thomas@okstate.edu May/4/20203 -// -// Purpose: Coverage for the Page Table Entry Global flag check. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbGLB.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# Modified: kevin.j.thomas@okstate.edu May/4/20203 +# +# Purpose: Coverage for the Page Table Entry Global flag check. +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 // try making asid = 0. + li t5, 0x9000000000080080 # try making asid = 0. csrw satp, t5 # switch to supervisor mode @@ -42,39 +42,39 @@ main: ecall li t5, 0 # j = 0, run nASID only once - li t3, 32 //Max amount of Loops = 32 - li t4, 0x1000 //offset between addressses. - li t1, 0x00008067 //load in jalr x0 x1 0 instruction to be stored + li t3, 32 #Max amount of Loops = 32 + li t4, 0x1000 #offset between addressses. + li t1, 0x00008067 #load in jalr x0 x1 0 instruction to be stored setup: - li t0, 0xC0000000 //starting address + li t0, 0xC0000000 #starting address li t2, 0 # i = 0 - beq t5, zero, loop //jump to first loop + beq t5, zero, loop #jump to first loop loop2: #jump to each of the addresses in different address space bge t2, t3, done - jalr t0 //jump to instruction at the virtual address - add t0, t0, t4 //change address for next loop - addi t2, t2, 1 //keep track of number of loops ran + jalr t0 #jump to instruction at the virtual address + add t0, t0, t4 #change address for next loop + addi t2, t2, 1 #keep track of number of loops ran j loop2 loop: #store jalr across memory bge t2, t3, nASID # exit loop if i >= loops - sw t1, 0(t0) //stores this jalr in the virtual address - fence.I //invalidate instruction cache - jalr t0 //jump to instruction at the virtual address - add t0, t0, t4 //change address for next loop - addi t2, t2, 1 //keep track of number of loops ran + sw t1, 0(t0) #stores this jalr in the virtual address + fence.I #invalidate instruction cache + jalr t0 #jump to instruction at the virtual address + add t0, t0, t4 #change address for next loop + addi t2, t2, 1 #keep track of number of loops ran j loop nASID: #swap to different address space -> jump to each address - li a0, 3 //swap to machine mode + li a0, 3 #swap to machine mode ecall - li t5, 0x9000100000080080 //swap to address space 1 from 0 + li t5, 0x9000100000080080 #swap to address space 1 from 0 csrw satp, t5 - li a0, 1 // change back to supervisor mode. + li a0, 1 # change back to supervisor mode. ecall - li t5, 1 //flag for finished after loops + li t5, 1 #flag for finished after loops j setup @@ -82,104 +82,100 @@ nASID: #swap to different address space -> jump to each address .data .align 19 # level 3 Page table situated at 0x8008 0000, should point to 8008,1000 -pagetable: +pagetable: .8byte 0x200204C1 - -.align 12 // level 2 page table, contains direction to a gigapageg - .8byte 0x0 - .8byte 0x0 - .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208E1 // pointer to next page table entry at 8008 2000 -.align 12 // level 1 page table, points to level 0 page table +.align 12 # level 2 page table, contains direction to a gigapageg + .8byte 0x0 + .8byte 0x0 + .8byte 0x200000EF # gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208E1 # pointer to next page table entry at 8008 2000 + +.align 12 # level 1 page table, points to level 0 page table .8byte 0x20020CE1 -.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000EF // access xC000 0000 - .8byte 0x200004EF // access xC000 1000 - .8byte 0x200008EF // access xC000 2000 - .8byte 0x20000CEF // access xC000 3000 +.align 12 # level 0 page table, points to address C000 0000 # FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 + .8byte 0x200000EF # access xC000 0000 + .8byte 0x200004EF # access xC000 1000 + .8byte 0x200008EF # access xC000 2000 + .8byte 0x20000CEF # access xC000 3000 - .8byte 0x200010EF // access xC000 4000 + .8byte 0x200010EF # access xC000 4000 .8byte 0x200014EF .8byte 0x200018EF .8byte 0x20001CEF - .8byte 0x200020EF // access xC000 8000 + .8byte 0x200020EF # access xC000 8000 .8byte 0x200024EF .8byte 0x200028EF .8byte 0x20002CEF - .8byte 0x200030EF // access xC000 C000 + .8byte 0x200030EF # access xC000 C000 .8byte 0x200034EF .8byte 0x200038EF .8byte 0x20003CEF - .8byte 0x200040EF // access xC001 0000 + .8byte 0x200040EF # access xC001 0000 .8byte 0x200044EF .8byte 0x200048EF .8byte 0x20004CEF - .8byte 0x200050EF // access xC001 4000 + .8byte 0x200050EF # access xC001 4000 .8byte 0x200054EF .8byte 0x200058EF .8byte 0x20005CEF - .8byte 0x200060EF // access xC001 8000 + .8byte 0x200060EF # access xC001 8000 .8byte 0x200064EF .8byte 0x200068EF .8byte 0x20006CEF - .8byte 0x200070EF // access xC001 C000 + .8byte 0x200070EF # access xC001 C000 .8byte 0x200074eF .8byte 0x200078EF .8byte 0x20007CEF - .8byte 0x200080EF // access xC002 0000 + .8byte 0x200080EF # access xC002 0000 .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF - .8byte 0x200010EF // access xC000 4000 + .8byte 0x200010EF # access xC000 4000 .8byte 0x200014EF .8byte 0x200018EF .8byte 0x20001CEF - .8byte 0x200020EF // access xC000 8000 + .8byte 0x200020EF # access xC000 8000 .8byte 0x200024EF .8byte 0x200028EF .8byte 0x20002CEF - .8byte 0x200030EF // access xC000 C000 + .8byte 0x200030EF # access xC000 C000 .8byte 0x200034EF .8byte 0x200038EF .8byte 0x20003CEF - .8byte 0x200040EF // access xC001 0000 + .8byte 0x200040EF # access xC001 0000 .8byte 0x200044EF .8byte 0x200048EF .8byte 0x20004CEF - .8byte 0x200050EF // access xC001 4000 + .8byte 0x200050EF # access xC001 4000 .8byte 0x200054EF .8byte 0x200058EF .8byte 0x20005CEF - .8byte 0x200060EF // access xC001 8000 + .8byte 0x200060EF # access xC001 8000 .8byte 0x200064EF .8byte 0x200068EF .8byte 0x20006CEF - .8byte 0x200070EF // access xC001 C000 + .8byte 0x200070EF # access xC001 C000 .8byte 0x200074eF .8byte 0x200078EF .8byte 0x20007CEF - .8byte 0x200080EF // access xC002 0000 + .8byte 0x200080EF # access xC002 0000 .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF - - - - \ No newline at end of file diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index bbdb703b4..58295195b 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// tlbGP.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// -// Purpose: Create Page tables and access gigapages -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbGP.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# +# Purpose: Create Page tables and access gigapages +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,11 +38,11 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t5, 0 - li t0, 0xC0200000 // go to first gigapage - li t4, 0x40000000 // put this outside the loop. + li t5, 0 + li t0, 0xC0200000 # go to first gigapage + li t4, 0x40000000 # put this outside the loop. li t2, 0 # i = 0 li t3, 64 # Max amount of Loops = 16 @@ -63,97 +63,92 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 -.align 12 - .8byte 0x000000CF //8000 0000 +.align 12 + .8byte 0x000000CF #8000 0000 .8byte 0x100000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF .8byte 0x200000CF .8byte 0x200000CF - .8byte 0x200000CF - .8byte 0x200000CF - - - - - + .8byte 0x200000CF + .8byte 0x200000CF diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 4382673ea..1881f305e 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// lsu_test.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// -// Purpose: Test coverage for LSU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# lsu_test.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# +# Purpose: Test coverage for LSU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,7 +38,7 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t0, 0x80015000 @@ -60,18 +60,18 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong +pagetable: + .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 - //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 @@ -114,7 +114,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index eba37ae99..2cc6b4537 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// tlbKP.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// -// Purpose: Test coverage for LSU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbKP.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# +# Purpose: Test coverage for LSU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,7 +38,7 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t0, 0x1000 @@ -57,7 +57,7 @@ loop: bge t2, t3, interim # exit loop if i >= loops interim: li t0, 0xFFFFFFFF000 li t2, 0 # i = 0 - + loop2:bge t2, t3, finished # exit loop if i >= loops lw t1, 0(t0) @@ -72,18 +72,18 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong +pagetable: + .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 - //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 @@ -126,7 +126,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index f6dc4c597..72f4af273 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// tlbMP.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// -// Purpose: Test coverage for LSU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbMP.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# +# Purpose: Test coverage for LSU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,12 +38,12 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t5, 0 - li t0, 0x84000000 // go to first megapage - li t4, 0x200000 // put this outside the loop. + li t5, 0 + li t0, 0x84000000 # go to first megapage + li t4, 0x200000 # put this outside the loop. li t2, 0 # i = 0 li t3, 32 # Max amount of Loops = 16 @@ -63,102 +63,102 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 .align 12 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - -.align 12 // megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) - .8byte 0x200000CF // access 8000,0000 - .8byte 0x200800CF // access 8020,0000 - .8byte 0x201000CF // acesss 8040,0000 - .8byte 0x201800CF // acesss 8060,0000 +.align 12 # megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) - .8byte 0x202000CF // access 8080,0000 - .8byte 0x202800CF // access 80A0,0000 - .8byte 0x203000CF // access 80C0,0000 - .8byte 0x203800CF // access 80E0,0000 + .8byte 0x200000CF # access 8000,0000 + .8byte 0x200800CF # access 8020,0000 + .8byte 0x201000CF # acesss 8040,0000 + .8byte 0x201800CF # acesss 8060,0000 - .8byte 0x204000CF // access 8100,0000 - .8byte 0x204800CF - .8byte 0x205000CF - .8byte 0x205800CF + .8byte 0x202000CF # access 8080,0000 + .8byte 0x202800CF # access 80A0,0000 + .8byte 0x203000CF # access 80C0,0000 + .8byte 0x203800CF # access 80E0,0000 - .8byte 0x206000CF // access 8180,0000 - .8byte 0x206800CF - .8byte 0x207000CF - .8byte 0x207800CF + .8byte 0x204000CF # access 8100,0000 + .8byte 0x204800CF + .8byte 0x205000CF + .8byte 0x205800CF - .8byte 0x208000CF // access 8200,0000 - .8byte 0x208800CF - .8byte 0x209000CF - .8byte 0x209800CF + .8byte 0x206000CF # access 8180,0000 + .8byte 0x206800CF + .8byte 0x207000CF + .8byte 0x207800CF - .8byte 0x20A000CF // access 8280,0000 - .8byte 0x20A800CF - .8byte 0x20B000CF - .8byte 0x20B800CF + .8byte 0x208000CF # access 8200,0000 + .8byte 0x208800CF + .8byte 0x209000CF + .8byte 0x209800CF - .8byte 0x20C000CF // access 8300,0000 - .8byte 0x20C800CF - .8byte 0x20D000CF + .8byte 0x20A000CF # access 8280,0000 + .8byte 0x20A800CF + .8byte 0x20B000CF + .8byte 0x20B800CF + + .8byte 0x20C000CF # access 8300,0000 + .8byte 0x20C800CF + .8byte 0x20D000CF .8byte 0x20D800CF - .8byte 0x20E000CF // access 8380,0000 - .8byte 0x20E800CF - .8byte 0x20F000CF + .8byte 0x20E000CF # access 8380,0000 + .8byte 0x20E800CF + .8byte 0x20F000CF .8byte 0x20F800CF - .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME. - .8byte 0x200800CF // access 8020,0000 - .8byte 0x201000CF // acesss 8040,0000 - .8byte 0x201800CF // acesss 8060,0000 + .8byte 0x200000CF # access 8000,0000 I AM REPEATING PTE TO SAVE TIME. + .8byte 0x200800CF # access 8020,0000 + .8byte 0x201000CF # acesss 8040,0000 + .8byte 0x201800CF # acesss 8060,0000 - .8byte 0x202000CF // access 8080,0000 - .8byte 0x202800CF // access 80A0,0000 - .8byte 0x203000CF // access 80C0,0000 - .8byte 0x203800CF // access 80E0,0000 + .8byte 0x202000CF # access 8080,0000 + .8byte 0x202800CF # access 80A0,0000 + .8byte 0x203000CF # access 80C0,0000 + .8byte 0x203800CF # access 80E0,0000 - .8byte 0x204000CF // access 8100,0000 - .8byte 0x204800CF - .8byte 0x205000CF - .8byte 0x205800CF + .8byte 0x204000CF # access 8100,0000 + .8byte 0x204800CF + .8byte 0x205000CF + .8byte 0x205800CF - .8byte 0x206000CF // access 8180,0000 - .8byte 0x206800CF - .8byte 0x207000CF - .8byte 0x207800CF + .8byte 0x206000CF # access 8180,0000 + .8byte 0x206800CF + .8byte 0x207000CF + .8byte 0x207800CF - .8byte 0x208000CF // access 8200,0000 - .8byte 0x208800CF - .8byte 0x209000CF - .8byte 0x209800CF + .8byte 0x208000CF # access 8200,0000 + .8byte 0x208800CF + .8byte 0x209000CF + .8byte 0x209800CF - .8byte 0x20A000CF // access 8280,0000 - .8byte 0x20A800CF - .8byte 0x20B000CF - .8byte 0x20B800CF + .8byte 0x20A000CF # access 8280,0000 + .8byte 0x20A800CF + .8byte 0x20B000CF + .8byte 0x20B800CF - .8byte 0x20C000CF // access 8300,0000 - .8byte 0x20C800CF - .8byte 0x20D000CF + .8byte 0x20C000CF # access 8300,0000 + .8byte 0x20C800CF + .8byte 0x20D000CF .8byte 0x20D800CF - .8byte 0x20E000CF // access 8380,0000 - .8byte 0x20E800CF - .8byte 0x20F000CF + .8byte 0x20E000CF # access 8380,0000 + .8byte 0x20E800CF + .8byte 0x20F000CF .8byte 0x20F800CF .8byte 0x20004CC1 - // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF - // point to ... + # Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF + # point to ... -.align 12 // should start at 84000000 +.align 12 # should start at 84000000 .8byte 0x210000CF .8byte 0x210004CF .8byte 0x210008CF @@ -198,4 +198,3 @@ pagetable: .8byte 0x210074CF .8byte 0x210078CF .8byte 0x21007CCF - diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S index e683c9a86..6c72a6be8 100644 --- a/tests/coverage/tlbMisaligned.S +++ b/tests/coverage/tlbMisaligned.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// tlbMisaligned.S -// -// Written: Rose Thompson rose@rosethompson.net -// -// Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbMisaligned.S +# +# Written: Rose Thompson rose@rosethompson.net +# +# Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -42,12 +42,12 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t5, 0 li t2, 0x1000 - li t0, 0x1000 // go to first gigapage - li t4, 0x40000000 // put this outside the loop. + li t0, 0x1000 # go to first gigapage + li t4, 0x40000000 # put this outside the loop. lw t1, 1(t0) # load a misaligned aligned cached address li t1, 0x00008067 #load in jalr @@ -58,7 +58,7 @@ main: lw t1, 1(t0) # load a misaligned aligned uncached address should fault add t0, t0, t2 # go to the next page sw t1, 1(t0) # store to another misaligned uncached address should falt. - + fence.I finished: @@ -68,18 +68,18 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 +pagetable: + .8byte 0x200044C1 .align 12 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 .8byte 0x00000000200048C1 - + .align 12 .8byte 0x0000000020004CC1 - //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 @@ -122,7 +122,7 @@ pagetable: .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - + .8byte 0x200080CF .8byte 0x200084CF .8byte 0x200088CF diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 508eb057c..68fb08d31 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -1,32 +1,32 @@ -/////////////////////////////////////////// -// tlbNAPOT.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages -// -// Purpose: Test coverage for LSU NAPOT -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbNAPOT.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages +# +# Purpose: Test coverage for LSU NAPOT +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -36,13 +36,13 @@ main: slli t5, t5, 62 csrs menvcfg, t5 # Page table root address at 0x80010000; SV48 - li t5, 0x9000000000080010 + li t5, 0x9000000000080010 csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall li t4, 0x200000 # address step size @@ -90,7 +90,7 @@ finished: jr a1 changetoipfhandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, ipf_handler csrw mtvec, a0 # point to new handler @@ -99,7 +99,7 @@ changetoipfhandler: ret changetodefaulthandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, trap_handler csrw mtvec, a0 # point to new handler @@ -137,8 +137,8 @@ ipf: .align 16 # root Page table situated at 0x80010000 -pagetable: - .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong +pagetable: + .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong # next page table at 0x80011000 .align 12 @@ -146,7 +146,7 @@ pagetable: .8byte 0x00000000200058C1 # gigapage at 0x40000000 used for non-NAPOT with PPN bit 3 set .8byte 0x00000000200048C1 # gigapage at 0x80000000 used for testing NAPOT huge pages .8byte 0x00000000200050C1 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN - + # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 @@ -231,7 +231,7 @@ pagetable: .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF - + .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF @@ -437,4 +437,3 @@ pagetable: .8byte 0x00000000200060CF .8byte 0x000000002000A0CF .8byte 0x000000002000E0CF - diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index f4b0a142e..45f751745 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -1,31 +1,31 @@ -/////////////////////////////////////////// -// tlbTP.S -// -// Written: mmendozamanriquez@hmc.edu 4 April 2023 -// nlimpert@hmc.edu -// -// Purpose: Test coverage for LSU -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbTP.S +# +# Written: mmendozamanriquez@hmc.edu 4 April 2023 +# nlimpert@hmc.edu +# +# Purpose: Test coverage for LSU +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,11 +38,11 @@ main: # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall - li t5, 0 - li t0, 0x80000000 // go to first gigapage - li t4, 0x8000000000 // put this outside the loop. + li t5, 0 + li t0, 0x80000000 # go to first gigapage + li t4, 0x8000000000 # put this outside the loop. li t2, 0 # i = 0 li t3, 64 # run through 64 PTEs @@ -63,7 +63,7 @@ finished: .align 16 # Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x0CF .8byte 0x0CF .8byte 0x0CF @@ -142,4 +142,4 @@ pagetable: .8byte 0x0CF .8byte 0x0CF .8byte 0x0CF - .8byte 0x0CF \ No newline at end of file + .8byte 0x0CF diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index f64645689..d47678dbd 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -1,30 +1,30 @@ -/////////////////////////////////////////// -// tlbmisc.S -// -// Written David_Harris@hmc.edu 1/1/24 -// -// Purpose: Test coverage for other TLB issues -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# tlbmisc.S +# +# Written David_Harris@hmc.edu 1/1/24 +# +# Purpose: Test coverage for other TLB issues +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// load code to initalize stack, handle interrupts, terminate +# load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -38,21 +38,21 @@ main: # store ret instruction in case we jump to an address mapping to 80000000 li t0, 0x80000000 li t5, 0x8082 # return instruction opcode - sw t5, 0(t0) + sw t5, 0(t0) fence.i - # Test not being able to write illegal SATP mode - li t5, 0xA000000000080010 + # Test not being able to write illegal SATP mode + li t5, 0xA000000000080010 csrw satp, t5 # Page table root address at 0x80010000; SV48 - li t5, 0x9000000000080010 + li t5, 0x9000000000080010 csrw satp, t5 # sfence.vma x0, x0 # switch to supervisor mode - li a0, 1 + li a0, 1 ecall # Instruction fetch from misaligned pages @@ -65,27 +65,27 @@ main: jalr ra, t0 # jump to misaligned megapage li t0, 0x7FFFFFFF80000000 - + jalr ra, t0 # jump to page with UpperBitsUnequal li t0, 0x0000000080C00000 jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE - - # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE, + + # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE, li a0, 3 ecall # switch to machine mode li t0, 1 - slli t0, t0, 61 + slli t0, t0, 61 csrs menvcfg, t0 # set menvcfg.ADUE - li a0, 1 + li a0, 1 ecall # switch back to supervisor mode li t0, 0x0000000080E00000 jalr ra, t0 # jump to page without accessed bit yet set li a0, 3 ecall # switch to machine mode li t0, 1 - slli t0, t0, 61 + slli t0, t0, 61 csrc menvcfg, t0 # clear menvcfg.ADUE - li a0, 1 + li a0, 1 ecall # switch back to supervisor mode # exercise malformed PBMT pages @@ -147,9 +147,9 @@ ConcurrentICacheMissDTLBMiss: # jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0 li t0, 0x80805000 - jalr ra, t0 + jalr ra, t0 li t0, 0x80807000 # again, triggering setting access bit - jalr ra, t0 + jalr ra, t0 # atomic access to uncachable memory #li t0, 0x80806000 @@ -168,7 +168,7 @@ ConcurrentICacheMissDTLBMiss: jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0 # Load and AMO operation on page table entry that causes access fault - li t0, 0x81000000 + li t0, 0x81000000 lw t1, 0(t0) sfence.vma amoadd.w t0, t0, 0(t0) @@ -190,7 +190,7 @@ ConcurrentICacheMissDTLBMiss: lw t1, 0(t0) # AMO operation on page table entry that causes page fault due to malformed PBMT - li t0, 0x81200000 + li t0, 0x81200000 jalr t0 # Attempt to fetch instruction from address causing faulty page walk lw t1, 0(t0) sfence.vma @@ -198,10 +198,10 @@ ConcurrentICacheMissDTLBMiss: # point top-level page table to an illegal address and verify it faults li t0, 0x9000000000070000 # trap handler at non-existing memory location - csrw satp, t0 # should cause trap + csrw satp, t0 # should cause trap sfence.vma nop - + # change back to default trap handler after checking everything that might cause an instruction page fault jal changetodefaulthandler @@ -263,7 +263,7 @@ ConcurrentICacheMissDTLBMiss: ecall - + # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry @@ -274,7 +274,7 @@ backandforth: ret changetoipfhandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, ipf_handler csrw mtvec, a0 # point to new handler @@ -283,7 +283,7 @@ changetoipfhandler: ret changetodefaulthandler: - li a0, 3 + li a0, 3 ecall # switch to machine mode la a0, trap_handler csrw mtvec, a0 # point to new handler @@ -301,8 +301,8 @@ ipf_handler: csrrw tp, mscratch, tp # swap MSCRATCH and tp sd t0, 0(tp) # Save t0 and t1 on the stack sd t1, -8(tp) - li t5, 0x9000000000080010 - csrw satp, t5 # make sure we are pointing to the root page table + li t5, 0x9000000000080010 + csrw satp, t5 # make sure we are pointing to the root page table csrr t0, mcause # Check the cause li t1, 8 # is it an ecall trap? andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 @@ -329,7 +329,7 @@ fixsatptraphandler: .align 16 # root Page table situated at 0x80010000 -pagetable: +pagetable: .8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000 @@ -345,9 +345,9 @@ pagetable: .8byte 0x0 .8byte 0x0 .8byte 0x0 -SpecialPage: +SpecialPage: .8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1 - + # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 @@ -429,7 +429,7 @@ SpecialPage: .8byte 0x80000000200060CF .8byte 0x80000000200060CF .8byte 0x80000000200060CF - + .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF .8byte 0x800000002000A0CF @@ -475,4 +475,3 @@ SpecialPage: .8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT .8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA - diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 2e03a4e1a..1b8d73aff 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -1,34 +1,34 @@ -/////////////////////////////////////////// -// vm64check.S -// -// Written: David_Harris@hmc.edu 7 April 2023 -// -// Purpose: vm64check coverage -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// https://github.com/openhwgroup/cvw -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// +########################################## +# vm64check.S +# +# Written: David_Harris@hmc.edu 7 April 2023 +# +# Purpose: vm64check coverage +# +# A component of the CORE-V-WALLY configurable RISC-V project. +# https://github.com/openhwgroup/cvw +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +############################################################################################## -// Cover IMMU vm64check block by jumping to illegal virtual addresses -// Need a nonstandard trap handler to deal with returns from theses jumps -// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); - // assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); - // assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; +# Cover IMMU vm64check block by jumping to illegal virtual addresses +# Need a nonstandard trap handler to deal with returns from theses jumps +# assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); + # assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); + # assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; .section .text.init .global rvtest_entry_point @@ -41,15 +41,15 @@ rvtest_entry_point: csrw mtvec, t0 # Initialize MTVEC to trap_handler # set up PMP so user and supervisor mode can access full address space csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF + li t0, 0xFFFFFFFF csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses - + # SATP in non-39 mode csrw satp, zero - // vm64check coverage + # vm64check coverage check1: - // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal + # check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero la ra, check2 jalr t0 @@ -79,7 +79,7 @@ check11: li t0, 0x8000000000000000 csrw satp, t0 - // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal + # check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero la ra, check12 jalr t0 @@ -118,8 +118,8 @@ self_loop: trap_handler: csrw mepc, ra # return to address in ra mret - -.section .tohost + +.section .tohost tohost: # write to HTIF .dword 0 fromhost: @@ -146,7 +146,7 @@ topofstack: lw t1, 0(t0) li t1, 0x0000010080000000 lw t1, 0(t0) - li t0, 0x8000000000000000 + li t0, 0x8000000000000000 csrw satp, t0 # SV39 mode li t0, 0x0000000080000000 lw t1, 0(t0) @@ -158,7 +158,7 @@ topofstack: lw t1, 0(t0) li t1, 0x0000010080000000 lw t1, 0(t0) - li t0, 0x9000000000000000 + li t0, 0x9000000000000000 csrw satp, t0 # SV48 mode li t0, 0x0000000080000000 lw t1, 0(t0) @@ -170,5 +170,5 @@ topofstack: lw t1, 0(t0) li t1, 0x0000010080000000 lw t1, 0(t0) - li t0, 0x0000000000000000 - csrw satp, t0 # disable virtual memory \ No newline at end of file + li t0, 0x0000000000000000 + csrw satp, t0 # disable virtual memory From f15ef57cb91d0165b77f48aa518b1354c7359a86 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 11:35:15 -0700 Subject: [PATCH 183/232] Debugging --- tests/coverage/Makefile | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 232bc053c..3285714b4 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -7,17 +7,20 @@ SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) #PROGS = $(patsubst %.S,%,$(SRCS)) SRCDIR = . SRCEXT = S -SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) +SOURCES ?= amoAccessFault.S #$(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) OBJEXT = elf OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT)) all: $(OBJECTS) -%.elf.objdump: %.elf +elf.o.objdump: %.elf # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< + riscv64-unknown-elf-as -o WALLY-init-lib.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 WALLY-init-lib.h + riscv64-unknown-elf-as -o $*.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< + # riscv64-unknown-elf-ld -o linked-$@ $@ WALLY-init-lib.o -T../../examples/link/link.ld + riscv64-unknown-elf-gcc -g -o $@ $*.o WALLY-init-lib.o -T../../examples/link/link.ld -mabi=lp64 -nostartfiles riscv64-unknown-elf-objdump -S -D $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump From 4c0e4846ea3ba722cabcc420647aae9bf08dafbd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 12:25:30 -0700 Subject: [PATCH 184/232] More debugging --- tests/coverage/Makefile | 15 ++-- tests/coverage/amoAccessFault.S | 138 +++++++++++++++++++++++++++++++- 2 files changed, 145 insertions(+), 8 deletions(-) diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 3285714b4..fbb548329 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -7,7 +7,7 @@ SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) #PROGS = $(patsubst %.S,%,$(SRCS)) SRCDIR = . SRCEXT = S -SOURCES ?= amoAccessFault.S #$(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) +SOURCES ?= amoAccessFault.S # $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) OBJEXT = elf OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT)) @@ -17,21 +17,22 @@ elf.o.objdump: %.elf # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-as -o WALLY-init-lib.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 WALLY-init-lib.h - riscv64-unknown-elf-as -o $*.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< - # riscv64-unknown-elf-ld -o linked-$@ $@ WALLY-init-lib.o -T../../examples/link/link.ld - riscv64-unknown-elf-gcc -g -o $@ $*.o WALLY-init-lib.o -T../../examples/link/link.ld -mabi=lp64 -nostartfiles +# riscv64-unknown-elf-gcc -E -Wall -g -o $*.s -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $< +# riscv64-unknown-elf-as -g -o WALLY-init-lib.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 WALLY-init-lib.h + riscv64-unknown-elf-as -g -o $*.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< +# riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o riscv64-unknown-elf-objdump -S -D $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump - + sim: %.elf spike +signature=%.signature.output +signature-granularity=8 %.elf diff --ignore-case %.signature.output %.reference_output || exit echo "Signature matches! Success!" clean: - rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile + rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile *.o *.s diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index 45350a0e8..83dc7d368 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -26,7 +26,143 @@ # load code to initalize stack, handle interrupts, terminate -#include "WALLY-init-lib.h" +.section .text.init +.global rvtest_entry_point + +rvtest_entry_point: + la sp, topofstack # Initialize stack pointer (not used) + + # Set up interrupts + la t0, trap_handler + csrw mtvec, t0 # Initialize MTVEC to trap_handler + csrw mideleg, zero # Don't delegate interrupts + csrw medeleg, zero # Don't delegate exceptions +# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again +# li t1, 0x02004000 # MTIMECMP in CLINT +# sd t0, 0(t1) + li t0, 0x80 +# li t0, 0x00 + csrw mie, t0 # Enable machine timer interrupt + la t0, topoftrapstack + csrw mscratch, t0 # MSCRATCH holds trap stack pointer + csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable + # set up PMP so user and supervisor mode can access full address space + csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX + li t0, 0xFFFFFFFF + csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses + j main # Call main function in user test program + +done: + li a0, 4 # argument to finish program + ecall # system call to finish program + j self_loop # wait forever (not taken) + +.align 4 # trap handlers must be aligned to multiple of 4 +trap_handler: + # Load trap handler stack pointer tp + csrrw tp, mscratch, tp # swap MSCRATCH and tp + sd t0, 0(tp) # Save t0 and t1 on the stack + sd t1, -8(tp) + csrr t0, mcause # Check the cause + csrr t1, mtval # And the trap value + bgez t0, exception # if msb is clear, it is an exception + +interrupt: # must be a timer interrupt + li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again + li t1, 0x02004000 # MTIMECMP in CLIN + sd t0, 0(t1) + csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt + li t0, 32 + csrc sip, t0 # clears stimer interrupt + j trap_return # clean up and return + +exception: + csrr t0, mcause + li t1, 8 # is it an ecall trap? + andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 + bne t0, t1, trap_return # ignore other exceptions + +ecall: + li t0, 4 + beq a0, t0, write_tohost # call 4: terminate program + bltu a0, t0, changeprivilege # calls 0-3: change privilege level + j trap_return # ignore other ecalls + +changeprivilege: + li t0, 0x00001800 # mask off mstatus.MPP in bits 11-12 + csrc mstatus, t0 + andi a0, a0, 0x003 # only keep bottom two bits of argument + slli a0, a0, 11 # move into mstatus.MPP position + csrs mstatus, a0 # set mstatus.MPP with desired privilege + +trap_return: # return from trap handler + csrr t0, mepc # get address of instruction that caused exception + li t1, 0x20000 + csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped + lh t0, 0(t0) # get instruction that caused exception + csrc mstatus, t1 # clear mprv bit to restore normal operation + li t1, 3 + and t0, t0, t1 # mask off upper bits + beq t0, t1, instr32 # if lower 2 bits are 11, instruction is uncompresssed + li t0, 2 # increment PC by 2 for compressed instruction + j updateepc +instr32: + li t0, 4 +updateepc: + csrr t1, mepc # add 2 or 4 (from t0) to MEPC to determine return Address + add t1, t1, t0 + csrw mepc, t1 + + ld t1, -8(tp) # restore t1 and t0 + ld t0, 0(tp) + csrrw tp, mscratch, tp # restore tp + mret # return from trap + +write_tohost: + la t1, tohost + li t0, 1 # 1 for success, 3 for failure + sd t0, 0(t1) # send success code + +self_loop: + j self_loop # wait + +# utility routines + +# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 +setmsb: + li a0, 0x80000000 # 1 in bit 31 + slli a1, a0, 1 # check if register is wider than 31 bits + beqz a1, setmsbdone # yes, a0 has 1 in bit 31 + slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63 + slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 +setmsbdone: + ret # return to calller + +.section .tohost +tohost: # write to HTIF + .dword 0 +fromhost: + .dword 0 + +.EQU XLEN,64 +begin_signature: + .fill 6*(XLEN/32),4,0xdeadbeef # +end_signature: + +scratch: + .fill 4,4,0x0 + +# Initialize stack with room for 512 bytes +.bss + .space 512 +topofstack: +# And another stack for the trap handler +.bss + .space 512 +topoftrapstack: + +.align 4 +.section .text.main # run-elf.bash find this in project description main: From a995f5e221914ff8640ae8338bac5041cb9c9484 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 13:03:24 -0700 Subject: [PATCH 185/232] Use preprocessor before assembler for gcc --- tests/coverage/Makefile | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index fbb548329..128665f56 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -7,7 +7,7 @@ SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) #PROGS = $(patsubst %.S,%,$(SRCS)) SRCDIR = . SRCEXT = S -SOURCES ?= amoAccessFault.S # $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) +SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) OBJEXT = elf OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT)) @@ -17,11 +17,9 @@ elf.o.objdump: %.elf # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile -# riscv64-unknown-elf-gcc -E -Wall -g -o $*.s -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $< -# riscv64-unknown-elf-as -g -o WALLY-init-lib.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 WALLY-init-lib.h - riscv64-unknown-elf-as -g -o $*.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< -# riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o + riscv64-unknown-elf-gcc -E -Wall -g -o $*.s -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $< + riscv64-unknown-elf-as -g -o $*.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $*.s + riscv64-unknown-elf-gcc -g -o $@ -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o riscv64-unknown-elf-objdump -S -D $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump From 8543cbb093c89d73208d37a943cb238607e2914d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 13:04:40 -0700 Subject: [PATCH 186/232] Revert manually include header file content --- tests/coverage/amoAccessFault.S | 138 +------------------------------- 1 file changed, 1 insertion(+), 137 deletions(-) diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index 83dc7d368..45350a0e8 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -26,143 +26,7 @@ # load code to initalize stack, handle interrupts, terminate -.section .text.init -.global rvtest_entry_point - -rvtest_entry_point: - la sp, topofstack # Initialize stack pointer (not used) - - # Set up interrupts - la t0, trap_handler - csrw mtvec, t0 # Initialize MTVEC to trap_handler - csrw mideleg, zero # Don't delegate interrupts - csrw medeleg, zero # Don't delegate exceptions -# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again -# li t1, 0x02004000 # MTIMECMP in CLINT -# sd t0, 0(t1) - li t0, 0x80 -# li t0, 0x00 - csrw mie, t0 # Enable machine timer interrupt - la t0, topoftrapstack - csrw mscratch, t0 # MSCRATCH holds trap stack pointer - csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable - # set up PMP so user and supervisor mode can access full address space - csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX - li t0, 0xFFFFFFFF - csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses - j main # Call main function in user test program - -done: - li a0, 4 # argument to finish program - ecall # system call to finish program - j self_loop # wait forever (not taken) - -.align 4 # trap handlers must be aligned to multiple of 4 -trap_handler: - # Load trap handler stack pointer tp - csrrw tp, mscratch, tp # swap MSCRATCH and tp - sd t0, 0(tp) # Save t0 and t1 on the stack - sd t1, -8(tp) - csrr t0, mcause # Check the cause - csrr t1, mtval # And the trap value - bgez t0, exception # if msb is clear, it is an exception - -interrupt: # must be a timer interrupt - li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again - li t1, 0x02004000 # MTIMECMP in CLIN - sd t0, 0(t1) - csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt - li t0, 32 - csrc sip, t0 # clears stimer interrupt - j trap_return # clean up and return - -exception: - csrr t0, mcause - li t1, 8 # is it an ecall trap? - andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 - bne t0, t1, trap_return # ignore other exceptions - -ecall: - li t0, 4 - beq a0, t0, write_tohost # call 4: terminate program - bltu a0, t0, changeprivilege # calls 0-3: change privilege level - j trap_return # ignore other ecalls - -changeprivilege: - li t0, 0x00001800 # mask off mstatus.MPP in bits 11-12 - csrc mstatus, t0 - andi a0, a0, 0x003 # only keep bottom two bits of argument - slli a0, a0, 11 # move into mstatus.MPP position - csrs mstatus, a0 # set mstatus.MPP with desired privilege - -trap_return: # return from trap handler - csrr t0, mepc # get address of instruction that caused exception - li t1, 0x20000 - csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped - lh t0, 0(t0) # get instruction that caused exception - csrc mstatus, t1 # clear mprv bit to restore normal operation - li t1, 3 - and t0, t0, t1 # mask off upper bits - beq t0, t1, instr32 # if lower 2 bits are 11, instruction is uncompresssed - li t0, 2 # increment PC by 2 for compressed instruction - j updateepc -instr32: - li t0, 4 -updateepc: - csrr t1, mepc # add 2 or 4 (from t0) to MEPC to determine return Address - add t1, t1, t0 - csrw mepc, t1 - - ld t1, -8(tp) # restore t1 and t0 - ld t0, 0(tp) - csrrw tp, mscratch, tp # restore tp - mret # return from trap - -write_tohost: - la t1, tohost - li t0, 1 # 1 for success, 3 for failure - sd t0, 0(t1) # send success code - -self_loop: - j self_loop # wait - -# utility routines - -# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 -setmsb: - li a0, 0x80000000 # 1 in bit 31 - slli a1, a0, 1 # check if register is wider than 31 bits - beqz a1, setmsbdone # yes, a0 has 1 in bit 31 - slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63 - slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64 -setmsbdone: - ret # return to calller - -.section .tohost -tohost: # write to HTIF - .dword 0 -fromhost: - .dword 0 - -.EQU XLEN,64 -begin_signature: - .fill 6*(XLEN/32),4,0xdeadbeef # -end_signature: - -scratch: - .fill 4,4,0x0 - -# Initialize stack with room for 512 bytes -.bss - .space 512 -topofstack: -# And another stack for the trap handler -.bss - .space 512 -topoftrapstack: - -.align 4 -.section .text.main +#include "WALLY-init-lib.h" # run-elf.bash find this in project description main: From b64f3f05f886b1b9d03eb9e2d3a68844d1fb20b9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 13:18:35 -0700 Subject: [PATCH 187/232] Revert changes to comment format now that preprocessor is being used --- tests/coverage/WALLY-init-lib.h | 58 ++++---- tests/coverage/amoAccessFault.S | 52 +++---- tests/coverage/csrwrites.S | 52 +++---- tests/coverage/dcache1.S | 16 +- tests/coverage/dcache1.py | 2 +- tests/coverage/dcache2.S | 60 ++++---- tests/coverage/ebu.S | 52 +++---- tests/coverage/floatmisc.S | 8 +- tests/coverage/fpu.S | 132 ++++++++--------- tests/coverage/fround.S | 2 +- tests/coverage/gshare.S | 54 +++---- tests/coverage/hptwAccessFault.S | 54 +++---- tests/coverage/ieu.S | 102 ++++++------- tests/coverage/ifu.S | 114 +++++++-------- tests/coverage/ifuCamlineWrite.S | 62 ++++---- tests/coverage/lsu.S | 54 +++---- tests/coverage/nonleafpbmtfault.S | 54 +++---- tests/coverage/pmp.S | 234 +++++++++++++++--------------- tests/coverage/pmpadrdecs.S | 6 +- tests/coverage/pmpcbo.S | 6 +- tests/coverage/pmpcfg.S | 10 +- tests/coverage/pmpcfg1.S | 10 +- tests/coverage/pmpcfg2.S | 8 +- tests/coverage/pmppriority.S | 14 +- tests/coverage/priv.S | 52 +++---- tests/coverage/tlbASID.S | 98 ++++++------- tests/coverage/tlbGLB.S | 142 +++++++++--------- tests/coverage/tlbGP.S | 60 ++++---- tests/coverage/tlbKP.S | 58 ++++---- tests/coverage/tlbM3.S | 58 ++++---- tests/coverage/tlbMP.S | 122 ++++++++-------- tests/coverage/tlbMisaligned.S | 58 ++++---- tests/coverage/tlbNAPOT.S | 58 ++++---- tests/coverage/tlbTP.S | 58 ++++---- tests/coverage/tlbmisc.S | 52 +++---- tests/coverage/vm64check.S | 66 ++++----- 36 files changed, 1049 insertions(+), 1049 deletions(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index f03fb6d1c..0ce72fd6b 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -1,32 +1,32 @@ -########################################## -# WALLY-init-lib.h -# -# Written: David_Harris@hmc.edu 21 March 2023 -# -# Purpose: Initialize stack, handle interrupts, terminate test case -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// WALLY-init-lib.h +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Initialize stack, handle interrupts, terminate test case +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate -# The PMP tests are sensitive to the exact addresses in this code, so unfortunately -# modifying anything breaks those tests. +// load code to initalize stack, handle interrupts, terminate +// The PMP tests are sensitive to the exact addresses in this code, so unfortunately +// modifying anything breaks those tests. .section .text.init .global rvtest_entry_point @@ -128,7 +128,7 @@ write_tohost: self_loop: j self_loop # wait -# utility routines +// utility routines # put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64 setmsb: diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S index 45350a0e8..b69c545a4 100644 --- a/tests/coverage/amoAccessFault.S +++ b/tests/coverage/amoAccessFault.S @@ -1,30 +1,30 @@ -########################################## -# hptwAccessFault.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Checks that only Store/AMO access faults are generated on AMO operations -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://#github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://#solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################### +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Checks that only Store/AMO access faults are generated on AMO operations +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index d21463ef9..fb5cfd436 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -1,30 +1,30 @@ -########################################## -# csrwrites.S -# -# Written: David_Harris@hmc.edu 21 March 2023 -# -# Purpose: Test writes to CSRs -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// csrwrites.S +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Test writes to CSRs +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/dcache1.S b/tests/coverage/dcache1.S index 7703e4a54..4a9b3de15 100644 --- a/tests/coverage/dcache1.S +++ b/tests/coverage/dcache1.S @@ -1,9 +1,9 @@ #include "WALLY-init-lib.h" main: - # start way test #1 + // start way test #1 li t0, 0x80100000 .align 6 - # i$ boundary, way test #1 + // i$ boundary, way test #1 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -20,10 +20,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - # start way test #2 + // start way test #2 li t0, 0x80101000 .align 6 - # i$ boundary, way test #2 + // i$ boundary, way test #2 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -40,10 +40,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - # start way test #3 + // start way test #3 li t0, 0x80102000 .align 6 - # i$ boundary, way test #3 + // i$ boundary, way test #3 .word 0x00000013 .word 0x00000013 .word 0x00000013 @@ -60,10 +60,10 @@ main: sd zero, 0(t0) .word 0x00000013 .word 0x00000013 - # start way test #4 + // start way test #4 li t0, 0x80103000 .align 6 - # i$ boundary, way test #4 + // i$ boundary, way test #4 .word 0x00000013 .word 0x00000013 .word 0x00000013 diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py index 350fe348a..d8740bdda 100644 --- a/tests/coverage/dcache1.py +++ b/tests/coverage/dcache1.py @@ -44,7 +44,7 @@ def wl(line="", comment=None, fname=test_name): ".align" in line or "# include" in line) else True indent = 6 if instr else 0 - comment = "# " + comment if comment is not None else "" + comment = "// " + comment if comment is not None else "" to_write = " " * indent + line + comment + "\n" f.write(to_write) diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index d94a05821..d5a18a708 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -1,48 +1,48 @@ -########################################## -# dcache2.S -# -# Written: avercruysse@hmc.edu 18 April 2023 -# -# Purpose: Test Coverage for D$ -# (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// dcache2.S +// +// Written: avercruysse@hmc.edu 18 April 2023 +// +// Purpose: Test Coverage for D$ +// (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// #include "WALLY-init-lib.h" main: - # way 0 + // way 0 li t0, 0x80100770 sd zero, 0(t0) sd zero, 1(t0) - # way 1 + // way 1 li t0, 0x80101770 sd zero, 0(t0) sd zero, 1(t0) - # way 2 + // way 2 li t0, 0x80102770 sd zero, 0(t0) sd zero, 1(t0) - # way 3 + // way 3 li t0, 0x80103770 sd zero, 0(t0) sd zero, 1(t0) diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index fd888e3d1..872e37394 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -1,30 +1,30 @@ -########################################## -# ebu.S -# -# Written: David_Harris@hmc.edu 21 January 2024 -# -# Purpose: Test coverage for EBU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// ebu.S +// +// Written: David_Harris@hmc.edu 21 January 2024 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/floatmisc.S b/tests/coverage/floatmisc.S index fc43ecd8a..46bbc5418 100644 --- a/tests/coverage/floatmisc.S +++ b/tests/coverage/floatmisc.S @@ -1,7 +1,7 @@ -# debug.S -# David_Harris@hmc.edu 4 February 2023 -# Small code snippets for the purpose of debugging issues -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// debug.S +// David_Harris@hmc.edu 4 February 2023 +// Small code snippets for the purpose of debugging issues +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 .global rvtest_entry_point rvtest_entry_point: diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 2767b5fe1..760898306 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -1,30 +1,30 @@ -########################################## -# fpu.S -# -# Written: David_Harris@hmc.edu 28 March 2023 -# -# Purpose: Test coverage for FPU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// fpu.S +// +// Written: David_Harris@hmc.edu 28 March 2023 +// +// Purpose: Test coverage for FPU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -120,9 +120,9 @@ main: fcvt.s.l ft0, t0 fcvt.s.lu ft0, t0 - # Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc - # fcvt.h.d ft3, ft0 # Somehow this instruction is taking the route on line 124 - # idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc + // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc + # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 + // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc # fcvt.h.w ft3, a0 # fcvt.w.h a0, ft0 # fcvt.q.w ft3, a0 @@ -131,12 +131,12 @@ main: # half-precision NaN boxing la t0, TestData3 - fld ft2, 0(t0) # bad NaN-boxed number - fmadd.h ft1, ft2, ft2, ft2 # Test NaN boxing - fmadd.s ft1, ft2, ft2, ft2 # Test NaN boxing + fld ft2, 0(t0) // bad NaN-boxed number + fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing + fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing - # fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) - # This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. + // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) + // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. li t0, 0x3F812345 # random value slightly bigger than 1 li t1, 0x3F823456 fmv.w.x ft0, t0 # move int to fp register @@ -155,44 +155,44 @@ main: csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE # Completing branch coverage in fctrl.sv - .word 0x38007553 # Testing the all False case for 119 - funct7 under, op = 101 0011 - .word 0x40000053 # Line 145 All False Test case - illegal instruction? - .word 0xd0400053 # Line 156 All False Test case - illegal instruction? - .word 0xc0400053 # Line 162 All False Test case - illegal instruction? - .word 0xd2400053 # Line 168 All False Test case - illegal instruction? - .word 0xc2400053 # Line 174 All False Test case - illegal instruction? + .word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011 + .word 0x40000053 // Line 145 All False Test case - illegal instruction? + .word 0xd0400053 // Line 156 All False Test case - illegal instruction? + .word 0xc0400053 // Line 162 All False Test case - illegal instruction? + .word 0xd2400053 // Line 168 All False Test case - illegal instruction? + .word 0xc2400053 // Line 174 All False Test case - illegal instruction? # Increasing conditional coverage in fctrl.sv - .word 0xc5000007 # Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to - .word 0xe0101053 # toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) - .word 0xe0100053 # toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) - .word 0x40D00053 # toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. - .word 0x40300053 # toggling SupportFmt2 to 0 on line 145 in fctrl. - .word 0x42100053 # toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr - .word 0xf0100053 # toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr + .word 0xc5000007 // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to + .word 0xe0101053 // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2) + .word 0xe0100053 // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2) + .word 0x40D00053 // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. + .word 0x40300053 // toggling SupportFmt2 to 0 on line 145 in fctrl. + .word 0x42100053 // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr + .word 0xf0100053 // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr # Test illegal instructions are detected - .word 0x00000007 # illegal floating-point load (bad Funct3) - .word 0x00000027 # illegal floating-point store (bad Funct3) - .word 0x58F00053 # illegal fsqrt (bad Rs2D) - .word 0x20007053 # illegal fsgnj (bad Funct3) - .word 0x28007053 # illegal fmin/max (bad Funct3) - .word 0xA0007053 # illegal fcmp (bad Funct3) - .word 0xE0007053 # illegal fclass/fmv (bad Funct3) - .word 0xF0007053 # illegal fmv (bad Funct3) - .word 0x43007053 # illegal fcvt.d.* (bad Rs2D) - .word 0x42207053 # illegal fcvt.d.* (bad Rs2D[1]) - .word 0xD5F00053 # illegal fcvt.h.* (bad Rs2D) - .word 0xC5F00053 # illegal fcvt.*.h (bad Rs2D) - .word 0x04000043 # illegal fmadd.h (h not supported) - .word 0xC2800053 # illegal fcvtmod.w.d with rm rne - .word 0xF0101053 # illegal fli with Funct3D not 0 - .word 0xF0400053 # illegal fli with Rs2D not 1 - .word 0x44200053 # illegal instruction for f.cvt.h.h + .word 0x00000007 // illegal floating-point load (bad Funct3) + .word 0x00000027 // illegal floating-point store (bad Funct3) + .word 0x58F00053 // illegal fsqrt (bad Rs2D) + .word 0x20007053 // illegal fsgnj (bad Funct3) + .word 0x28007053 // illegal fmin/max (bad Funct3) + .word 0xA0007053 // illegal fcmp (bad Funct3) + .word 0xE0007053 // illegal fclass/fmv (bad Funct3) + .word 0xF0007053 // illegal fmv (bad Funct3) + .word 0x43007053 // illegal fcvt.d.* (bad Rs2D) + .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1]) + .word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D) + .word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D) + .word 0x04000043 // illegal fmadd.h (h not supported) + .word 0xC2800053 // illegal fcvtmod.w.d with rm rne + .word 0xF0101053 // illegal fli with Funct3D not 0 + .word 0xF0400053 // illegal fli with Rs2D not 1 + .word 0x44200053 // illegal instruction for f.cvt.h.h - # Test divide by zero with rounding mode toward zero + // Test divide by zero with rounding mode toward zero li t0, 1 - csrw frm, t0 # set rounding mode = 1 + csrw frm, t0 // set rounding mode = 1 li t0, 0x3f800000 fcvt.s.w ft1, t0 fcvt.s.w ft2, zero diff --git a/tests/coverage/fround.S b/tests/coverage/fround.S index 76d4c683c..7d469d773 100644 --- a/tests/coverage/fround.S +++ b/tests/coverage/fround.S @@ -1,4 +1,4 @@ -# fround.s +// fround.s #include "WALLY-init-lib.h" diff --git a/tests/coverage/gshare.S b/tests/coverage/gshare.S index 0b213ba34..ef0fcab77 100644 --- a/tests/coverage/gshare.S +++ b/tests/coverage/gshare.S @@ -1,31 +1,31 @@ -########################################## -# gshare.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection. -# TODO: *** Automate checking prediction accuracy. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// gshare.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: basic check that global history and gshare branch npredictors are working as expected. Requires manual inspection. +// TODO: *** Automate checking prediction accuracy. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S index dc7e43dd1..86f681d21 100644 --- a/tests/coverage/hptwAccessFault.S +++ b/tests/coverage/hptwAccessFault.S @@ -1,31 +1,31 @@ -########################################## -# hptwAccessFault.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker -# generate access faults. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker +// generate access faults. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 252488779..43e7b6604 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -1,30 +1,30 @@ -########################################## -# ieu.S -# -# Written: David_Harris@hmc.edu 21 March 2023 -# -# Purpose: Test coverage for IEU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// ieu.S +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Test coverage for IEU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -56,31 +56,31 @@ main: # Test illegal instructions are detected - .word 0x80000033 # illegal R-type instruction - .word 0x00007003 # illegal Load instruction - .word 0x80005013 # illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 - .word 0x00000000 # illegal instruction - .word 0x0000701B # Illegal IW instruction - .word 0x00004023 # Illegal store instruction - .word 0x0400003B # Illegal RW or MulDivW instruction - .word 0x00007067 # Illegal JALR instruction - .word 0x00002063 # Illegal branch instruction - .word 0x60F01013 # Illegal BMU sign extend / count instruction - .word 0x60801013 # Illegal BMU sign extend / count instruction - .word 0x60301013 # Illegal BMU sign extend / count instruction - .word 0x6BF05013 # Illegal BMU similar to rev8 - .word 0x69805013 # Illegal BMU similar to rev8 - .word 0x28F05013 # Illegal BMU similar to or.c - .word 0x60F0101B # Illegal BMU similar to count word - .word 0x6080101B # Illegal BMU similar to count word - .word 0x6030101B # Illegal BMU similar to count word - .word 0x0000202F # Illegal similar to LR - .word 0x1010202F # Illegal similar to LR - .word 0x00402003 # illegal similar to CMO - .word 0x00202003 # illegal similar to CMO - .word 0xFF00302F # illegal Atomic instruction - .word 0xFF00402F # illegal Atomic instruction - .word 0x00000873 # illegal CSR instruction + .word 0x80000033 // illegal R-type instruction + .word 0x00007003 // illegal Load instruction + .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 + .word 0x00000000 // illegal instruction + .word 0x0000701B // Illegal IW instruction + .word 0x00004023 // Illegal store instruction + .word 0x0400003B // Illegal RW or MulDivW instruction + .word 0x00007067 // Illegal JALR instruction + .word 0x00002063 // Illegal branch instruction + .word 0x60F01013 // Illegal BMU sign extend / count instruction + .word 0x60801013 // Illegal BMU sign extend / count instruction + .word 0x60301013 // Illegal BMU sign extend / count instruction + .word 0x6BF05013 // Illegal BMU similar to rev8 + .word 0x69805013 // Illegal BMU similar to rev8 + .word 0x28F05013 // Illegal BMU similar to or.c + .word 0x60F0101B // Illegal BMU similar to count word + .word 0x6080101B // Illegal BMU similar to count word + .word 0x6030101B // Illegal BMU similar to count word + .word 0x0000202F // Illegal similar to LR + .word 0x1010202F // Illegal similar to LR + .word 0x00402003 // illegal similar to CMO + .word 0x00202003 // illegal similar to CMO + .word 0xFF00302F // illegal Atomic instruction + .word 0xFF00402F // illegal Atomic instruction + .word 0x00000873 // illegal CSR instruction # Illegal CMO instructions because envcfg is 0 and system is in user Mode li a0, 0 diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 08a527f94..72c515287 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -1,30 +1,30 @@ -########################################## -# ifu.S -# -# Written: sriley@g.hmc.edu 28 March 2023 -# -# Purpose: Test coverage for IFU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// ifu.S +// +// Written: sriley@g.hmc.edu 28 March 2023 +// +// Purpose: Test coverage for IFU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: @@ -33,47 +33,47 @@ main: csrs mstatus, t0 # calling compressed floating point load double instruction - #.hword 0x2000 # CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op - # binary version 0000 0000 0000 0000 0010 0000 0000 0000 + //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op + // binary version 0000 0000 0000 0000 0010 0000 0000 0000 mv s0, sp - c.fld fs0, 0(s0) # Previously uncovered instructions + c.fld fs0, 0(s0) // Previously uncovered instructions c.fsd fs0, 0(s0) - .hword 0x2002 # c.fldsp fs0, 0 - .hword 0xA002 # c.fsdsp fs0, 0 - .hword 0x9C41 # line 134 Illegal compressed instruction + .hword 0x2002 // c.fldsp fs0, 0 + .hword 0xA002 // c.fsdsp fs0, 0 + .hword 0x9C41 // line 134 Illegal compressed instruction # Zcb coverage tests # could restore assembly language versions when GCC supports Zcb mv s0, sp - #c.lbu s1, 0(s0) # exercise c.lbu - .hword 0x8004 # c.lbu s1, 0(s0) - #c.lh s1, 0(s0) # exercise c.lh - .hword 0x8444 # c.lh s1, 0(s0) - #c.lhu s1, 0(s0) # exercise c.lhu - .hword 0x8404 # c.lhu s1, 0(s0) - #c.sb s1, 0(s0) # exercise c.sb - .hword 0x8804 # c.sb s1, 0(s0) - #c.sh s1, 0(s0) # exercise c.sh - .hword 0x8C04 # c.sh s1, 0(s0) + #c.lbu s1, 0(s0) // exercise c.lbu + .hword 0x8004 // c.lbu s1, 0(s0) + #c.lh s1, 0(s0) // exercise c.lh + .hword 0x8444 // c.lh s1, 0(s0) + #c.lhu s1, 0(s0) // exercise c.lhu + .hword 0x8404 // c.lhu s1, 0(s0) + #c.sb s1, 0(s0) // exercise c.sb + .hword 0x8804 // c.sb s1, 0(s0) + #c.sh s1, 0(s0) // exercise c.sh + .hword 0x8C04 // c.sh s1, 0(s0) - .hword 0x8C44 # Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction - .hword 0x9C00 # Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction + .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction + .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction li s0, 0xFF - # c.zext.b s0 # exercise c.zext.b - .hword 0x9C61 # c.zext.b s0 - # c.sext.b s0 # exercise c.sext.b - .hword 0x9C65 # c.sext.b s0 - # c.zext.h s0 # exercise c.zext.h - .hword 0x9C69 # c.zext.h s0 - # c.sext.h s0 # exercise c.sext.h - .hword 0x9C6D # c.sext.h s0 - # c.zext.w s0 # exercise c.zext.w - .hword 0x9C71 # c.zext.w s0 - # c.not s0 # exercise c.not - .hword 0x9C75 # c.not s0 + # c.zext.b s0 // exercise c.zext.b + .hword 0x9C61 // c.zext.b s0 + # c.sext.b s0 // exercise c.sext.b + .hword 0x9C65 // c.sext.b s0 + # c.zext.h s0 // exercise c.zext.h + .hword 0x9C69 // c.zext.h s0 + # c.sext.h s0 // exercise c.sext.h + .hword 0x9C6D // c.sext.h s0 + # c.zext.w s0 // exercise c.zext.w + .hword 0x9C71 // c.zext.w s0 + # c.not s0 // exercise c.not + .hword 0x9C75 // c.not s0 - .hword 0x9C7D # Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else + .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else # exercise all the cache ways j way0code diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index f32ecd97d..fed86756e 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -1,33 +1,33 @@ -########################################## -# ifuCamlineWrite.S -# -# Written: Miles Cook and Kevin Box 4/17 -# -# Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza -# and Noah Limpert. -# -# Purpose: Test coverage for TLBCamlines in IFU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// ifuCamlineWrite.S +// +// Written: Miles Cook and Kevin Box 4/17 +// +// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza +// and Noah Limpert. +// +// Purpose: Test coverage for TLBCamlines in IFU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -64,7 +64,7 @@ finished: .align 16 # Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 @@ -74,7 +74,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index f0c0494b7..1c1d7fea6 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -1,35 +1,35 @@ -########################################## -# lsu.S -# -# Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 -# -# Purpose: Test coverage for lsu -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// lsu.S +// +// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 +// +// Purpose: Test coverage for lsu +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: - sfence.vma x0, x0 # sfence.vma to assert TLBFlush + sfence.vma x0, x0 // sfence.vma to assert TLBFlush li a0, 0x80000001 # misaligned address amoadd.w t0, a0, (a0) # amo access to misaligned address diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S index 3ad0b914d..d4aa723f7 100644 --- a/tests/coverage/nonleafpbmtfault.S +++ b/tests/coverage/nonleafpbmtfault.S @@ -1,31 +1,31 @@ -########################################## -# hptwAccessFault.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate -# a load or store/amo page fault based on the original access type. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// hptwAccessFault.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate +// a load or store/amo page fault based on the original access type. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/pmp.S b/tests/coverage/pmp.S index b4c13527d..9680bfdeb 100644 --- a/tests/coverage/pmp.S +++ b/tests/coverage/pmp.S @@ -1,8 +1,8 @@ -########################################## -# /content/sample_data/PMPConfigregs.S -# Kevin Box, kbox@hmc.edu -# Created 2023-04-09 23:20:54.863039 -########################################## +/////////////////////////////////////////// +// /content/sample_data/PMPConfigregs.S +// Kevin Box, kbox@hmc.edu +// Created 2023-04-09 23:20:54.863039 +/////////////////////////////////////////// @@ -11,10 +11,10 @@ main: -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 0 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 0 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |0 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -107,16 +107,16 @@ li t4, 1733894653101739012 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 0 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 0 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 1 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 1 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |1 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -209,16 +209,16 @@ li t4, 1155173425015948313 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 1 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 1 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 2 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 2 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |2 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -311,16 +311,16 @@ li t4, 576491624729942289 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 2 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 2 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 3 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 3 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |3 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -413,16 +413,16 @@ li t4, 7903341188813065 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 3 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 3 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 4 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 4 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |4 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -515,16 +515,16 @@ li t4, 2023255344336144641 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 4 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 4 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 5 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 5 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |5 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -617,16 +617,16 @@ li t4, 1444534086185583003 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 5 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 5 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 6 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 6 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |6 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -719,16 +719,16 @@ li t4, 865844589318216595 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 6 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 6 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 7 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 7 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |7 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -821,16 +821,16 @@ li t4, 295285980948829067 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 7 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 7 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 8 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 8 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |8 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -923,16 +923,16 @@ li t4, 1806234828062034819 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 8 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 8 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 9 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 9 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |9 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1025,16 +1025,16 @@ li t4, 1227514141142123288 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 9 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 9 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 10 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 10 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |10 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1127,16 +1127,16 @@ li t4, 648970879321184272 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 10 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 10 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 11 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 11 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |11 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1229,16 +1229,16 @@ li t4, 115848442837209096 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 11 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 11 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 12 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 12 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |12 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1331,16 +1331,16 @@ li t4, 11210457292615976960 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 12 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 12 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 13 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 13 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |13 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1433,16 +1433,16 @@ li t4, 10631735484709601308 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 13 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 13 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 14 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 14 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |14 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1535,16 +1535,16 @@ li t4, 10052905250353847316 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 14 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 14 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// -###########################################################################################################/ -# BEGIN Configuration and Testing Starting at Register: 15 -# -# Configuration +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BEGIN Configuration and Testing Starting at Register: 15 +// +// Configuration # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments # |15 | 0x2000003f | 0x83 | 1 | 00 | 0 | 1 | 1 | 0 @@ -1637,10 +1637,10 @@ li t4, 9446317844957238284 csrw pmpcfg2, t4 -# Testing +// Testing -# END Configuration and Testing Starting at Register: 15 -###########################################################################################################/ +// END Configuration and Testing Starting at Register: 15 +///////////////////////////////////////////////////////////////////////////////////////////////////////////////// j done diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S index 5b9992931..8e6701d8e 100644 --- a/tests/coverage/pmpadrdecs.S +++ b/tests/coverage/pmpadrdecs.S @@ -1,6 +1,6 @@ -# pmpadrdecs -# Liam Chalk, lchalk@hmc.edu, 4/27/2023 -# Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] +// pmpadrdecs +// Liam Chalk, lchalk@hmc.edu, 4/27/2023 +// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S index 25f16fdaa..3a7638404 100644 --- a/tests/coverage/pmpcbo.S +++ b/tests/coverage/pmpcbo.S @@ -1,6 +1,6 @@ -# pmpcbo.S -# David_Harris@hmc.edu 1/21/24 -# Cover PMP checks of cache management instructions +// pmpcbo.S +// David_Harris@hmc.edu 1/21/24 +// Cover PMP checks of cache management instructions #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S index 22cb7a223..1013439b7 100644 --- a/tests/coverage/pmpcfg.S +++ b/tests/coverage/pmpcfg.S @@ -1,8 +1,8 @@ -# pmpcfg part 1 -# Kevin Wan, kewan@hmc.edu, 4/18/2023 -# Liam Chalk, lchalk@hmc.edu, 4/25/2023 -# locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. -# See the next part in pmpcfg1.S +// pmpcfg part 1 +// Kevin Wan, kewan@hmc.edu, 4/18/2023 +// Liam Chalk, lchalk@hmc.edu, 4/25/2023 +// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +// See the next part in pmpcfg1.S #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcfg1.S b/tests/coverage/pmpcfg1.S index b91400ef2..37dcec14b 100644 --- a/tests/coverage/pmpcfg1.S +++ b/tests/coverage/pmpcfg1.S @@ -1,9 +1,9 @@ -# another set of pmpcfg tests. A new file is made because pmpcfg register fields are -# locked forever after writing 1 to the lock bit for the first time. +// another set of pmpcfg tests. A new file is made because pmpcfg register fields are +// locked forever after writing 1 to the lock bit for the first time. -# Kevin Wan, kewan@hmc.edu, 4/13/2023 -# This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. -# for the other part of the tests, see pmpcfg.S +// Kevin Wan, kewan@hmc.edu, 4/13/2023 +// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. +// for the other part of the tests, see pmpcfg.S #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmpcfg2.S b/tests/coverage/pmpcfg2.S index ffc380438..4e0002e6e 100644 --- a/tests/coverage/pmpcfg2.S +++ b/tests/coverage/pmpcfg2.S @@ -1,7 +1,7 @@ -# pmpcfg part 3 -# Kevin Wan, kewan@hmc.edu, 4/18/2023 -# locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. -# See the next part in pmpcfg1.S +// pmpcfg part 3 +// Kevin Wan, kewan@hmc.edu, 4/18/2023 +// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. +// See the next part in pmpcfg1.S #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S index ac8e65c63..8a30c6019 100644 --- a/tests/coverage/pmppriority.S +++ b/tests/coverage/pmppriority.S @@ -1,15 +1,15 @@ -# pmppriority test cases -# Kevin Wan kewan@hmc.edu 4/27/2023 -# want memory ranges to match: -# 1. only the most significant address and none of the lower ones, -# 2. the most significant address and ANY of the lower ones. +// pmppriority test cases +// Kevin Wan kewan@hmc.edu 4/27/2023 +// want memory ranges to match: +// 1. only the most significant address and none of the lower ones, +// 2. the most significant address and ANY of the lower ones. #include "WALLY-init-lib.h" main: - li t1, 0x21FFFFFF # start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. + li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. csrw pmpaddr0, t1 csrw pmpaddr1, t1 csrw pmpaddr2, t1 @@ -30,7 +30,7 @@ main: li t0, 0x1F - csrw pmpcfg0, t0 #set to XWR and NAPOT + csrw pmpcfg0, t0 //set to XWR and NAPOT sw zero, 0(sp) li t0, 0x1F00 diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 61417e83e..1af15add7 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -1,30 +1,30 @@ -########################################## -# priv.S -# -# Written: David_Harris@hmc.edu 23 March 2023 -# -# Purpose: Test coverage for EBU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// priv.S +// +// Written: David_Harris@hmc.edu 23 March 2023 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" main: diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index f7fc56e74..bb870429a 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -1,41 +1,41 @@ -########################################## -# tlbASID.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd -# numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbASID.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd +// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 # try making asid = 0. + li t5, 0x9000000000080080 // try making asid = 0. csrw satp, t5 # sfence.vma x0, x0 @@ -47,7 +47,7 @@ main: li t0, 0xC0000000 li t2, 0 # i = 0 - li t5, 0 # j = 0 # now use as a counter for new asid loop + li t5, 0 # j = 0 // now use as a counter for new asid loop li t3, 32 # Max amount of Loops = 32 loop: bge t2, t3, finished # exit loop if i >= loops @@ -56,10 +56,10 @@ loop: bge t2, t3, finished # exit loop if i >= loops sw t1, 0(t0) fence.I jalr t0 - li t5, 0x9001000000080080 # try making asid = 1 + li t5, 0x9001000000080080 // try making asid = 1 csrw satp, t5 jalr t0 - li t5, 0x9000000000080080 # try making asid = 0 + li t5, 0x9000000000080080 // try making asid = 0 csrw satp, t5 li t4, 0x1000 add t0, t0, t4 @@ -75,57 +75,57 @@ finished: pagetable: .8byte 0x200204C1 -.align 12 # level 2 page table, contains direction to a gigapage +.align 12 // level 2 page table, contains direction to a gigapage .8byte 0x0 .8byte 0x0 - .8byte 0x200000CF # gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208C1 # pointer to next page table entry at 8008 2000 + .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208C1 // pointer to next page table entry at 8008 2000 -.align 12 # level 1 page table, points to level 0 page table +.align 12 // level 1 page table, points to level 0 page table .8byte 0x20020CC1 -.align 12 # level 0 page table, points to address C000 0000 # FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000CF # access xC000 0000 - .8byte 0x200004CF # access xC000 1000 - .8byte 0x200008CF # access xC000 2000 - .8byte 0x20000CCF # access xC000 3000 +.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 + .8byte 0x200000CF // access xC000 0000 + .8byte 0x200004CF // access xC000 1000 + .8byte 0x200008CF // access xC000 2000 + .8byte 0x20000CCF // access xC000 3000 - .8byte 0x200010CF # access xC000 4000 + .8byte 0x200010CF // access xC000 4000 .8byte 0x200014CF .8byte 0x200018CF .8byte 0x20001CCF - .8byte 0x200020CF # access xC000 8000 + .8byte 0x200020CF // access xC000 8000 .8byte 0x200024CF .8byte 0x200028CF .8byte 0x20002CCF - .8byte 0x200030CF # access xC000 C000 + .8byte 0x200030CF // access xC000 C000 .8byte 0x200034CF .8byte 0x200038CF .8byte 0x20003CCF - .8byte 0x200040CF # access xC001 0000 + .8byte 0x200040CF // access xC001 0000 .8byte 0x200044CF .8byte 0x200048CF .8byte 0x20004CCF - .8byte 0x200050CF # access xC001 4000 + .8byte 0x200050CF // access xC001 4000 .8byte 0x200054CF .8byte 0x200058CF .8byte 0x20005CCF - .8byte 0x200060CF # access xC001 8000 + .8byte 0x200060CF // access xC001 8000 .8byte 0x200064CF .8byte 0x200068CF .8byte 0x20006CCF - .8byte 0x200070CF # access xC001 C000 + .8byte 0x200070CF // access xC001 C000 .8byte 0x200074CF .8byte 0x200078CF .8byte 0x20007CCF - .8byte 0x200080CF # access xC002 0000 + .8byte 0x200080CF // access xC002 0000 .8byte 0x200084CF .8byte 0x200088CF .8byte 0x20008CCF diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index 523b02718..affc4e49d 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -1,40 +1,40 @@ -########################################## -# tlbGLB.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# Modified: kevin.j.thomas@okstate.edu May/4/20203 -# -# Purpose: Coverage for the Page Table Entry Global flag check. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbGLB.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// Modified: kevin.j.thomas@okstate.edu May/4/20203 +// +// Purpose: Coverage for the Page Table Entry Global flag check. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" # run-elf.bash find this in project description main: # Page table root address at 0x80010000 - li t5, 0x9000000000080080 # try making asid = 0. + li t5, 0x9000000000080080 // try making asid = 0. csrw satp, t5 # switch to supervisor mode @@ -42,39 +42,39 @@ main: ecall li t5, 0 # j = 0, run nASID only once - li t3, 32 #Max amount of Loops = 32 - li t4, 0x1000 #offset between addressses. - li t1, 0x00008067 #load in jalr x0 x1 0 instruction to be stored + li t3, 32 //Max amount of Loops = 32 + li t4, 0x1000 //offset between addressses. + li t1, 0x00008067 //load in jalr x0 x1 0 instruction to be stored setup: - li t0, 0xC0000000 #starting address + li t0, 0xC0000000 //starting address li t2, 0 # i = 0 - beq t5, zero, loop #jump to first loop + beq t5, zero, loop //jump to first loop loop2: #jump to each of the addresses in different address space bge t2, t3, done - jalr t0 #jump to instruction at the virtual address - add t0, t0, t4 #change address for next loop - addi t2, t2, 1 #keep track of number of loops ran + jalr t0 //jump to instruction at the virtual address + add t0, t0, t4 //change address for next loop + addi t2, t2, 1 //keep track of number of loops ran j loop2 loop: #store jalr across memory bge t2, t3, nASID # exit loop if i >= loops - sw t1, 0(t0) #stores this jalr in the virtual address - fence.I #invalidate instruction cache - jalr t0 #jump to instruction at the virtual address - add t0, t0, t4 #change address for next loop - addi t2, t2, 1 #keep track of number of loops ran + sw t1, 0(t0) //stores this jalr in the virtual address + fence.I //invalidate instruction cache + jalr t0 //jump to instruction at the virtual address + add t0, t0, t4 //change address for next loop + addi t2, t2, 1 //keep track of number of loops ran j loop nASID: #swap to different address space -> jump to each address - li a0, 3 #swap to machine mode + li a0, 3 //swap to machine mode ecall - li t5, 0x9000100000080080 #swap to address space 1 from 0 + li t5, 0x9000100000080080 //swap to address space 1 from 0 csrw satp, t5 - li a0, 1 # change back to supervisor mode. + li a0, 1 // change back to supervisor mode. ecall - li t5, 1 #flag for finished after loops + li t5, 1 //flag for finished after loops j setup @@ -85,97 +85,97 @@ nASID: #swap to different address space -> jump to each address pagetable: .8byte 0x200204C1 -.align 12 # level 2 page table, contains direction to a gigapageg +.align 12 // level 2 page table, contains direction to a gigapageg .8byte 0x0 .8byte 0x0 - .8byte 0x200000EF # gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208E1 # pointer to next page table entry at 8008 2000 + .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208E1 // pointer to next page table entry at 8008 2000 -.align 12 # level 1 page table, points to level 0 page table +.align 12 // level 1 page table, points to level 0 page table .8byte 0x20020CE1 -.align 12 # level 0 page table, points to address C000 0000 # FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000EF # access xC000 0000 - .8byte 0x200004EF # access xC000 1000 - .8byte 0x200008EF # access xC000 2000 - .8byte 0x20000CEF # access xC000 3000 +.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 + .8byte 0x200000EF // access xC000 0000 + .8byte 0x200004EF // access xC000 1000 + .8byte 0x200008EF // access xC000 2000 + .8byte 0x20000CEF // access xC000 3000 - .8byte 0x200010EF # access xC000 4000 + .8byte 0x200010EF // access xC000 4000 .8byte 0x200014EF .8byte 0x200018EF .8byte 0x20001CEF - .8byte 0x200020EF # access xC000 8000 + .8byte 0x200020EF // access xC000 8000 .8byte 0x200024EF .8byte 0x200028EF .8byte 0x20002CEF - .8byte 0x200030EF # access xC000 C000 + .8byte 0x200030EF // access xC000 C000 .8byte 0x200034EF .8byte 0x200038EF .8byte 0x20003CEF - .8byte 0x200040EF # access xC001 0000 + .8byte 0x200040EF // access xC001 0000 .8byte 0x200044EF .8byte 0x200048EF .8byte 0x20004CEF - .8byte 0x200050EF # access xC001 4000 + .8byte 0x200050EF // access xC001 4000 .8byte 0x200054EF .8byte 0x200058EF .8byte 0x20005CEF - .8byte 0x200060EF # access xC001 8000 + .8byte 0x200060EF // access xC001 8000 .8byte 0x200064EF .8byte 0x200068EF .8byte 0x20006CEF - .8byte 0x200070EF # access xC001 C000 + .8byte 0x200070EF // access xC001 C000 .8byte 0x200074eF .8byte 0x200078EF .8byte 0x20007CEF - .8byte 0x200080EF # access xC002 0000 + .8byte 0x200080EF // access xC002 0000 .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF - .8byte 0x200010EF # access xC000 4000 + .8byte 0x200010EF // access xC000 4000 .8byte 0x200014EF .8byte 0x200018EF .8byte 0x20001CEF - .8byte 0x200020EF # access xC000 8000 + .8byte 0x200020EF // access xC000 8000 .8byte 0x200024EF .8byte 0x200028EF .8byte 0x20002CEF - .8byte 0x200030EF # access xC000 C000 + .8byte 0x200030EF // access xC000 C000 .8byte 0x200034EF .8byte 0x200038EF .8byte 0x20003CEF - .8byte 0x200040EF # access xC001 0000 + .8byte 0x200040EF // access xC001 0000 .8byte 0x200044EF .8byte 0x200048EF .8byte 0x20004CEF - .8byte 0x200050EF # access xC001 4000 + .8byte 0x200050EF // access xC001 4000 .8byte 0x200054EF .8byte 0x200058EF .8byte 0x20005CEF - .8byte 0x200060EF # access xC001 8000 + .8byte 0x200060EF // access xC001 8000 .8byte 0x200064EF .8byte 0x200068EF .8byte 0x20006CEF - .8byte 0x200070EF # access xC001 C000 + .8byte 0x200070EF // access xC001 C000 .8byte 0x200074eF .8byte 0x200078EF .8byte 0x20007CEF - .8byte 0x200080EF # access xC002 0000 + .8byte 0x200080EF // access xC002 0000 .8byte 0x200084EF .8byte 0x200088EF .8byte 0x20008CEF diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index 58295195b..da1301cb0 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -1,31 +1,31 @@ -########################################## -# tlbGP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Create Page tables and access gigapages -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbGP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Create Page tables and access gigapages +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -41,8 +41,8 @@ main: li a0, 1 ecall li t5, 0 - li t0, 0xC0200000 # go to first gigapage - li t4, 0x40000000 # put this outside the loop. + li t0, 0xC0200000 // go to first gigapage + li t4, 0x40000000 // put this outside the loop. li t2, 0 # i = 0 li t3, 64 # Max amount of Loops = 16 @@ -67,7 +67,7 @@ pagetable: .8byte 0x200044C1 .align 12 - .8byte 0x000000CF #8000 0000 + .8byte 0x000000CF //8000 0000 .8byte 0x100000CF .8byte 0x200000CF .8byte 0x200000CF diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 1881f305e..ca72a16db 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -1,31 +1,31 @@ -########################################## -# lsu_test.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// lsu_test.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -61,7 +61,7 @@ finished: .align 16 # Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x0000000000000000 @@ -71,7 +71,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index 2cc6b4537..986fb378a 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -1,31 +1,31 @@ -########################################## -# tlbKP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbKP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -73,7 +73,7 @@ finished: .align 16 # Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong .align 12 .8byte 0x00000000200048C1 @@ -83,7 +83,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 72f4af273..5f35c5879 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -1,31 +1,31 @@ -########################################## -# tlbMP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbMP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -42,8 +42,8 @@ main: ecall li t5, 0 - li t0, 0x84000000 # go to first megapage - li t4, 0x200000 # put this outside the loop. + li t0, 0x84000000 // go to first megapage + li t4, 0x200000 // put this outside the loop. li t2, 0 # i = 0 li t3, 32 # Max amount of Loops = 16 @@ -72,93 +72,93 @@ pagetable: .8byte 0x00000000200048C1 -.align 12 # megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) +.align 12 // megapages starting at 8000 0000 going to 8480 0000 (32*2 MiB beyond that) - .8byte 0x200000CF # access 8000,0000 - .8byte 0x200800CF # access 8020,0000 - .8byte 0x201000CF # acesss 8040,0000 - .8byte 0x201800CF # acesss 8060,0000 + .8byte 0x200000CF // access 8000,0000 + .8byte 0x200800CF // access 8020,0000 + .8byte 0x201000CF // acesss 8040,0000 + .8byte 0x201800CF // acesss 8060,0000 - .8byte 0x202000CF # access 8080,0000 - .8byte 0x202800CF # access 80A0,0000 - .8byte 0x203000CF # access 80C0,0000 - .8byte 0x203800CF # access 80E0,0000 + .8byte 0x202000CF // access 8080,0000 + .8byte 0x202800CF // access 80A0,0000 + .8byte 0x203000CF // access 80C0,0000 + .8byte 0x203800CF // access 80E0,0000 - .8byte 0x204000CF # access 8100,0000 + .8byte 0x204000CF // access 8100,0000 .8byte 0x204800CF .8byte 0x205000CF .8byte 0x205800CF - .8byte 0x206000CF # access 8180,0000 + .8byte 0x206000CF // access 8180,0000 .8byte 0x206800CF .8byte 0x207000CF .8byte 0x207800CF - .8byte 0x208000CF # access 8200,0000 + .8byte 0x208000CF // access 8200,0000 .8byte 0x208800CF .8byte 0x209000CF .8byte 0x209800CF - .8byte 0x20A000CF # access 8280,0000 + .8byte 0x20A000CF // access 8280,0000 .8byte 0x20A800CF .8byte 0x20B000CF .8byte 0x20B800CF - .8byte 0x20C000CF # access 8300,0000 + .8byte 0x20C000CF // access 8300,0000 .8byte 0x20C800CF .8byte 0x20D000CF .8byte 0x20D800CF - .8byte 0x20E000CF # access 8380,0000 + .8byte 0x20E000CF // access 8380,0000 .8byte 0x20E800CF .8byte 0x20F000CF .8byte 0x20F800CF - .8byte 0x200000CF # access 8000,0000 I AM REPEATING PTE TO SAVE TIME. - .8byte 0x200800CF # access 8020,0000 - .8byte 0x201000CF # acesss 8040,0000 - .8byte 0x201800CF # acesss 8060,0000 + .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME. + .8byte 0x200800CF // access 8020,0000 + .8byte 0x201000CF // acesss 8040,0000 + .8byte 0x201800CF // acesss 8060,0000 - .8byte 0x202000CF # access 8080,0000 - .8byte 0x202800CF # access 80A0,0000 - .8byte 0x203000CF # access 80C0,0000 - .8byte 0x203800CF # access 80E0,0000 + .8byte 0x202000CF // access 8080,0000 + .8byte 0x202800CF // access 80A0,0000 + .8byte 0x203000CF // access 80C0,0000 + .8byte 0x203800CF // access 80E0,0000 - .8byte 0x204000CF # access 8100,0000 + .8byte 0x204000CF // access 8100,0000 .8byte 0x204800CF .8byte 0x205000CF .8byte 0x205800CF - .8byte 0x206000CF # access 8180,0000 + .8byte 0x206000CF // access 8180,0000 .8byte 0x206800CF .8byte 0x207000CF .8byte 0x207800CF - .8byte 0x208000CF # access 8200,0000 + .8byte 0x208000CF // access 8200,0000 .8byte 0x208800CF .8byte 0x209000CF .8byte 0x209800CF - .8byte 0x20A000CF # access 8280,0000 + .8byte 0x20A000CF // access 8280,0000 .8byte 0x20A800CF .8byte 0x20B000CF .8byte 0x20B800CF - .8byte 0x20C000CF # access 8300,0000 + .8byte 0x20C000CF // access 8300,0000 .8byte 0x20C800CF .8byte 0x20D000CF .8byte 0x20D800CF - .8byte 0x20E000CF # access 8380,0000 + .8byte 0x20E000CF // access 8380,0000 .8byte 0x20E800CF .8byte 0x20F000CF .8byte 0x20F800CF .8byte 0x20004CC1 - # Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF - # point to ... + // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF + // point to ... -.align 12 # should start at 84000000 +.align 12 // should start at 84000000 .8byte 0x210000CF .8byte 0x210004CF .8byte 0x210008CF diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S index 6c72a6be8..13506646d 100644 --- a/tests/coverage/tlbMisaligned.S +++ b/tests/coverage/tlbMisaligned.S @@ -1,30 +1,30 @@ -########################################## -# tlbMisaligned.S -# -# Written: Rose Thompson rose@rosethompson.net -# -# Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbMisaligned.S +// +// Written: Rose Thompson rose@rosethompson.net +// +// Purpose: Create a page table with misaligned load and store access. Checks TLB misses prevent misaligned load/store fault. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -46,8 +46,8 @@ main: ecall li t5, 0 li t2, 0x1000 - li t0, 0x1000 # go to first gigapage - li t4, 0x40000000 # put this outside the loop. + li t0, 0x1000 // go to first gigapage + li t4, 0x40000000 // put this outside the loop. lw t1, 1(t0) # load a misaligned aligned cached address li t1, 0x00008067 #load in jalr @@ -79,7 +79,7 @@ pagetable: .align 12 .8byte 0x0000000020004CC1 - #.8byte 0x00000200800CF# ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? .align 12 #80000000 diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 68fb08d31..c38472ad0 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -1,32 +1,32 @@ -########################################## -# tlbNAPOT.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages -# -# Purpose: Test coverage for LSU NAPOT -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbNAPOT.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages +// +// Purpose: Test coverage for LSU NAPOT +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -138,7 +138,7 @@ ipf: .align 16 # root Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # old page table was 200040 which just pointed to itself! wrong + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong # next page table at 0x80011000 .align 12 diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index 45f751745..89b5d1ec7 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -1,31 +1,31 @@ -########################################## -# tlbTP.S -# -# Written: mmendozamanriquez@hmc.edu 4 April 2023 -# nlimpert@hmc.edu -# -# Purpose: Test coverage for LSU -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbTP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" @@ -41,8 +41,8 @@ main: li a0, 1 ecall li t5, 0 - li t0, 0x80000000 # go to first gigapage - li t4, 0x8000000000 # put this outside the loop. + li t0, 0x80000000 // go to first gigapage + li t4, 0x8000000000 // put this outside the loop. li t2, 0 # i = 0 li t3, 64 # run through 64 PTEs diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index d47678dbd..9e660bdc4 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -1,30 +1,30 @@ -########################################## -# tlbmisc.S -# -# Written David_Harris@hmc.edu 1/1/24 -# -# Purpose: Test coverage for other TLB issues -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// tlbmisc.S +// +// Written David_Harris@hmc.edu 1/1/24 +// +// Purpose: Test coverage for other TLB issues +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# load code to initalize stack, handle interrupts, terminate +// load code to initalize stack, handle interrupts, terminate #include "WALLY-init-lib.h" diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 1b8d73aff..0cc16ef8d 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -1,34 +1,34 @@ -########################################## -# vm64check.S -# -# Written: David_Harris@hmc.edu 7 April 2023 -# -# Purpose: vm64check coverage -# -# A component of the CORE-V-WALLY configurable RISC-V project. -# https://github.com/openhwgroup/cvw -# -# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https://solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -############################################################################################## +/////////////////////////////////////////// +// vm64check.S +// +// Written: David_Harris@hmc.edu 7 April 2023 +// +// Purpose: vm64check coverage +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// -# Cover IMMU vm64check block by jumping to illegal virtual addresses -# Need a nonstandard trap handler to deal with returns from theses jumps -# assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); - # assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); - # assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; +// Cover IMMU vm64check block by jumping to illegal virtual addresses +// Need a nonstandard trap handler to deal with returns from theses jumps +// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); + // assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); + // assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; .section .text.init .global rvtest_entry_point @@ -47,9 +47,9 @@ rvtest_entry_point: # SATP in non-39 mode csrw satp, zero - # vm64check coverage + // vm64check coverage check1: - # check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal + // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero la ra, check2 jalr t0 @@ -79,7 +79,7 @@ check11: li t0, 0x8000000000000000 csrw satp, t0 - # check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal + // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero la ra, check12 jalr t0 From 0f571045b9ce33399f13a4bd9121943c15188382 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 18 Oct 2024 15:25:20 -0700 Subject: [PATCH 188/232] Finally got Makefile working for Quads on GCC 14 --- tests/coverage/Makefile | 57 +++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 128665f56..63b605679 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -1,36 +1,43 @@ -CEXT := c -CPPEXT := cpp -AEXT := s -SEXT := S -SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) -#SRCS = $(wildcard *.S) -#PROGS = $(patsubst %.S,%,$(SRCS)) -SRCDIR = . -SRCEXT = S +# Disable builtin rules because they are a shorter (but incorrect) path that Make will use by default +MAKEFLAGS += --no-builtin-rules +SRCDIR := . +SRCEXT := S +AEXT := s +OBJEXT := o +EXEEXT := elf SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) -OBJEXT = elf -OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT)) +ELFS := $(SOURCES:.$(SRCEXT)=.$(EXEEXT)) +OBJDUMPS := $(addsuffix .objdump, $(ELFS)) +MEMFILES := $(addsuffix .memfile, $(ELFS)) -all: $(OBJECTS) +all: $(OBJDUMPS) $(MEMFILES) -elf.o.objdump: %.elf +# Create dissassembly +%.elf.objdump: %.elf + riscv64-unknown-elf-objdump -S -D $< > $@ + extractFunctionRadix.sh $@ -# Change many things if bit width isn't 64 -%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -E -Wall -g -o $*.s -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $< - riscv64-unknown-elf-as -g -o $*.o -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $*.s - riscv64-unknown-elf-gcc -g -o $@ -mabi=lp64 -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o - riscv64-unknown-elf-objdump -S -D $@ > $@.objdump - riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile - extractFunctionRadix.sh $@.objdump +# Create memfile +%.elf.memfile: %.elf + riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@ -sim: %.elf +# Link object file to create executable +.PRECIOUS: %.$(EXEEXT) +%.$(EXEEXT): %.$(OBJEXT) + riscv64-unknown-elf-gcc -g -o $@ -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o + +# Assemble into object files +%.$(OBJEXT): %.$(AEXT) + riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< + +# Preprocess assembly files +%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h + riscv64-unknown-elf-gcc -E -g -o $@ $< + +sim: %.$(EXEEXT) spike +signature=%.signature.output +signature-granularity=8 %.elf diff --ignore-case %.signature.output %.reference_output || exit echo "Signature matches! Success!" clean: rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile *.o *.s - - - From 60a12efa3067289c2d940780594fd04a221b3679 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 01:00:19 -0700 Subject: [PATCH 189/232] Test user install to custom location --- .github/workflows/install.yml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index dfa449526..857283e17 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -67,6 +67,12 @@ jobs: os: ubuntu-latest image: null riscv_path: /home/riscv + # Custom location user level installation + - name: custom-user-install + os: ubuntu-latest + image: null + user: true + riscv_path: $HOME/riscv # run on selected version of ubuntu or on ubuntu-latest with docker image runs-on: ${{ matrix.os }} From 32c6427ae953c5c194c4b0de649e071150fe7253 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 13:36:38 -0700 Subject: [PATCH 190/232] Only suggest installation log if it exists --- bin/wally-tool-chain-install.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c722abf81..9e7a91327 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -48,7 +48,9 @@ ENDC='\033[0m' # Reset to default color error() { echo -e "${FAIL_COLOR}Error: $STATUS installation failed" echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" - echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information." + if [ -e "$RISCV/logs/$STATUS.log" ]; then + echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information." + fi exit 1 } From 871bae19249344dfee26254ac7b870b1d10b7b37 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 14:18:48 -0700 Subject: [PATCH 191/232] Refactor git_check function to be far more readable --- bin/wally-tool-chain-install.sh | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 9e7a91327..91b6dc716 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -55,16 +55,37 @@ error() { } # Check if a git repository exists, is up to date, and has been installed -# Clones the repository if it doesn't exist +# clones the repository if it doesn't exist +# $1: repo name +# $2: repo url to clone from +# $3: file to check if already installed +# $4: upstream branch, optional, default is master git_check() { local repo=$1 local url=$2 local check=$3 local branch="${4:-master}" - if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd "$repo"; git rev-parse origin/"$branch")) || (! -e $check) ]]; then - return 0 + + # Clone repo if it doesn't exist + if [[ ! -e $repo ]]; then + git clone "$url" + fi + + # Get the current HEAD commit hash and the remote branch commit hash + cd "$repo" + git fetch + local local_head=$(git rev-parse HEAD) + local remote_head=$(git rev-parse origin/"$branch") + + # Check if the git repository is not up to date or the specified file does not exist + if [[ "$local_head" != "$remote_head" ]]; then + echo "$repo is not up to date" + true + elif [[ ! -e $check ]]; then + echo "$check does not exist" + true else - return 1 + false fi } From 57400a12b37f204a8e901c8ea54bd5c2284fba8c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 14:22:48 -0700 Subject: [PATCH 192/232] Refactor logger function to be more readable --- bin/wally-tool-chain-install.sh | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 91b6dc716..fcd3504cf 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -91,8 +91,13 @@ git_check() { # Log output to a file and only print lines with keywords logger() { - local log="$RISCV/logs/$1.log" - cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true) + local log_file="$RISCV/logs/$1.log" + local keyword_pattern="(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)" + local exclude_pattern="(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" + + cat < /dev/stdin | tee -a "$log_file" | \ + (grep -iE --color=never "$keyword_pattern" || true) | \ + (grep -viE --color=never "$exclude_pattern" || true) } set -e # break on error From 8fb7aef7d91f4e640f207c7b5051aceebf6ec379 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 15:32:03 -0700 Subject: [PATCH 193/232] Switch to wget for improved error handling --- bin/wally-tool-chain-install.sh | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index fcd3504cf..b1714e817 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -219,7 +219,9 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then section_header "Installing glib" pip install -U meson # Meson is needed to build glib cd "$RISCV" - curl --location https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz | tar xJ + wget --retry-connrefused --retry-on-host-error https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + tar -xJf glib-2.70.5.tar.xz + rm -f glib-2.70.5.tar.xz cd glib-2.70.5 meson setup _build --prefix="$RISCV" meson compile -C _build @@ -236,7 +238,9 @@ if (( RHEL_VERSION == 8 )); then if [ ! -e "$RISCV"/include/gmp.h ]; then section_header "Installing gmp" cd "$RISCV" - curl --location https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz | tar xJ + wget --retry-connrefused --retry-on-host-error https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + tar -xJf gmp-6.3.0.tar.xz + rm -f gmp-6.3.0.tar.xz cd gmp-6.3.0 ./configure --prefix="$RISCV" make -j "${NUM_THREADS}" @@ -380,7 +384,9 @@ section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" if [ ! -e "$RISCV"/bin/sail ]; then cd "$RISCV" - curl --location https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz | tar xvz --directory="$RISCV" --strip-components=1 + wget --retry-connrefused --retry-on-host-error --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz + tar xz --directory="$RISCV" --strip-components=1 -f sail.tar.gz + rm -f sail.tar.gz echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}" else echo -e "${SUCCESS_COLOR}Sail Compiler already installed.${ENDC}" @@ -456,8 +462,8 @@ section_header "Downloading Site Setup Script" STATUS="site-setup scripts" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then - wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh - wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh + wget --retry-connrefused --retry-on-host-error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh + wget --retry-connrefused --retry-on-host-error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}" echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}" else From fbf607af324296e402473acfe4d4ff5587f9a8dd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 15:48:22 -0700 Subject: [PATCH 194/232] Retry git clone if failure --- bin/wally-tool-chain-install.sh | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index b1714e817..0ada8b0b4 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -68,7 +68,16 @@ git_check() { # Clone repo if it doesn't exist if [[ ! -e $repo ]]; then - git clone "$url" + for ((i=1; i<=5; i++)); do + git clone "$url" && break + echo -e "${WARNING_COLOR}Failed to clone $repo. Retrying.${ENDC}" + rm -rf "$repo" + sleep $i + done + if [[ ! -e $repo ]]; then + echo -e "${ERROR_COLOR}Failed to clone $repo after 5 attempts. Exiting.${ENDC}" + exit 1 + fi fi # Get the current HEAD commit hash and the remote branch commit hash @@ -79,10 +88,9 @@ git_check() { # Check if the git repository is not up to date or the specified file does not exist if [[ "$local_head" != "$remote_head" ]]; then - echo "$repo is not up to date" + echo "$repo is not up to date. Updating now." true elif [[ ! -e $check ]]; then - echo "$check does not exist" true else false From fe43880a235c8f8b74e3c95dbaee567da9dce180 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 16:15:32 -0700 Subject: [PATCH 195/232] Fix path issues --- bin/wally-tool-chain-install.sh | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 0ada8b0b4..4c337434f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -271,7 +271,7 @@ STATUS="riscv-gnu-toolchain" cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then - cd riscv-gnu-toolchain + cd "$RISCV"/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] @@ -297,7 +297,7 @@ STATUS="elf2hex" cd "$RISCV" export PATH=$RISCV/bin:$PATH if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv64-unknown-elf-elf2bin"; then - cd elf2hex + cd "$RISCV"/elf2hex git reset --hard && git clean -f && git checkout master && git pull autoreconf -i ./configure --target=riscv64-unknown-elf --prefix="$RISCV" @@ -319,7 +319,7 @@ section_header "Installing/Updating QEMU" STATUS="qemu" cd "$RISCV" if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then - cd qemu + cd "$RISCV"/qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}" git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" @@ -341,7 +341,7 @@ section_header "Installing/Updating SPIKE" STATUS="spike" cd "$RISCV" if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-sim" "$RISCV/lib/pkgconfig/riscv-riscv.pc"; then - cd riscv-isa-sim + cd "$RISCV"/riscv-isa-sim git reset --hard && git clean -f && git checkout master && git pull mkdir -p build cd build @@ -367,7 +367,7 @@ STATUS="verilator" cd "$RISCV" if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then unset VERILATOR_ROOT - cd verilator + cd "$RISCV"/verilator git reset --hard && git clean -f && git checkout master && git pull autoconf ./configure --prefix="$RISCV" @@ -405,7 +405,7 @@ fi section_header "Installing/Updating RISC-V Sail Model" STATUS="riscv-sail-model" if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then - cd sail-riscv + cd "$RISCV"/sail-riscv git reset --hard && git clean -f && git checkout master && git pull ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] @@ -428,7 +428,7 @@ STATUS="OSU Skywater 130 cell library" mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12" "$RISCV/cad/lib/sky130_osu_sc_t12" "main"; then - cd sky130_osu_sc_t12 + cd "$RISCV"/sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed!${ENDC}" else From 51d5c81392fd47683d0308eaead92e946dfebecf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 16:18:46 -0700 Subject: [PATCH 196/232] Incompatible options on red hat 8 --- bin/wally-tool-chain-install.sh | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 4c337434f..07dc6252b 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -147,6 +147,12 @@ fi export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH +if (( RHEL_VERSION == 8 )); then + retry_on_host_error="" +else + retry_on_host_error="--retry-on-host-error" +fi + # Check for incompatible PATH environment variable before proceeding with installation if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then echo -e "${FAIL_COLOR}Error: You seem to have the current working directory in your \$PATH environment variable." @@ -227,7 +233,7 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then section_header "Installing glib" pip install -U meson # Meson is needed to build glib cd "$RISCV" - wget --retry-connrefused --retry-on-host-error https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + wget --retry-connrefused "$retry_on_host_error" https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz tar -xJf glib-2.70.5.tar.xz rm -f glib-2.70.5.tar.xz cd glib-2.70.5 @@ -246,7 +252,7 @@ if (( RHEL_VERSION == 8 )); then if [ ! -e "$RISCV"/include/gmp.h ]; then section_header "Installing gmp" cd "$RISCV" - wget --retry-connrefused --retry-on-host-error https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + wget --retry-connrefused "$retry_on_host_error" https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz tar -xJf gmp-6.3.0.tar.xz rm -f gmp-6.3.0.tar.xz cd gmp-6.3.0 @@ -392,7 +398,7 @@ section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" if [ ! -e "$RISCV"/bin/sail ]; then cd "$RISCV" - wget --retry-connrefused --retry-on-host-error --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz + wget --retry-connrefused "$retry_on_host_error" --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz tar xz --directory="$RISCV" --strip-components=1 -f sail.tar.gz rm -f sail.tar.gz echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}" @@ -470,8 +476,8 @@ section_header "Downloading Site Setup Script" STATUS="site-setup scripts" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then - wget --retry-connrefused --retry-on-host-error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh - wget --retry-connrefused --retry-on-host-error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh + wget --retry-connrefused "$retry_on_host_error" https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh + wget --retry-connrefused "$retry_on_host_error" https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}" echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}" else From cb0025dffe53d921fc7a7c6ac9ea1cabedcacc57 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 16:40:11 -0700 Subject: [PATCH 197/232] Additional validation in Linux Makefile --- linux/Makefile | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index aadf24bdc..74cabcf32 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -27,9 +27,16 @@ BINARIES := fw_jump.elf vmlinux busybox OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf)) OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) -.PHONY: all generate disassemble install clean cleanDTB cleanDriver check_write_permissions +.PHONY: all generate disassemble install clean cleanDTB check_write_permissions check_environment -all: check_write_permissions clean download Image disassemble install dumptvs +all: check_environment check_write_permissions clean download Image disassemble install dumptvs + +check_environment: $(RISCV) +ifeq ($(findstring :$(RISCV)/lib:,:$(LD_LIBRARY_PATH):),) + @(echo "ERROR: Your environment variables are not set correctly." >&2 \ + && echo "Make sure to source setup.sh or install buildroot using the wally-tool-chain-install.sh script." >&2 \ + && exit 1) +endif check_write_permissions: ifeq ($(SUDO), sudo) @@ -41,24 +48,24 @@ endif && exit 1) @$(SUDO) rm -r $(RISCV)/.test -Image: +Image: check_environment bash -c "unset LD_LIBRARY_PATH; $(MAKE) -C $(BUILDROOT)" $(MAKE) generate @echo "Buildroot Image successfully generated." -install: check_write_permissions +install: check_write_permissions check_environment $(SUDO) rm -rf $(RISCV)/$(BUILDROOT) $(SUDO) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) @echo "Buildroot successfully installed." -dumptvs: check_write_permissions +dumptvs: check_write_permissions check_environment $(SUDO) mkdir -p $(RISCV)/linux-testvectors cd testvector-generation; ./genInitMem.sh @echo "Testvectors successfully generated." generate: $(DTB) $(IMAGES) -$(IMAGES)/%.dtb: ./devicetree/%.dts +$(IMAGES)/%.dtb: check_environment ./devicetree/%.dts dtc -I dts -O dtb $< > $@ $(IMAGES): @@ -70,7 +77,7 @@ $(RISCV): @ echo "and sourced setup.sh" # Disassembly rules --------------------------------------------------- -disassemble: +disassemble: check_environment rm -rf $(BUILDROOT)/output/images/disassembly find $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs cp -t $(BUILDROOT)/output/images/ mkdir -p $(DIS) @@ -114,9 +121,6 @@ $(BUILDROOT): # --------------------------------------------------------------------- -cleanDriver: - rm -f $(DRIVER) - cleanDTB: rm -f $(IMAGES)/*.dtb From f0e58b8fbab675568990be26d0b3ac87241128b5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 16:47:03 -0700 Subject: [PATCH 198/232] Fix syntax error --- bin/wally-tool-chain-install.sh | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 07dc6252b..bbbc42093 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -147,9 +147,7 @@ fi export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH -if (( RHEL_VERSION == 8 )); then - retry_on_host_error="" -else +if (( RHEL_VERSION != 8 )); then retry_on_host_error="--retry-on-host-error" fi From 0ee9fc779c5bd8cac3d03ac2c23aea5e61e17edb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 19:06:11 -0700 Subject: [PATCH 199/232] Always set environ variables so logs upload correctly --- .github/workflows/install.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index 857283e17..e8c431238 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -114,6 +114,7 @@ jobs: fi # Set environment variables for the rest of the job - name: Set Environment Variables + if: always() run: | if [ ! -z ${{ matrix.riscv_path }} ]; then sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh From 401b37dd93bbc1cf9860fadb589683bee4461488 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 19:08:49 -0700 Subject: [PATCH 200/232] Fix Linux Makefile --- linux/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 74cabcf32..b098b0a8b 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -65,7 +65,7 @@ dumptvs: check_write_permissions check_environment generate: $(DTB) $(IMAGES) -$(IMAGES)/%.dtb: check_environment ./devicetree/%.dts +$(IMAGES)/%.dtb: ./devicetree/%.dts dtc -I dts -O dtb $< > $@ $(IMAGES): From 150365d320f5056eab6617c6fee1019c174149f4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 22:18:08 -0700 Subject: [PATCH 201/232] fix wget --- bin/wally-tool-chain-install.sh | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index bbbc42093..db48e08e5 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -231,7 +231,7 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then section_header "Installing glib" pip install -U meson # Meson is needed to build glib cd "$RISCV" - wget --retry-connrefused "$retry_on_host_error" https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + wget -nv --retry-connrefused $retry_on_host_error https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz tar -xJf glib-2.70.5.tar.xz rm -f glib-2.70.5.tar.xz cd glib-2.70.5 @@ -250,7 +250,7 @@ if (( RHEL_VERSION == 8 )); then if [ ! -e "$RISCV"/include/gmp.h ]; then section_header "Installing gmp" cd "$RISCV" - wget --retry-connrefused "$retry_on_host_error" https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + wget -nv --retry-connrefused $retry_on_host_error https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz tar -xJf gmp-6.3.0.tar.xz rm -f gmp-6.3.0.tar.xz cd gmp-6.3.0 @@ -396,7 +396,7 @@ section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" if [ ! -e "$RISCV"/bin/sail ]; then cd "$RISCV" - wget --retry-connrefused "$retry_on_host_error" --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz + wget -nv --retry-connrefused $retry_on_host_error --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz tar xz --directory="$RISCV" --strip-components=1 -f sail.tar.gz rm -f sail.tar.gz echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}" @@ -474,8 +474,8 @@ section_header "Downloading Site Setup Script" STATUS="site-setup scripts" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then - wget --retry-connrefused "$retry_on_host_error" https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh - wget --retry-connrefused "$retry_on_host_error" https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh + wget -nv --retry-connrefused $retry_on_host_error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh + wget -nv --retry-connrefused $retry_on_host_error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}" echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}" else From 19a14a231c44d78a129f6c8e24626784c10f68f8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 22:37:55 -0700 Subject: [PATCH 202/232] Log installation of old distro dependencies --- bin/wally-tool-chain-install.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index db48e08e5..f20da4e22 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -236,8 +236,8 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then rm -f glib-2.70.5.tar.xz cd glib-2.70.5 meson setup _build --prefix="$RISCV" - meson compile -C _build - meson install -C _build + meson compile -C _build -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + meson install -C _build 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] cd "$RISCV" rm -rf glib-2.70.5 echo -e "${SUCCESS_COLOR}glib successfully installed!${ENDC}" @@ -255,8 +255,8 @@ if (( RHEL_VERSION == 8 )); then rm -f gmp-6.3.0.tar.xz cd gmp-6.3.0 ./configure --prefix="$RISCV" - make -j "${NUM_THREADS}" - make install + make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] + make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] cd "$RISCV" rm -rf gmp-6.3.0 echo -e "${SUCCESS_COLOR}gmp successfully installed!${ENDC}" From 0f1f9ab3417654588f3186838a28e988abbdaa84 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 20 Oct 2024 22:53:42 -0700 Subject: [PATCH 203/232] Fix custom user install location --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index e8c431238..a49761e8a 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -72,7 +72,7 @@ jobs: os: ubuntu-latest image: null user: true - riscv_path: $HOME/riscv + riscv_path: $HOME/riscv-toolchain # run on selected version of ubuntu or on ubuntu-latest with docker image runs-on: ${{ matrix.os }} From a4cda877efdc5f2d19ad05252b16c57a76aea782 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 21 Oct 2024 14:52:40 -0500 Subject: [PATCH 204/232] Fixed bit position of SPI fifo receive and transmit flags. --- src/uncore/spi_apb.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 91021e2b6..57260e769 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -221,8 +221,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( SPI_DELAY0: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]}; SPI_DELAY1: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]}; SPI_FMT: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0}; - SPI_TXDATA: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0}; - SPI_RXDATA: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]}; + SPI_TXDATA: Dout <= {TransmitFIFOWriteFull, 23'b0, 8'b0}; + SPI_RXDATA: Dout <= {ReceiveFIFOReadEmpty, 23'b0, ReceiveData[7:0]}; SPI_TXMARK: Dout <= {29'b0, TransmitWatermark}; SPI_RXMARK: Dout <= {29'b0, ReceiveWatermark}; SPI_IE: Dout <= {30'b0, InterruptEnable}; From 170082e30b4fe6dd623f2e0f1238c14ef10ea7f4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 21 Oct 2024 15:38:00 -0700 Subject: [PATCH 205/232] Point installation CI badge at OpenHW repo --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 62a59d5a2..2c2bc0d0a 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -![Installation CI](https://github.com/jordancarlin/cvw/actions/workflows/install.yml/badge.svg?branch=main) +![Installation CI](https://github.com/openhwgroup/cvw/actions/workflows/install.yml/badge.svg?branch=main) # core-v-wally From 69cc36795bbe724021372c079aca68b1bc740a9f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 22 Oct 2024 04:45:40 -0700 Subject: [PATCH 206/232] privileged coverage updates --- config/rv64gc/coverage.svh | 3 ++- sim/questa/wally.do | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d1bbaedbb..1629fb9da 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,7 +9,8 @@ `include "RV64M_coverage.svh" `include "RV64F_coverage.svh" `include "RV64Zfh_coverage.svh" -// `include "RV64VM_coverage.svh" +`include "RV64VM_coverage.svh" +`include "ZicsrM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" diff --git a/sim/questa/wally.do b/sim/questa/wally.do index d147080f3..f59e123f6 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -192,7 +192,7 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 From b848a1abfe22f6d3a4ec114acad68d0f0c32064b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 22 Oct 2024 05:26:29 -0700 Subject: [PATCH 207/232] added no_pseudo_inst to only print regular instructions. --- config/rv32gc/imperas.ic | 2 ++ config/rv64gc/imperas.ic | 1 + 2 files changed, 3 insertions(+) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index eb4039216..57c58c3e8 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -62,6 +62,8 @@ # context registers not implemented --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T +--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions + # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 31584d22d..558fb8cae 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -60,6 +60,7 @@ # context registers not implemented --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T +--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions # nonratified mnosie register not implemented --override cpu/mnoise_undefined=T From dfbe01084fd49cabdcce9fabfa82d415acc09688 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 23 Oct 2024 08:47:56 -0700 Subject: [PATCH 208/232] Fixed error where an elif was written as if in test conditionals --- bin/nightly_build.py | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 506a0e997..6d89f777f 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -410,7 +410,7 @@ class TestRunner: # Remove ANSI escape codes line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index]) - if "Success" in line: + if "Success" in line: # test succeeds passed_configs.append(line.split(':')[0].strip()) elif "passed lint" in line: passed_configs.append(f"Lint: {line.split(' ')[0].strip()}") @@ -419,13 +419,21 @@ class TestRunner: failed_configs.append([f"Lint: {line.split(' ')[0].strip()}", "No Log File"]) #failed_configs.append(line) - elif "Failures detected in output" in line: + elif "Failures detected in output" in line: # Text explicitly fails try: config_name = line.split(':')[0].strip() log_file = os.path.abspath(os.path.join("logs", config_name, ".log")) failed_configs.append((config_name, log_file)) except: failed_configs.append((config_name, "Log file not found")) + + elif "Timeout" in line: # Test times out + try: + config_name = line.split(':')[0].strip() + log_file = os.path.abspath("logs/"+config_name+".log") + failed_configs.append((f"Timeout: {config_name}", log_file)) + except: + failed_configs.append((f"Timeout: {config_name}", "No Log File")) index += 1 @@ -664,7 +672,7 @@ def main(): parser.add_argument('--path',default = "nightly", help='specify the path for where the nightly repositories will be cloned ex: "nightly-runs') parser.add_argument('--repository',default = "https://github.com/openhwgroup/cvw", help='specify which github repository you want to clone') - parser.add_argument('--target', default = "all", help='types of tests you can make are: all, wally-riscv-arch-test, no') + parser.add_argument('--target', default = "--jobs", help='types of tests you can make are: all, wally-riscv-arch-test, no') parser.add_argument('--tests', default = "nightly", help='types of tests you can run are: nightly, test, test_lint') parser.add_argument('--send_email',default = "", nargs="+", help='What emails to send test results to. Example: "[email1],[email2],..."') @@ -699,7 +707,7 @@ def main(): # flags are a list if (args.tests == "all"): test_list = [["python", "./regression-wally", ["--nightly", "--buildroot"]]] - if (args.tests == "nightly"): + elif (args.tests == "nightly"): test_list = [["python", "./regression-wally", ["--nightly"]]] elif (args.tests == "regression"): test_list = [["python", "./regression-wally", []]] @@ -755,11 +763,12 @@ def main(): if args.target != "no": test_runner.execute_makefile(target = args.target, makefile_path=test_runner.cvw) - if args.target == "all": - # Compile Linux for local testing - test_runner.set_env_var("RISCV",str(test_runner.cvw)) - linux_path = test_runner.cvw / "linux" - test_runner.execute_makefile(target = "all", makefile_path=linux_path) + # TODO: remove vestigial code if no longer wanted + # if args.target == "all": + # # Compile Linux for local testing + # test_runner.set_env_var("RISCV",str(test_runner.cvw)) + # linux_path = test_runner.cvw / "linux" + # test_runner.execute_makefile(target = "all", makefile_path=linux_path) ############################################# # RUN TESTS # From 885d8cb936d37f2fdbbd9c635e7881baf706d007 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Thu, 24 Oct 2024 04:53:41 -0700 Subject: [PATCH 209/232] Enabling D and ZfhD Coverage --- config/rv32gc/coverage.svh | 2 ++ config/rv64gc/coverage.svh | 2 ++ 2 files changed, 4 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 3a04643ad..e2d25d765 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -8,6 +8,8 @@ `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" `include "RV32F_coverage.svh" +`include "RV32D_coverage.svh" +`include "RV32ZfhD_coverage.svh" `include "RV32Zfh_coverage.svh" `include "RV32Zicond_coverage.svh" `include "RV32Zca_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 845b20e58..5f60e2039 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,6 +9,8 @@ `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" `include "RV64F_coverage.svh" +`include "RV64D_coverage.svh" +`include "RV64ZfhD_coverage.svh" `include "RV64Zfh_coverage.svh" `include "RV64VM_coverage.svh" `include "RV64Zicond_coverage.svh" From 929f3892e0fc552e33732aa98859424e4e98e1b9 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 24 Oct 2024 12:49:46 -0700 Subject: [PATCH 210/232] Added code to terminate pool processes on timeout --- bin/regression-wally | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/regression-wally b/bin/regression-wally index 2d741ded8..c833516bf 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -534,6 +534,7 @@ def main(): try: num_fail+=result.get(timeout=TIMEOUT_DUR) except TimeoutError: + pool.terminate() num_fail+=1 print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR)) From 44e17efcf3520773b1004bc09ecadb58c766a731 Mon Sep 17 00:00:00 2001 From: Kaitlin Lucio Date: Thu, 24 Oct 2024 16:29:46 -0700 Subject: [PATCH 211/232] Removed unnecessary os.path.dirname in foldermanager init --- bin/nightly_build.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 6d89f777f..349bdb378 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -97,7 +97,7 @@ class FolderManager: self.base_parent_dir = os.path.dirname(self.base_dir) else: self.base_dir = basedir - self.base_parent_dir = os.path.dirname(self.base_dir) + self.base_parent_dir = self.base_dir # logger.info(f"Base directory: {self.base_dir}") # logger.info(f"Parent Base directory: {self.base_parent_dir}") From 1c1acc467e84ce6268152326eecb6830f3a591ae Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 26 Oct 2024 02:01:09 -0700 Subject: [PATCH 212/232] Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0 --- src/uncore/spi_apb.sv | 4 +- .../references/WALLY-spi-01.reference_output | 40 +++++++++---------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 57260e769..54a072ac9 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -234,9 +234,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1)) // Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase - // When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK + // When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK *** dh 10/26/24: this logic is seriously broken. SCLK is not scaled to PCLK/(2*(SckDiv + 1)). SCLKenableEarly doesn't work right for SckDiv=0 assign ZeroDiv = ~|(SckDiv[10:0]); - assign SCLKenable = ZeroDiv ? PCLK : (DivCounter == SckDiv); + assign SCLKenable = ZeroDiv ? 1 : (DivCounter == SckDiv); assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv); always_ff @(posedge PCLK) if (~PRESETn) DivCounter <= '0; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output index f62d9b088..425866ac2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output @@ -32,59 +32,59 @@ 00000003 -00000074 +00000074 # spi_burst_send -00000063 +00000063 # spi_burst_send -00000052 +00000052 # spi_burst_send -00000041 +00000041 # spi_burst_send -000000A1 +000000A1 # spi_burst_send 00000003 -000000B2 +000000B2 # spi_burst_send 00000001 -000000C3 +000000C3 # spi_burst_send -000000D4 +000000D4 # spi_burst_send 00000003 -000000A4 +000000A4 # tx_data write test 00000001 -000000B4 +000000B4 # tx_data write test -000000A5 +000000A5 # spi_burst_send -000000B5 +000000B5 # spi_burst_send -000000C5 +000000C5 # spi_burst_send -000000D5 +000000D5 # spi_burst_send -000000A7 +000000A7 # spi_burst_send -000000B7 +000000B7 # spi_burst_send -000000C7 +000000C7 # spi_burst_send 00000002 -000000D7 +000000D7 # spi_burst_send 00000000 00000011 #basic read write -000000FF +000000FF # first test sck_div -000000AE +000000AE # min sck_div first spi_burst_send 000000AD From e618596e5265b2b3143f5416e60525f4cd210b0f Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 26 Oct 2024 02:11:40 -0700 Subject: [PATCH 213/232] Added CSR coverage --- config/rv32gc/coverage.svh | 6 +++++- config/rv64gc/coverage.svh | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index e2d25d765..2d1730a94 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -5,6 +5,7 @@ // This file is needed in the config subdirectory for each config supporting coverage. // It defines which extensions are enabled for that config. +// Unprivileged extensions `include "RV32I_coverage.svh" `include "RV32M_coverage.svh" `include "RV32F_coverage.svh" @@ -15,4 +16,7 @@ `include "RV32Zca_coverage.svh" `include "RV32Zcb_coverage.svh" `include "RV32ZcbM_coverage.svh" -`include "RV32ZcbZbb_coverage.svh" \ No newline at end of file +`include "RV32ZcbZbb_coverage.svh" + +// Privileged extensions +`include "ZicsrM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 5f60e2039..df3b5403a 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -12,7 +12,6 @@ `include "RV64D_coverage.svh" `include "RV64ZfhD_coverage.svh" `include "RV64Zfh_coverage.svh" -`include "RV64VM_coverage.svh" `include "RV64Zicond_coverage.svh" `include "RV64Zca_coverage.svh" `include "RV64Zcb_coverage.svh" @@ -21,6 +20,7 @@ `include "RV64ZcbZba_coverage.svh" // Privileged extensions +`include "RV64VM_coverage.svh" `include "ZicsrM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" From 0555e58afe0988ab6a26ce71d743d7dc2466ed14 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 26 Oct 2024 02:12:43 -0700 Subject: [PATCH 214/232] Removed unnecessary display statement from testbench for DTIM versions --- testbench/testbench.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index e8ad09b36..5b053c763 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -540,7 +540,6 @@ module testbench; always @(posedge clk) begin if (LoadMem) begin $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.ram.RAM); - $display("Read memfile %s", memfilename); end if (CopyRAM) begin LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64 From 3ba92950600457fc8d66d7a421e28725156eb57b Mon Sep 17 00:00:00 2001 From: Zain2050 Date: Sat, 26 Oct 2024 09:06:01 -0700 Subject: [PATCH 215/232] enabled Zcf in rv32gc --- config/rv32gc/coverage.svh | 1 + 1 file changed, 1 insertion(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 2d1730a94..80ab73f7b 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -17,6 +17,7 @@ `include "RV32Zcb_coverage.svh" `include "RV32ZcbM_coverage.svh" `include "RV32ZcbZbb_coverage.svh" +`include "RV32Zcf_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" From d22988b6788233dd5b2fc7740274b1d00b894dc1 Mon Sep 17 00:00:00 2001 From: Zain2050 Date: Sat, 26 Oct 2024 09:17:34 -0700 Subject: [PATCH 216/232] also added Zcd --- config/rv32gc/coverage.svh | 1 + config/rv64gc/coverage.svh | 1 + 2 files changed, 2 insertions(+) diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 80ab73f7b..217e8788a 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -18,6 +18,7 @@ `include "RV32ZcbM_coverage.svh" `include "RV32ZcbZbb_coverage.svh" `include "RV32Zcf_coverage.svh" +`include "RV32Zcd_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index df3b5403a..0491b4ab3 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -18,6 +18,7 @@ `include "RV64ZcbM_coverage.svh" `include "RV64ZcbZbb_coverage.svh" `include "RV64ZcbZba_coverage.svh" +`include "RV64Zcd_coverage.svh" // Privileged extensions `include "RV64VM_coverage.svh" From 874d5f6cce05decab1d033bb6111b4eef22e4751 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 28 Oct 2024 15:55:34 -0700 Subject: [PATCH 217/232] Updated ImperasDV config to fix issue #1031 --- config/rv32gc/imperas.ic | 13 ++++++++++--- config/rv64gc/imperas.ic | 14 +++++++++++--- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 57c58c3e8..a4b5fe64c 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -59,9 +59,16 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T -# context registers not implemented ---override cpu/scontext_undefined=T ---override cpu/mcontext_undefined=T +## context registers not implemented +#--override cpu/scontext_undefined=True +#--override cpu/mcontext_undefined=True + +# Disable all features that might want mseccfg or CSRs 7a0-7af +--override cpu/Smepmp_version=none +--override cpu/Smmpm=none +#--override cpu/Zicfilp=F +--override cpu/trigger_num=0 # disable CSRs 7a0-7a8 + --override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 558fb8cae..0ff19fa68 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -58,9 +58,17 @@ #--override cpu/hpmcounter_undefined=T # context registers not implemented ---override cpu/scontext_undefined=T ---override cpu/mcontext_undefined=T ---override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions +#--override cpu/scontext_undefined=True +#--override cpu/mcontext_undefined=True + +# Disable all features that might want mseccfg or CSRs 7a0-7af +--override cpu/Smepmp_version=none +--override cpu/Smmpm=none +#--override cpu/Zicfilp=F +--override cpu/trigger_num=0 # disable CSRs 7a0-7a8 + +# For code coverage, don't produce pseudoinstructions +--override no_pseudo_inst=T # nonratified mnosie register not implemented --override cpu/mnoise_undefined=T From 37d2f3220e47f7b1d55d159bfee9bb06fba4a407 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 29 Oct 2024 10:30:08 -0500 Subject: [PATCH 218/232] Added a new spi controller design. Designed as a proof of concept to see if timing issues can be fixed. I intend to work it into existing SPI peripheral. --- src/uncore/spi_controller.sv | 317 +++++++++++++++++++++++++++++++++++ 1 file changed, 317 insertions(+) create mode 100644 src/uncore/spi_controller.sv diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv new file mode 100644 index 000000000..983a9d83e --- /dev/null +++ b/src/uncore/spi_controller.sv @@ -0,0 +1,317 @@ +module spi_controller ( + input logic PCLK, + input logic PRESETn, + input logic TransmitStart, + input logic [11:0] SckDiv, + input logic [1:0] SckMode, + input logic [1:0] CSMode, + input logic [15:0] Delay0, + input logic [15:0] Delay1, + input logic [7:0] txFIFORead, + input logic txFIFOReadEmpty, + output logic SPICLK, + output logic SPIOUT, + output logic CS +); + + // CSMode Stuff + localparam HOLDMODE = 2'b10; + localparam AUTOMODE = 2'b00; + localparam OFFMODE = 2'b11; + + typedef enum logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype; + statetype CurrState, NextState; + + // SCLKenable stuff + logic [11:0] DivCounter; + logic SCLKenable; + logic SCLKenableEarly; + logic SCLKenableLate; + logic EdgeTiming; + logic ZeroDiv; + logic Clock0; + logic Clock1; + logic SCK; // SUPER IMPORTANT, THIS CAN'T BE THE SAME AS SPICLK! + + + // Shift and Sample Edges + logic PreShiftEdge; + logic PreSampleEdge; + logic ShiftEdge; + logic SampleEdge; + + // Frame stuff + logic [2:0] BitNum; + logic LastBit; + logic EndOfFrame; + logic EndOfFrameDelay; + logic PhaseOneOffset; + + // Transmit Stuff + logic ContinueTransmit; + + // SPIOUT Stuff + logic TransmitLoad; + logic [7:0] TransmitReg; + logic Transmitting; + logic EndTransmission; + + logic HoldMode; + + // Delay Stuff + logic [7:0] cssck; + logic [7:0] sckcs; + logic [7:0] intercs; + logic [7:0] interxfr; + + logic HasCSSCK; + logic HasSCKCS; + logic HasINTERCS; + logic HasINTERXFR; + + logic EndOfCSSCK; + logic EndOfSCKCS; + logic EndOfINTERCS; + logic EndOfINTERXFR; + + logic [7:0] CSSCKCounter; + logic [7:0] SCKCSCounter; + logic [7:0] INTERCSCounter; + logic [7:0] INTERXFRCounter; + + logic DelayIsNext; + + // Convenient Delay Reg Names + assign cssck = Delay0[7:0]; + assign sckcs = Delay0[15:8]; + assign intercs = Delay1[7:0]; + assign interxfr = Delay1[15:8]; + + // Do we have delay for anything? + assign HasCSSCK = cssck > 8'b0; + assign HasSCKCS = sckcs > 8'b0; + assign HasINTERCS = intercs > 8'b0; + assign HasINTERXFR = interxfr > 8'b0; + + // Have we hit full delay for any of the delays? + assign EndOfCSSCK = CSSCKCounter == cssck; + assign EndOfSCKCS = SCKCSCounter == sckcs; + assign EndOfINTERCS = INTERCSCounter == intercs; + assign EndOfINTERXFR = INTERXFRCounter == interxfr; + + // Clock Signal Stuff ----------------------------------------------- + // I'm going to handle all clock stuff here, including ShiftEdge and + // SampleEdge. This makes sure that SPICLK is an output of a register + // and it properly synchronizes signals. + + assign SCLKenableLate = DivCounter > SckDiv; + assign SCLKenable = DivCounter == SckDiv; + assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv; + assign LastBit = BitNum == 3'd7; + assign EdgeTiming = SckDiv > 12'b0 ? SCLKenableEarly : SCLKenable; + + //assign SPICLK = Clock0; + + assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame; + assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay; + + always_ff @(posedge PCLK) begin + if (~PRESETn) begin + DivCounter <= 12'b0; + SPICLK <= SckMode[1]; + SCK <= 0; + BitNum <= 3'h0; + PreShiftEdge <= 0; + PreSampleEdge <= 0; + EndOfFrame <= 0; + end else begin + // TODO: Consolidate into one delay counter since none of the + // delays happen at the same time? + if (TransmitStart) begin + SCK <= 0; + end else if (SCLKenable) begin + SCK <= ~SCK; + end + + if ((CurrState == CSSCK) & SCK) begin + CSSCKCounter <= CSSCKCounter + 8'd1; + end else begin + CSSCKCounter <= 8'd0; + end + + if ((CurrState == SCKCS) & SCK) begin + SCKCSCounter <= SCKCSCounter + 8'd1; + end else begin + SCKCSCounter <= 8'd0; + end + + if ((CurrState == INTERCS) & SCK) begin + INTERCSCounter <= INTERCSCounter + 8'd1; + end else begin + INTERCSCounter <= 8'd0; + end + + if ((CurrState == INTERXFR) & SCK) begin + INTERXFRCounter <= INTERXFRCounter + 8'd1; + end else begin + INTERXFRCounter <= 8'd0; + end + + // SPICLK Logic + if (TransmitStart) begin + SPICLK <= SckMode[1]; + end else if (SCLKenable & Transmitting) begin + SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; + end + + // Reset divider + if (SCLKenable | TransmitStart) begin + DivCounter <= 12'b0; + end else begin + DivCounter = DivCounter + 12'd1; + end + + // EndOfFrame controller + // if (SckDiv > 0 ? SCLKenableEarly & LastBit & SPICLK : LastBit & ~SPICLK) begin + // EndOfFrame <= 1'b1; + // end else begin + // EndOfFrame <= 1'b0; + // end + + if (~TransmitStart) begin + EndOfFrame <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting; + end + + // Increment BitNum + if (ShiftEdge & Transmitting) begin + BitNum <= BitNum + 3'd1; + end else if (EndOfFrameDelay) begin + BitNum <= 3'b0; + end + end + end + + // Delay ShiftEdge and SampleEdge by a half PCLK period + // Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges. + // Sweeeeeeeeeet... + always_ff @(posedge ~PCLK) begin + if (~PRESETn | TransmitStart) begin + ShiftEdge <= 0; + PhaseOneOffset <= 0; + SampleEdge <= 0; + EndOfFrameDelay <= 0; + end else begin + ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset; + PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : PhaseOneOffset; + SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting; + EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting; + end + end + + // typedef enum logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype; + // statetype CurrState, NextState; + + assign HoldMode = CSMode == 2'b10; + assign TransmitLoad = TransmitStart | (EndOfFrameDelay & ~txFIFOReadEmpty); + + always_ff @(posedge PCLK) begin + if (~PRESETn) begin + CurrState <= INACTIVE; + end else if (SCLKenable) begin + CurrState <= NextState; + end + end + + always_comb begin + case (CurrState) + INACTIVE: begin // INACTIVE case -------------------------------- + if (TransmitStart) begin + if (~HasCSSCK) begin + NextState = TRANSMIT; + end else begin + NextState = CSSCK; + end + end else begin + NextState = INACTIVE; + end + end + CSSCK: begin // DELAY0 case ------------------------------------- + if (EndOfCSSCK) begin + NextState = TRANSMIT; + end + end + TRANSMIT: begin // TRANSMIT case -------------------------------- + case(CSMode) + AUTOMODE: begin + if (EndTransmission) begin + NextState = INACTIVE; + end else if (ContinueTransmit) begin + NextState = SCKCS; + end + end + HOLDMODE: begin + if (EndTransmission) begin + NextState = HOLD; + end else if (ContinueTransmit) begin + if (HasINTERXFR) NextState = INTERXFR; + end + end + OFFMODE: begin + + end + + endcase + end + SCKCS: begin // SCKCS case -------------------------------------- + if (EndOfSCKCS) begin + if (EndTransmission) begin + if (CSMode == AUTOMODE) NextState = INACTIVE; + else if (CSMode == HOLDMODE) NextState = HOLD; + end else if (ContinueTransmit) begin + if (HasINTERCS) NextState = INTERCS; + else NextState = TRANSMIT; + end + end + end + HOLD: begin // HOLD mode case ----------------------------------- + if (CSMode == AUTOMODE) begin + NextState = INACTIVE; + end else if (TransmitStart) begin // If FIFO is written to, start again. + NextState = TRANSMIT; + end + end + INTERCS: begin // INTERCS case ---------------------------------- + if (EndOfINTERCS) begin + if (HasCSSCK) NextState = CSSCK; + else NextState = TRANSMIT; + end + end + INTERXFR: begin // INTERXFR case -------------------------------- + if (EndOfINTERXFR) begin + NextState = TRANSMIT; + end + end + default: begin + NextState = INACTIVE; + end + endcase + end + + assign Transmitting = CurrState == TRANSMIT; + assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR); + + // + always_ff @(posedge PCLK) begin + if (~PRESETn) begin + TransmitReg <= 8'b0; + end else if (TransmitLoad) begin + TransmitReg <= txFIFORead; + end else if (ShiftEdge) begin + TransmitReg <= {TransmitReg[6:0], TransmitReg[0]}; + end + end + + assign SPIOUT = TransmitReg[7]; + assign CS = CurrState == INACTIVE | CurrState == INTERCS; + +endmodule From 784630b94582434b34ea99ae62a3d8f1989903f1 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 29 Oct 2024 10:53:33 -0500 Subject: [PATCH 219/232] Added wally header to spi_controller. --- src/uncore/spi_controller.sv | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 983a9d83e..c4305047e 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -1,3 +1,34 @@ +/////////////////////////////////////////// +// spi_controller.sv +// +// Written: jacobpease@protonmail.com +// Created: October 28th, 2024 +// Modified: +// +// Purpose: Controller logic for SPI +// +// Documentation: RISC-V System on Chip Design +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + + module spi_controller ( input logic PCLK, input logic PRESETn, From b8c09f96498ea9940259a2dd0d1c470a65a66942 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 29 Oct 2024 12:04:20 -0700 Subject: [PATCH 220/232] Set MTI_VCO_MODE for all Questa runs --- bin/wsim | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/wsim b/bin/wsim index 3f6cbaaae..6df11e6b5 100755 --- a/bin/wsim +++ b/bin/wsim @@ -59,12 +59,12 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che args.testsuite = fields[1] + "_" + fields[3] else: args.testsuite = fields[2] + "_" + fields[3] - elif ('/' in args.testsuite): + elif ('/' in args.testsuite): args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present else: print("ELF file not found: " + args.testsuite) exit(1) - + if(args.lockstep and not args.testsuite.endswith('.elf')): print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf.") exit(1) @@ -89,13 +89,13 @@ if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 prefix = "" if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): - if (args.sim == "questa" or args.sim == "vcs"): + if (args.sim == "questa" or args.sim == "vcs"): prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" - if (args.sim == "questa"): - prefix = "MTI_VCO_MODE=64 " + prefix +if (args.sim == "questa"): + prefix = "MTI_VCO_MODE=64 " + prefix if (args.lockstep or args.lockstepverbose): - if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) + if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) else: ImperasPlusArgs = "" if(args.fcovimp): CovEnableStr = "1" if int(args.covlog) > 0 else "0" From 7993a877335111e17287f8e68a83e8675df1c7a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 29 Oct 2024 12:08:48 -0700 Subject: [PATCH 221/232] Add comment for MTI_VCO_MODE --- bin/wsim | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/wsim b/bin/wsim index 6df11e6b5..ca44e22a6 100755 --- a/bin/wsim +++ b/bin/wsim @@ -91,6 +91,7 @@ prefix = "" if (args.lockstep or args.lockstepverbose or args.fcov or args.fcovimp): if (args.sim == "questa" or args.sim == "vcs"): prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" +# Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines if (args.sim == "questa"): prefix = "MTI_VCO_MODE=64 " + prefix From 40783c1a5469892fcc6e5dd463d071481a347540 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 29 Oct 2024 18:01:47 -0700 Subject: [PATCH 222/232] Update README for design compiler support in red hat 9 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2c2bc0d0a..40dc08d51 100644 --- a/README.md +++ b/README.md @@ -184,7 +184,7 @@ The Synopsys Installer automatically installs all downloaded product files into ``` > [!Note] -> Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. +> Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2024, the Synopsys CAD tools for SoC design are only supported on Red Hat Enterprise Linux (or AlmaLinux/Rocky) 8.4+ or 9.1+ or SUSE Linux Enterprise Server (SLES) 15. The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. From b9317e7cd38c01a37c0e562afa7a963cde343662 Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Wed, 30 Oct 2024 03:28:58 -0700 Subject: [PATCH 223/232] Fixed fround bug --- src/fpu/fround.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index 3265ec626..fadd963d0 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -76,7 +76,8 @@ module fround import cvw::*; #(parameter cvw_t P) ( assign Eeqm1 = ($signed(E) == -1); // Logic for nonnegative mask and rounding bits - assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below. + // assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below. + assign IMask = $signed({1'b1, {P.NF{1'b0}}}) >>> E; assign Tmasknonneg = ~IMask >>> 1'b1; assign HotE = IMask & ~(IMask << 1'b1); assign HotEP1 = HotE >> 1'b1; From b1f340ba5c1b0c3bb3a252dbc2f230294c76fe6d Mon Sep 17 00:00:00 2001 From: Corey Hickson Date: Wed, 30 Oct 2024 03:39:55 -0700 Subject: [PATCH 224/232] formatting --- src/fpu/fround.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index fadd963d0..6c37d2973 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -76,8 +76,7 @@ module fround import cvw::*; #(parameter cvw_t P) ( assign Eeqm1 = ($signed(E) == -1); // Logic for nonnegative mask and rounding bits - // assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below. - assign IMask = $signed({1'b1, {P.NF{1'b0}}}) >>> E; + assign IMask = $signed({1'b1, {P.NF{1'b0}}}) >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below. assign Tmasknonneg = ~IMask >>> 1'b1; assign HotE = IMask & ~(IMask << 1'b1); assign HotEP1 = HotE >> 1'b1; From 43f5ec283c8d6d74279d3953ba1633a1006fa2ec Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 26 Oct 2024 02:02:14 -0700 Subject: [PATCH 225/232] Added -j6 to nightly_build to make tests quicker. Untested, git rebase -i once it is confirmed this does not affect coverage using a nightly run --- bin/nightly_build.py | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 349bdb378..8c184b66c 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -288,16 +288,17 @@ class TestRunner: makefile_location = self.cvw.joinpath(makefile_path) os.chdir(makefile_location) - output_file = self.log_dir.joinpath(f"make-{target}-output.log") + if target: + output_file = self.log_dir.joinpath(f"make-{target}-output.log") + else: output_file = self.log_dir.joinpath(f"make-output.log") - command = ["make"] + command = ["make", "-j6"] # Add target to the command if specified if target: command.append(target) - self.logger.info(f"Command used in directory {makefile_location}: {command[0]} {command[1]}") - else: - self.logger.info(f"Command used in directory {makefile_location}: {command[0]}") + + self.logger.info(f"Command used in directory {makefile_location}: {' '.join(command)}") # Execute the command using subprocess and save the output into a file with open(output_file, "w") as f: @@ -311,10 +312,10 @@ class TestRunner: # Check the result if result.returncode == 0: - self.logger.info(f"Tests have been made with target: {target}") + self.logger.info(f"Tests have been made with target: {' '.join(command)}") return True else: - self.logger.error(f"Error making the tests. Target: {target}") + self.logger.error(f"Error making the tests. Command: {' '.join(command)}") return False def run_tests(self, test_type=None, test_name=None, test_extensions=None): @@ -422,7 +423,7 @@ class TestRunner: elif "Failures detected in output" in line: # Text explicitly fails try: config_name = line.split(':')[0].strip() - log_file = os.path.abspath(os.path.join("logs", config_name, ".log")) + log_file = os.path.abspath(os.path.join("logs", config_name)) failed_configs.append((config_name, log_file)) except: failed_configs.append((config_name, "Log file not found")) @@ -672,7 +673,7 @@ def main(): parser.add_argument('--path',default = "nightly", help='specify the path for where the nightly repositories will be cloned ex: "nightly-runs') parser.add_argument('--repository',default = "https://github.com/openhwgroup/cvw", help='specify which github repository you want to clone') - parser.add_argument('--target', default = "--jobs", help='types of tests you can make are: all, wally-riscv-arch-test, no') + parser.add_argument('--target', default = "", help='types of tests you can make are: all, wally-riscv-arch-test, no') parser.add_argument('--tests', default = "nightly", help='types of tests you can run are: nightly, test, test_lint') parser.add_argument('--send_email',default = "", nargs="+", help='What emails to send test results to. Example: "[email1],[email2],..."') From f605cb693a94558a2ddd4e328e408ada0b973e5d Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 26 Oct 2024 02:15:37 -0700 Subject: [PATCH 226/232] Added --dry-run feature. Changed detection for buildrootboot sim when adding short buildroot tests with multiple sims to avoid unnecessary failures --- bin/regression-wally | 40 +++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 643787adc..2b325f437 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -334,22 +334,29 @@ def search_log_for_text(text, grepfile): # print(" search_log_for_text invoking %s" % grepcmd) return os.system(grepcmd) == 0 -def run_test_case(config): - """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" +def run_test_case(config, dryrun: bool = False): + """ + Run the given test case, and return 0 if the test suceeds and 1 if it fails + + Do not execute commands if dryrun + """ grepfile = config.grepfile cmd = config.cmd os.chdir(regressionDir) - # print(" run_test_case invoking %s" % cmd, flush=True) - os.system(cmd) - if search_log_for_text(config.grepstr, grepfile): - # Flush is needed to flush output to stdout when running in multiprocessing Pool -# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name), flush=True) - print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd), flush=True) + if dryrun: + print(f"Executing {cmd}", flush=True) return 0 else: - print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd), flush=True) - print(" Check %s" % grepfile) - return 1 + os.system(cmd) + if search_log_for_text(config.grepstr, grepfile): + # Flush is needed to flush output to stdout when running in multiprocessing Pool + # print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name), flush=True) + print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd), flush=True) + return 0 + else: + print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd), flush=True) + print(" Check %s" % grepfile) + return 1 ################################## # Main body @@ -363,6 +370,7 @@ os.chdir(regressionDir) coveragesim = "questa" # Questa is required for code/functional coverage #defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready defaultsim = "verilator" # Default simulator for all other tests +buildrootbootsim = "questa" parser = argparse.ArgumentParser() parser.add_argument("--ccov", help="Code Coverage", action="store_true") @@ -371,6 +379,7 @@ parser.add_argument("--nightly", help="Run large nightly regression", action="st parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") +parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true") args = parser.parse_args() if (args.nightly): @@ -404,7 +413,7 @@ configs = [ # run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests if (args.buildroot): # addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours - addTests(tests_buildrootbootlockstep, "questa") # lockstep with Questa and ImperasDV runs overnight + addTests(tests_buildrootbootlockstep, buildrootbootsim) # lockstep with Questa and ImperasDV runs overnight if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) @@ -417,7 +426,7 @@ elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional c else: for sim in sims: - if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one + if (not (args.buildroot and sim == buildrootbootsim)): # skip short buildroot sim if running long one addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) @@ -428,6 +437,7 @@ if (args.nightly): addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", "questa", 0) addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", "questa", 0) addTests(derivconfigtests, defaultsim) + addTests(bpredtests, defaultsim) # testfloat tests if (args.testfloat): # for testfloat alone, just run testfloat tests @@ -540,9 +550,9 @@ def main(): # Coverage report if args.ccov: - os.system('make QuestaCodeCoverage') + os.system('make QuestaCodeCoverage') if args.fcov: - os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge') + os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) From 9284dd3a9a7c769cb011b2fc7e0dfd320f0dd76a Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sun, 27 Oct 2024 17:59:00 -0700 Subject: [PATCH 227/232] Changed buildrootbootsim to lockstepsim and added lockstepsim to lockstep tests in nightly --- bin/regression-wally | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 2b325f437..1f30a9dce 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -370,7 +370,7 @@ os.chdir(regressionDir) coveragesim = "questa" # Questa is required for code/functional coverage #defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready defaultsim = "verilator" # Default simulator for all other tests -buildrootbootsim = "questa" +lockstepsim = "questa" parser = argparse.ArgumentParser() parser.add_argument("--ccov", help="Code Coverage", action="store_true") @@ -413,7 +413,7 @@ configs = [ # run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests if (args.buildroot): # addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours - addTests(tests_buildrootbootlockstep, buildrootbootsim) # lockstep with Questa and ImperasDV runs overnight + addTests(tests_buildrootbootlockstep, lockstepsim) # lockstep with Questa and ImperasDV runs overnight if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) @@ -426,7 +426,7 @@ elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional c else: for sim in sims: - if (not (args.buildroot and sim == buildrootbootsim)): # skip short buildroot sim if running long one + if (not (args.buildroot and sim == lockstepsim)): # skip short buildroot sim if running long one addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) @@ -434,8 +434,8 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", "questa", 0) - addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", "questa", 0) + addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) addTests(derivconfigtests, defaultsim) addTests(bpredtests, defaultsim) From b9d215db7672984d8442df18c39c7deec6cd9e72 Mon Sep 17 00:00:00 2001 From: Kaitlin Lucio Date: Mon, 28 Oct 2024 16:05:39 -0700 Subject: [PATCH 228/232] Update regression-wally according to PR --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 1f30a9dce..0a7a8fa69 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -437,7 +437,7 @@ if (args.nightly): addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) addTests(derivconfigtests, defaultsim) - addTests(bpredtests, defaultsim) + # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. # testfloat tests if (args.testfloat): # for testfloat alone, just run testfloat tests From c105c09cdeb5f99847592ceb645ed9d1a8262fa3 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 30 Oct 2024 11:39:11 -0700 Subject: [PATCH 229/232] Added jobs flag to make during nightly regression --- bin/nightly_build.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/nightly_build.py b/bin/nightly_build.py index 8c184b66c..cb8583eef 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -292,11 +292,11 @@ class TestRunner: output_file = self.log_dir.joinpath(f"make-{target}-output.log") else: output_file = self.log_dir.joinpath(f"make-output.log") - command = ["make", "-j6"] - - # Add target to the command if specified - if target: - command.append(target) + # Execute make with target and cores/2 + if target: + command = ["make", target, "--jobs=$(($(nproc)/2))"] + else: + command = ["make", "--jobs=$(($(nproc)/2))"] self.logger.info(f"Command used in directory {makefile_location}: {' '.join(command)}") @@ -305,7 +305,7 @@ class TestRunner: formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S") f.write(formatted_datetime) f.write("\n\n") - result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True) + result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True, shell=True) # Execute the command using a subprocess and not save the output #result = subprocess.run(command, text=True) From 1636942166d7ef5b1603a1229b3864fb45f187d6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 30 Oct 2024 15:37:33 -0700 Subject: [PATCH 230/232] Link ncurses6 to ncurses 5 on Ubuntu 24.04 for Vivado --- bin/wally-package-install.sh | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 725d3b201..ce79dc575 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -123,5 +123,14 @@ else eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" + + # Post install steps + # Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6 + # Create symbolic links to the ncurses6 libraries to fool Vivado + if (( UBUNTU_VERSION >= 24 )); then + ln -vsf /lib/x86_64-linux-gnu/libncurses.so.6 /lib/x86_64-linux-gnu/libncurses.so.5 + ln -vsf /lib/x86_64-linux-gnu/libtinfo.so.6 /lib/x86_64-linux-gnu/libntinfo.so.5 + fi + echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" fi From e8bcbb42ac405cfa6ab8c7b510dcfc00ad898dbf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 30 Oct 2024 15:39:01 -0700 Subject: [PATCH 231/232] Add sudo --- bin/wally-package-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index ce79dc575..1fc003189 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -128,8 +128,8 @@ else # Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6 # Create symbolic links to the ncurses6 libraries to fool Vivado if (( UBUNTU_VERSION >= 24 )); then - ln -vsf /lib/x86_64-linux-gnu/libncurses.so.6 /lib/x86_64-linux-gnu/libncurses.so.5 - ln -vsf /lib/x86_64-linux-gnu/libtinfo.so.6 /lib/x86_64-linux-gnu/libntinfo.so.5 + sudo ln -vsf /lib/x86_64-linux-gnu/libncurses.so.6 /lib/x86_64-linux-gnu/libncurses.so.5 + sudo ln -vsf /lib/x86_64-linux-gnu/libtinfo.so.6 /lib/x86_64-linux-gnu/libntinfo.so.5 fi echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" From 51800ad4d1e3429e3df67792f020c9e6a9301348 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 30 Oct 2024 15:40:38 -0700 Subject: [PATCH 232/232] Fix installation workflow check paths --- .github/workflows/install.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml index b87f4f116..b065cd924 100644 --- a/.github/workflows/install.yml +++ b/.github/workflows/install.yml @@ -18,7 +18,7 @@ on: paths: - 'bin/wally-tool-chain-install.sh' - 'bin/wally-distro-check.sh' - - 'wally-package-install.sh' + - 'bin/wally-package-install.sh' schedule: - cron: "0 7 * * 3" # Run at 12:00 AM Pacific Time on Wednesdays