mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
LSU minor edits
This commit is contained in:
parent
b795cf4731
commit
7c91ed38a3
@ -86,7 +86,7 @@
|
|||||||
// WFI Timeout Wait
|
// WFI Timeout Wait
|
||||||
`define WFI_TIMEOUT_BIT 16
|
`define WFI_TIMEOUT_BIT 16
|
||||||
|
|
||||||
// Peripheral Physiccal Addresses
|
// Peripheral Physical Addresses
|
||||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||||
|
|
||||||
|
@ -196,6 +196,9 @@ module lsu (
|
|||||||
logic SelUncachedAdr;
|
logic SelUncachedAdr;
|
||||||
assign IgnoreRequest = IgnoreRequestTLB | TrapM;
|
assign IgnoreRequest = IgnoreRequestTLB | TrapM;
|
||||||
|
|
||||||
|
// The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently
|
||||||
|
// use the same RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
|
||||||
|
|
||||||
if (`DMEM == `MEM_TIM) begin : dtim
|
if (`DMEM == `MEM_TIM) begin : dtim
|
||||||
// *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW.
|
// *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW.
|
||||||
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
|
// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
|
||||||
|
@ -398,7 +398,7 @@ module riscvassertions;
|
|||||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
||||||
assert (`F_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting float (F)");
|
assert (`F_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting float (F)");
|
||||||
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||||
assert (`DMEM == `MEM_CACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN");
|
assert (`DMEM == `MEM_CACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||||
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
||||||
assert (`FLEN<=`XLEN | `DMEM == `MEM_CACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported");
|
assert (`FLEN<=`XLEN | `DMEM == `MEM_CACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported");
|
||||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||||
|
Loading…
Reference in New Issue
Block a user