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Broken commit starting to address radix 2 issues

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This commit is contained in:
David Harris 2022-12-31 06:19:15 -08:00
parent 50af122909
commit 7c7d40ad63
2 changed files with 20 additions and 11 deletions
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4
pipelined/config/shared/wally-shared.vh
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@ -23,8 +23,8 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// division constants // division constants
`define RADIX 32'h4 `define RADIX 32'h2
`define DIVCOPIES 32'h4 `define DIVCOPIES 32'h2
// Memory synthesis configuration // Memory synthesis configuration
`define USE_SRAM 0 `define USE_SRAM 0

27
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -53,7 +53,7 @@ module fdivsqrtpreproc (
logic [`DIVb-1:0] XPreproc; logic [`DIVb-1:0] XPreproc;
logic [`DIVb:0] PreSqrtX; logic [`DIVb:0] PreSqrtX;
logic [`DIVb+3:0] DivX, SqrtX, PreShiftX; // Variations of dividend, to be muxed logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
logic [`NE+1:0] QeE; // Quotient Exponent (FP only) logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator
logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs
@ -63,8 +63,7 @@ module fdivsqrtpreproc (
logic signedDiv, NegQuotE; logic signedDiv, NegQuotE;
logic AsBit, BsBit, AsE, BsE, ALTBE; logic AsBit, BsBit, AsE, BsE, ALTBE;
logic [`XLEN-1:0] AE, BE, PosA, PosB; logic [`XLEN-1:0] AE, BE, PosA, PosB;
logic [`DIVBLEN:0] TotalIntBits, ZeroDiff, IntSteps, p; logic [`DIVBLEN:0] ZeroDiff, p;
logic [`LOGRK-1:0] IntTrunc, RightShiftX;
// Extract inputs, signs, zero, depending on W64 mode if applicable // Extract inputs, signs, zero, depending on W64 mode if applicable
assign signedDiv = ~Funct3E[0]; assign signedDiv = ~Funct3E[0];
@ -104,16 +103,26 @@ module fdivsqrtpreproc (
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
// calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps // calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
assign TotalIntBits = `LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
assign IntTrunc = TotalIntBits % `RK; // Truncation check for ceiling operator if (`LOGRK > 0) begin // more than 1 bit per cycle
assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc; // Number of steps for int div logic [`LOGRK-1:0] IntTrunc, RightShiftX;
assign nE = (IntSteps * `DIVCOPIES) - 1; // Fractional digits logic [`DIVBLEN:0] TotalIntBits, IntSteps;
assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK); // Right shift amount
assign TotalIntBits = `LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
assign IntTrunc = TotalIntBits % `RK; // Truncation check for ceiling operator
assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc; // Number of steps for int div
assign nE = (IntSteps * `DIVCOPIES) - 1; // Fractional digits
assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK); // Right shift amount
assign DivXShifted = DivX >> RightShiftX; // shift X to complete in nE steps
end else begin // radix 2 1 copy doesn't require shifting
assign nE = p + 1;
assign DivXShifted = DivX;
end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
// Selet integer or floating-point operands // Selet integer or floating-point operands
mux2 #(1) numzmux(XZeroE, AZeroE, MDUE, NumerZeroE); mux2 #(1) numzmux(XZeroE, AZeroE, MDUE, NumerZeroE);
mux2 #(`DIVb+4) xmux(PreShiftX, DivX >> RightShiftX, MDUE, X); mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, MDUE, X);
// pipeline registers // pipeline registers
flopen #(1) mdureg(clk, IFDivStartE, MDUE, MDUM); flopen #(1) mdureg(clk, IFDivStartE, MDUE, MDUM);