Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

put the FMA priority encoders into their own module

Browse Source
This commit is contained in:
Katherine Parry 2021-10-22 10:03:12 -07:00
parent 0dcca43f48
commit 7c7c0f538a
2 changed files with 24 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
wally-pipelined/src/fpu/fma.sv
View File

@ -381,15 +381,10 @@ module posloa(
// Apply function to determine Leading pattern // Apply function to determine Leading pattern
logic [3*`NF+6:0] pf; logic [3*`NF+6:0] f;
assign pf = T^{Z[3*`NF+5:0], 1'b0}; assign f = T^{Z[3*`NF+5:0], 1'b0};
logic [8:0] i; lzc lzc(.f, .Cnt(PCnt));
always_comb begin
i = 0;
while (~pf[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
PCnt = i;
end
endmodule endmodule
@ -410,17 +405,23 @@ module negloa(
logic [3*`NF+6:0] f; logic [3*`NF+6:0] f;
assign f = T^{~Z, 1'b0}; assign f = T^{~Z, 1'b0};
logic [8:0] i; lzc lzc(.f, .Cnt(NCnt));
always_comb begin
i = 0;
while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
NCnt = i;
end
endmodule endmodule
module lzc(
input logic [3*`NF+6:0] f,
output logic [8:0] Cnt // normalization shift count for the negitive result
);
logic [8:0] i;
always_comb begin
i = 0;
while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one
Cnt = i;
end
endmodule

16
wally-pipelined/testbench/tests.vh
View File

@ -85,10 +85,10 @@ string imperas32f[] = '{
"rv64f/I-FSW-01", "2000", "rv64f/I-FSW-01", "2000",
"rv64f/I-FCLASS-S-01", "2000", "rv64f/I-FCLASS-S-01", "2000",
"rv64f/I-FADD-S-01", "2000", "rv64f/I-FADD-S-01", "2000",
// "rv64f/I-FCVT-S-L-01", "2000", "rv64f/I-FCVT-S-L-01", "2000",
// "rv64f/I-FCVT-S-LU-01", "2000", "rv64f/I-FCVT-S-LU-01", "2000",
// "rv64f/I-FCVT-S-W-01", "2000", "rv64f/I-FCVT-S-W-01", "2000",
// "rv64f/I-FCVT-S-WU-01", "2000", "rv64f/I-FCVT-S-WU-01", "2000",
"rv64f/I-FCVT-L-S-01", "2000", "rv64f/I-FCVT-L-S-01", "2000",
"rv64f/I-FCVT-LU-S-01", "2000", "rv64f/I-FCVT-LU-S-01", "2000",
"rv64f/I-FCVT-W-S-01", "2000", "rv64f/I-FCVT-W-S-01", "2000",
@ -135,11 +135,11 @@ string imperas32f[] = '{
"rv64d/I-FSGNJX-D-01", "2000", "rv64d/I-FSGNJX-D-01", "2000",
"rv64d/I-FSQRT-D-01", "2000", "rv64d/I-FSQRT-D-01", "2000",
"rv64d/I-FSUB-D-01", "2000", "rv64d/I-FSUB-D-01", "2000",
// "rv64d/I-FCVT-D-L-01", "2000", "rv64d/I-FCVT-D-L-01", "2000",
// "rv64d/I-FCVT-D-LU-01", "2000", "rv64d/I-FCVT-D-LU-01", "2000",
"rv64d/I-FCVT-D-S-01", "2000", "rv64d/I-FCVT-D-S-01", "2000",
// "rv64d/I-FCVT-D-W-01", "2000", "rv64d/I-FCVT-D-W-01", "2000",
// "rv64d/I-FCVT-D-WU-01", "2000", "rv64d/I-FCVT-D-WU-01", "2000",
"rv64d/I-FCVT-L-D-01", "2000", "rv64d/I-FCVT-L-D-01", "2000",
"rv64d/I-FCVT-LU-D-01", "2000", "rv64d/I-FCVT-LU-D-01", "2000",
"rv64d/I-FCVT-S-D-01", "2000", "rv64d/I-FCVT-S-D-01", "2000",