From 0e1c53f9f6bdb360762663ac1a1099b6976e3efc Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 24 Jan 2024 12:24:33 -0800 Subject: [PATCH 01/20] Fixed tlbmisc testing with PBMTE = 0 --- tests/coverage/tlbmisc.S | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index db1435008..d993db43a 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -104,14 +104,17 @@ main: # jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0 li t0, 0x80805000 jalr ra, t0 + li t0, 0x80807000 # again, triggering setting access bit + jalr ra, t0 + # Good PBMT with menvcfg.PBMTE = 0 - li t0, 3 + li a0, 3 ecall # switch to machine mode li t5, 0x1 slli t5, t5, 62 csrc menvcfg, t5 # menvcfg.PBMTE = 0 - li t0, 1 + li a0, 1 ecall # switch back to supervisor mode li t0, 0x80806000 jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0 @@ -365,6 +368,7 @@ pagetable: .8byte 0x00000000200000C3 # valid r for VA 80802000 .8byte 0x00000000200000C9 # valid x for VA 80803000 .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol) - .8byte 0x000000002000000F # valid rwx for VA 80805000 for covering ITLB translate and UpdateDA + .8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate .8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT + .8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA From 2449e06e55121775cfdc01bb3a641c342ec9860e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jan 2024 21:03:41 -0800 Subject: [PATCH 02/20] Fixed FPU coverage, solved Issue 596 by misaligned AMO throwing access fault when misaligned non-amo are supported --- src/fpu/fpu.sv | 6 ++++-- src/mmu/mmu.sv | 26 +++++++++++++++++--------- tests/coverage/tlbmisc.S | 6 +++++- 3 files changed, 26 insertions(+), 12 deletions(-) diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index c304219aa..05d5f2e00 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -211,7 +211,8 @@ module fpu import cvw::*; #(parameter cvw_t P) ( {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}, {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes - assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); + assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10); + // ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z @@ -352,7 +353,8 @@ module fpu import cvw::*; #(parameter cvw_t P) ( .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM)); // FPU flag selection - to privileged - mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM); + //mux2 #(5) FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM); + mux2 #(5) FPUFlgMux({PreNVM, 4'b0}, PostProcFlgM, (FResSelM == 2'b01), SetFflagsM); mux2 #(P.FLEN) FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM); // M/W pipe registers diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index dffa7be76..6957ed315 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -74,6 +74,8 @@ module mmu import cvw::*; #(parameter cvw_t P, logic TLBPageFault; // Page fault from TLB logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults logic [1:0] PBMemoryType; // PBMT field of PTE during TLB hit, or 00 otherwise + logic AmoMisalignedCausesAccessFaultM; // Misaligned AMO is not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM + logic AmoAccessM; // AMO access detected when ReadAccessM and WriteAccessM are simultaneously asserted // only instantiate TLB if Virtual Memory is supported if (P.VIRTMEM_SUPPORTED) begin:tlb @@ -123,24 +125,30 @@ module mmu import cvw::*; #(parameter cvw_t P, assign PMPLoadAccessFaultM = 0; end - assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault - - // Access faults - // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. - assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss; - assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~TLBMiss; - assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss; + assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault + assign AmoAccessM = ReadAccessM & WriteAccessM; // Misaligned faults - always_comb // exclusion-tag: immu-wordaccess + always_comb // exclusion-tag: immu-wordaccess case(Size[1:0]) 2'b00: DataMisalignedM = 0; // lb, sb, lbu 2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu 2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu 2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd endcase + // When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); - assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & (~(P.ZICCLSM_SUPPORTED & Cacheable) | ReadAccessM); // Misaligned AMO faults even if ZICCLSM supported + assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); // Store and AMO both assert WriteAccess + + // Access faults + // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. + assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss; + assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~TLBMiss; + // a misaligned AMO causes an access fault rather than a misaligned fault if a misaligned load/store is handled in hardware + // this is subtle - see privileged spec 3.6.3.3 + // AMO is detected as ReadAccess & WriteAccess + assign AmoMisalignedCausesAccessFaultM = DataMisalignedM & AmoAccessM & (P.ZICCLSM_SUPPORTED & Cacheable); + assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM | AmoMisalignedCausesAccessFaultM) & ~TLBMiss; // Specify which type of page fault is occurring assign InstrPageFaultF = TLBPageFault & ExecuteAccessF; diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index d993db43a..d62a4f2d6 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -95,7 +95,7 @@ main: sw t1, 0(t0) # write to page jalr ra, t0 # jump to page - # Nonleaf PTE has PBMT != 0 # this should cause a page fault during page walking. However, as of issue 546 1/1/24, both ImperasDV and Wally don't detect this + # Nonleaf PTE has PBMT != 0 causes a page fault during page walking. H li t0, 0x80600000 lw t1, 0(t0) # read from page sw t1, 0(t0) # write to page @@ -107,6 +107,10 @@ main: li t0, 0x80807000 # again, triggering setting access bit jalr ra, t0 + # atomic access to uncachable memory + #li t0, 0x80806000 + #sd zero, 0(t0) + #amoadd.w t1, t0, (t0) # Good PBMT with menvcfg.PBMTE = 0 li a0, 3 From 1c1d3eb9569a8de46f68e74ee88b2e92bd7e4f33 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Jan 2024 10:46:38 -0800 Subject: [PATCH 03/20] HPTW coverage improvements --- sim/coverage-exclusions-rv64gc.do | 24 +++++++++++++++ sim/imperas.ic | 2 +- src/mmu/hptw.sv | 29 +++++++++--------- tests/coverage/tlbmisc.S | 49 +++++++++++++++++++++---------- 4 files changed, 72 insertions(+), 32 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index d8e05c7d4..d64b730be 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -246,6 +246,30 @@ coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerang # never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18 +############### +# HPTW exclusions +############### + +# RV64GC HPTW never starts at L1_ADR +set line [GetLineNum ../src/mmu/hptw.sv "InitialWalkerState == L1_ADR"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item c 1 -feccondrow 2 + +# Never possible to get a page fault when neither reading nor writing +set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWLoadPageFault"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 7 + +# Never possible to get a store page fault from an ITLB walk +set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWStoreAmoPageFault"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3 + +# Never possible to get Access = 0 on a nonleaf PTE with no OtherPageFault (because InvalidRead/Write will be 1 on the nonleaf) +set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWUpdateDA"] +coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3 + +############### +# Other exclusions +############### + # IMMU PMP does not support CBO instructions coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"] coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] diff --git a/sim/imperas.ic b/sim/imperas.ic index 4cebcf526..51344b75a 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -11,7 +11,7 @@ --override cpu/mvendorid=0x602 --override cpu/marchid=0x24 --override refRoot/cpu/tvec_align=64 ---override refRoot/cpu/envcfg_mask=1 +--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written # bit manipulation --override cpu/add_Extensions=B diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 82eeaef87..2a99b14fd 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -93,7 +93,6 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.PA_BITS-1:0] HPTWReadAdr; logic SelHPTWAdr; logic [P.XLEN+1:0] HPTWAdrExt; - logic ITLBMissOrUpdateDAF; logic DTLBMissOrUpdateDAM; logic LSUAccessFaultM; logic [P.PA_BITS-1:0] HPTWAdr; @@ -113,12 +112,12 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // map hptw access faults onto either the original LSU load/store fault or instruction access fault assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM; assign HPTWFaultM = LSUAccessFaultM | PBMTFaultM; - assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; + assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; assign HPTWStoreAmoAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[0]; assign HPTWInstrAccessFault = LSUAccessFaultM & ~DTLBWalk; - assign HPTWLoadPageFault = PBMTFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; - assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0]; - assign HPTWInstrPageFault = PBMTFaultM & ~DTLBWalk; + assign HPTWLoadPageFault = PBMTFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0]; + assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0]; + assign HPTWInstrPageFault = PBMTFaultM & ~DTLBWalk; flopr #(7) HPTWAccesFaultReg(clk, reset, {TakeHPTWFault, HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault}, @@ -127,17 +126,18 @@ module hptw import cvw::*; #(parameter cvw_t P) ( assign TakeHPTWFault = WalkerState != IDLE; - assign LoadAccessFaultM = TakeHPTWFault ? HPTWLoadAccessFaultDelay : LSULoadAccessFaultM; + // Improve timing by taking HPTW faults off critical path because these are multicycle operations anyway + assign LoadAccessFaultM = TakeHPTWFault ? HPTWLoadAccessFaultDelay : LSULoadAccessFaultM; assign StoreAmoAccessFaultM = TakeHPTWFault ? HPTWStoreAmoAccessFaultDelay : LSUStoreAmoAccessFaultM; assign HPTWInstrAccessFaultF = TakeHPTWFault ? HPTWInstrAccessFaultDelay : 1'b0; - assign LoadPageFaultM = TakeHPTWFault ? HPTWLoadPageFaultDelay : LSULoadPageFaultM; - assign StoreAmoPageFaultM = TakeHPTWFault ? HPTWStoreAmoPageFaultDelay : LSUStoreAmoPageFaultM; - assign HPTWInstrPageFaultF = TakeHPTWFault ? HPTWInstrPageFaultDelay : 1'b0; + assign LoadPageFaultM = TakeHPTWFault ? HPTWLoadPageFaultDelay : LSULoadPageFaultM; + assign StoreAmoPageFaultM = TakeHPTWFault ? HPTWStoreAmoPageFaultDelay : LSUStoreAmoPageFaultM; + assign HPTWInstrPageFaultF = TakeHPTWFault ? HPTWInstrPageFaultDelay : 1'b0; // Extract bits from CSRs and inputs assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]; assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0]; - assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissOrUpdateDAF); + assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissF); // Determine which address to translate mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr); @@ -203,7 +203,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // memory access. If there is the PTE needs to be updated seting Access // and possibly also Dirty. Dirty is set if the operation is a store/amo. // However any other fault should not cause the update, and updates are in software when ENVCFG_ADUE = 0 - assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault; + assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault; assign HPTWRW[0] = (WalkerState == UPDATE_PTE); // HPTWRW[0] will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA; // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 @@ -283,7 +283,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) - IDLE: if (TLBMiss & ~DCacheBusStallM) NextWalkerState = InitialWalkerState; + IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // first access in SV48 L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD; @@ -294,7 +294,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD; else if(HPTWFaultM) NextWalkerState = FAULT; else NextWalkerState = L1_ADR; - L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 + L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 else NextWalkerState = LEAF; L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD; else if(HPTWFaultM) NextWalkerState = FAULT; @@ -320,9 +320,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high. assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay; - assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); + assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); - assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF); assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM); // HTPW address/data/control muxing diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index d62a4f2d6..a51436e3a 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -123,6 +123,27 @@ main: li t0, 0x80806000 jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0 + # Load and AMO operation on page table entry that causes access fault + li t0, 0x81000000 + lw t1, 0(t0) + sfence.vma + amoadd.w t0, t0, 0(t0) + + # Access fault on top level PTE + li t0, 0x1000000000 + lw t1, 0(t0) + + # Access fault on megapage + li t0, 0x81400000 + lw t1, 0(t0) + + # AMO operation on page table entry that causes page fault due to malformed PBMT + li t0, 0x81200000 + jalr t0 # Attempt to fetch instruction from address causing faulty page walk + lw t1, 0(t0) + sfence.vma + amoadd.w t0, t0, 0(t0) + # change back to default trap handler after checking everything that might cause an instruction page fault jal changetodefaulthandler @@ -178,8 +199,6 @@ main: li a0, 1 ecall - - # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry ecall @@ -237,32 +256,30 @@ ipf: .align 16 # root Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid + .8byte 0x200044C1 # 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 + .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000 # next page table at 0x80011000 .align 12 .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 - .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 + .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000 .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 # Next page table at 0x80012000 for gigapage at 0x80000000 .align 12 - .8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages) + .8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages Page table at 80013000) .8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage) - .8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages) + .8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages page table at 0x80014000) .8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) - .8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) - .8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) + .8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz . page table at 0x80015000) + .8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000. page table at 0x80013000) .8byte 0x0F00000020004CCF # for VA starting at 80C00000 (bad reserved field in bits 60:54) - .8byte 0x000000002000000F # for VA starting at 80E00000 (not dirty or accessed) - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 - .8byte 0x0000000020004CC1 + .8byte 0x000000002000000F # for VA starting at 80E00000 (megapage not dirty or accessed) + .8byte 0x0000000000004CC1 # for VA starting at 81000000 (nonleaf pointing to unimplemented memory causes access fault) + .8byte 0x4000000020004CC1 # for VA starting at 81200000 (nonleaf with PBMT nonzero causes page fault) + .8byte 0x00000000000000CF # for VA starting at 81400000 (megapage with access fault) .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 @@ -288,7 +305,7 @@ pagetable: .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 -# Leaf page table at 0x80013000 with NAPOT pages +# Leaf page table at 0x80013000 with 64 KiB NAPOT pages .align 12 #80000000 .8byte 0xA0000000200020CF From 3620a10c0be7135db500db4322cd58a07cb48636 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Jan 2024 14:55:51 -0800 Subject: [PATCH 04/20] Improved hptw and I CacheWays coverage --- sim/coverage-exclusions-rv64gc.do | 8 ++++++++ src/cache/cache.sv | 5 +++-- src/cache/cacheway.sv | 6 +++--- tests/coverage/fround.S | 18 +++++++++++++++++ tests/coverage/ifu.S | 23 ++++++++++++++++++++++ tests/coverage/tlbmisc.S | 32 +++++++++++++++++++++++++++++-- 6 files changed, 85 insertions(+), 7 deletions(-) create mode 100644 tests/coverage/fround.S diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index d64b730be..06e1b6e9f 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -93,6 +93,11 @@ for {set i 0} {$i < $numcacheways} {incr i} { # below: flushD can't go high during an icache write b/c of pipeline stall coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4 + # No CMO to clear valid bits of I$ + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"] + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1 + # No dirty ways in read-only I$ + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1 } ## D$ Exclusions. @@ -246,6 +251,9 @@ coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerang # never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18 + + + ############### # HPTW exclusions ############### diff --git a/src/cache/cache.sv b/src/cache/cache.sv index c8f707904..86aba57a0 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -199,7 +199,7 @@ module cache import cvw::*; #(parameter cvw_t P, // Flush logic ///////////////////////////////////////////////////////////////////////////////////////////// - if (!READ_ONLY_CACHE) begin:flushlogic + if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed // Flush address (line number) assign ResetOrFlushCntRst = reset | FlushCntRst; flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr); @@ -213,7 +213,8 @@ module cache import cvw::*; #(parameter cvw_t P, else assign NextFlushWay = FlushWay[NUMWAYS-1]; assign FlushWayFlag = FlushWay[NUMWAYS-1]; end // block: flushlogic - else begin:flushlogic + else begin:flushlogic // I$ is never flushed because it is never dirty + assign FlushWay = 0; assign FlushWayFlag = 0; assign FlushAdrFlag = 0; end diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index d7a5ae34a..cd9d08687 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -100,7 +100,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, ///////////////////////////////////////////////////////////////////////////////////////////// assign SetValidWay = SetValid & SelData; - assign ClearValidWay = ClearValid & SelData; + assign ClearValidWay = ClearValid & SelData; // exclusion-tag: icache ClearValidWay assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn @@ -121,7 +121,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, // AND portion of distributed tag multiplexer assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux assign HitDirtyWay = Dirty & ValidWay; - assign DirtyWay = SelDirty & HitDirtyWay; + assign DirtyWay = SelDirty & HitDirtyWay; // exclusion-tag: icache DirtyWay assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay); @@ -163,7 +163,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, ValidWay <= #1 ValidBits[CacheSetTag]; if(InvalidateCache) ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway else if (SetValidEN) ValidBits[CacheSetData] <= #1 SetValidWay; - else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0; + else if (ClearValidEN) ValidBits[CacheSetData] <= #1 '0; // exclusion-tag: icache ClearValidBits end end diff --git a/tests/coverage/fround.S b/tests/coverage/fround.S new file mode 100644 index 000000000..7d469d773 --- /dev/null +++ b/tests/coverage/fround.S @@ -0,0 +1,18 @@ +// fround.s + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + + bseti t0, zero, 14 # turn on FPU + csrs mstatus, t0 + + # test fround behavior on NaN + li t0, 0x7FC00001 + fmv.w.x ft0, t0 + fround.s ft1, ft0 + j done + +.align 10 +data_start: diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index f387774bf..0866326cc 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -74,8 +74,31 @@ main: .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else + # exercise all the cache ways + j way0code +# stress test cache ways by loading stuff from each one and then doing fence.i to invalidate +.align 12 +way0code: + jal way1code + fence.i + j done +.align 12 +way1code: + j way2code + +.align 12 +way2code: + j way3code + +.align 12 +way3code: + j way00code + +.align 12 +way00code: + ret j done diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index a51436e3a..eeb1c7d34 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -133,10 +133,18 @@ main: li t0, 0x1000000000 lw t1, 0(t0) + # Bad PBMT on top level PTE + li t0, 0x1800000000 + lw t1, 0(t0) + # Access fault on megapage li t0, 0x81400000 lw t1, 0(t0) + # Access fault walking page tables at megapage level + li t0, 0xC0000000 + lw t1, 0(t0) + # AMO operation on page table entry that causes page fault due to malformed PBMT li t0, 0x81200000 jalr t0 # Attempt to fetch instruction from address causing faulty page walk @@ -144,6 +152,13 @@ main: sfence.vma amoadd.w t0, t0, 0(t0) + # point top-level page table to an illegal address and verify it faults + li t0, 0x9000000000070000 # trap handler at non-existing memory location + csrw satp, t0 # should cause trap + sfence.vma + nop + + # change back to default trap handler after checking everything that might cause an instruction page fault jal changetodefaulthandler @@ -199,6 +214,9 @@ main: li a0, 1 ecall + + + # wrap up li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry ecall @@ -229,12 +247,14 @@ instructionpagefaulthandler: csrw mepc, ra # go back to calling function mret -.align 4 # trap handlers must be aligned to multiple of 4 +.align 4 # trap handlers must be aligned to multiple of 16 ipf_handler: # Load trap handler stack pointer tp csrrw tp, mscratch, tp # swap MSCRATCH and tp sd t0, 0(tp) # Save t0 and t1 on the stack sd t1, -8(tp) + li t5, 0x9000000000080010 + csrw satp, t5 # make sure we are pointing to the root page table csrr t0, mcause # Check the cause li t1, 8 # is it an ecall trap? andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 @@ -251,20 +271,28 @@ ipf: csrrw tp, mscratch, tp # restore tp mret # return from trap +.align 4 # trap handlers must be aligned to multiple of 16 +fixsatptraphandler: + li t5, 0x9000000000080010 # fix satp entry to normal page table root + csrw satp, t5 + mret + .data .align 16 # root Page table situated at 0x80010000 pagetable: - .8byte 0x200044C1 # 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid + .8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000 .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000 + .8byte 0x40000000200044C1 # Bad PBMT at VA 0x180_0000000 # next page table at 0x80011000 .align 12 .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000 .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000 .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000 + .8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault # Next page table at 0x80012000 for gigapage at 0x80000000 From e8dde265be782d89080036a8d4805e46d09fbc82 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Jan 2024 16:14:36 -0800 Subject: [PATCH 05/20] More coverage: CacheWay --- sim/coverage-exclusions-rv64gc.do | 2 ++ src/cache/cacheway.sv | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 06e1b6e9f..e39128f5a 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -109,6 +109,8 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 + # InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2 # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW. diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index cd9d08687..9c5523cec 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -122,7 +122,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux assign HitDirtyWay = Dirty & ValidWay; assign DirtyWay = SelDirty & HitDirtyWay; // exclusion-tag: icache DirtyWay - assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; + assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; // exclusion-tag: dcache HitWay flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay); From 45e2317636eda2e07ddf50bffdec6c6cb995e285 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Jan 2024 05:38:11 -0800 Subject: [PATCH 06/20] Added Wally github address to header comments --- bin/CModelBTBAccuracy.sh | 1 + bin/CModelBranchAccuracy.sh | 1 + bin/CacheSim.py | 1 + bin/SeparateBranch.sh | 1 + bin/derivgen.pl | 58 ++++++++++++++++++ bin/elf2hex.sh | 1 + bin/exe2memfile.pl | 1 + bin/fparchtest.sh | 21 +++++++ bin/imperas-one-time.sh | 1 + bin/libppa.pl | 1 + bin/parseHPMC.py | 1 + bin/testcount.pl | 1 + bin/testlist.pl | 1 + bin/vclean.pl | 1 + bin/wally-tool-chain-install.sh | 1 + config/derivlist.txt | 73 +++++++++++++++++++++++ docs/Dockerfile | 1 + fpga/generator/insert_debug_comment.sh | 1 + fpga/probe | 1 + fpga/proberange | 1 + fpga/probes | 1 + gitflow.txt | 1 + sim/coverage-exclusions-rv64gc.do | 1 + sim/rv64gc_CacheSim.py | 1 + sim/sim-imperas | 1 + src/cache/cache.sv | 1 + src/cache/cacheLRU.sv | 1 + src/cache/cachefsm.sv | 1 + src/cache/cacheway.sv | 1 + src/cache/subcachelineread.sv | 1 + src/ebu/ahbcacheinterface.sv | 1 + src/ebu/ahbinterface.sv | 1 + src/ebu/buscachefsm.sv | 1 + src/ebu/busfsm.sv | 1 + src/ebu/controllerinput.sv | 1 + src/ebu/ebu.sv | 1 + src/ebu/ebufsmarb.sv | 1 + src/fpu/fclassify.sv | 1 + src/fpu/fcmp.sv | 1 + src/fpu/fctrl.sv | 1 + src/fpu/fdivsqrt/fdivsqrt.sv | 1 + src/fpu/fdivsqrt/fdivsqrtcycles.sv | 1 + src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 1 + src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 1 + src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 1 + src/fpu/fdivsqrt/fdivsqrtfsm.sv | 1 + src/fpu/fdivsqrt/fdivsqrtiter.sv | 1 + src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 1 + src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 1 + src/fpu/fdivsqrt/fdivsqrtstage2.sv | 1 + src/fpu/fdivsqrt/fdivsqrtstage4.sv | 1 + src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 1 + src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 1 + src/fpu/fdivsqrt/fdivsqrtuslc2.sv | 1 + src/fpu/fdivsqrt/fdivsqrtuslc4.sv | 1 + src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv | 1 + src/fpu/fhazard.sv | 1 + src/fpu/fli.sv | 1 + src/fpu/fma/fma.sv | 1 + src/fpu/fma/fmaadd.sv | 1 + src/fpu/fma/fmaalign.sv | 1 + src/fpu/fma/fmaexpadd.sv | 1 + src/fpu/fma/fmalza.sv | 1 + src/fpu/fma/fmamult.sv | 1 + src/fpu/fma/fmasign.sv | 1 + src/fpu/fpu.sv | 1 + src/fpu/fregfile.sv | 1 + src/fpu/fsgninj.sv | 1 + src/fpu/postproc/cvtshiftcalc.sv | 1 + src/fpu/postproc/divshiftcalc.sv | 1 + src/fpu/postproc/flags.sv | 1 + src/fpu/postproc/fmashiftcalc.sv | 1 + src/fpu/postproc/negateintres.sv | 1 + src/fpu/postproc/normshift.sv | 1 + src/fpu/postproc/postprocess.sv | 1 + src/fpu/postproc/resultsign.sv | 1 + src/fpu/postproc/round.sv | 1 + src/fpu/postproc/roundsign.sv | 1 + src/fpu/postproc/shiftcorrection.sv | 1 + src/fpu/postproc/specialcase.sv | 1 + src/fpu/unpack.sv | 1 + src/fpu/unpackinput.sv | 1 + src/generic/adder.sv | 1 + src/generic/aplusbeq0.sv | 1 + src/generic/arrs.sv | 1 + src/generic/binencoder.sv | 1 + src/generic/clockgater.sv | 1 + src/generic/counter.sv | 1 + src/generic/csa.sv | 1 + src/generic/decoder.sv | 1 + src/generic/flop/flop.sv | 1 + src/generic/flop/flopen.sv | 1 + src/generic/flop/flopenl.sv | 1 + src/generic/flop/flopenr.sv | 1 + src/generic/flop/flopenrc.sv | 1 + src/generic/flop/flopens.sv | 1 + src/generic/flop/flopr.sv | 1 + src/generic/flop/floprc.sv | 1 + src/generic/flop/synchronizer.sv | 1 + src/generic/lzc.sv | 1 + src/generic/mem/ram1p1rwbe.sv | 1 + src/generic/mem/ram1p1rwbe_64x128.sv | 1 + src/generic/mem/ram1p1rwbe_64x22.sv | 1 + src/generic/mem/ram1p1rwbe_64x44.sv | 1 + src/generic/mem/ram1p1rwe.sv | 1 + src/generic/mem/ram2p1r1wbe.sv | 1 + src/generic/mem/ram2p1r1wbe_1024x36.sv | 1 + src/generic/mem/ram2p1r1wbe_1024x68.sv | 1 + src/generic/mem/ram2p1r1wbe_128x64.sv | 1 + src/generic/mem/ram2p1r1wbe_512x64.sv | 1 + src/generic/mem/ram2p1r1wbe_64x32.sv | 1 + src/generic/mem/rom1p1r.sv | 1 + src/generic/mem/rom1p1r_128x32.sv | 1 + src/generic/mem/rom1p1r_128x64.sv | 1 + src/generic/mux.sv | 1 + src/generic/neg.sv | 1 + src/generic/onehotdecoder.sv | 1 + src/generic/or_rows.sv | 1 + src/generic/priorityonehot.sv | 1 + src/generic/prioritythermometer.sv | 1 + src/hazard/hazard.sv | 1 + src/ieu/alu.sv | 1 + src/ieu/bmu/bitmanipalu.sv | 1 + src/ieu/bmu/bitreverse.sv | 1 + src/ieu/bmu/bmuctrl.sv | 1 + src/ieu/bmu/byteop.sv | 1 + src/ieu/bmu/clmul.sv | 1 + src/ieu/bmu/cnt.sv | 1 + src/ieu/bmu/ext.sv | 1 + src/ieu/bmu/popcnt.sv | 1 + src/ieu/bmu/zbb.sv | 1 + src/ieu/bmu/zbc.sv | 1 + src/ieu/comparator.sv | 1 + src/ieu/controller.sv | 1 + src/ieu/datapath.sv | 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src/mmu/pmachecker.sv | 1 + src/mmu/pmpadrdec.sv | 1 + src/mmu/pmpchecker.sv | 1 + src/mmu/tlb/tlb.sv | 1 + src/mmu/tlb/tlbcam.sv | 1 + src/mmu/tlb/tlbcamline.sv | 1 + src/mmu/tlb/tlbcontrol.sv | 1 + src/mmu/tlb/tlblru.sv | 1 + src/mmu/tlb/tlbmixer.sv | 1 + src/mmu/tlb/tlbram.sv | 1 + src/mmu/tlb/tlbramline.sv | 1 + src/mmu/tlb/vm64check.sv | 1 + src/privileged/csr.sv | 1 + src/privileged/csrc.sv | 1 + src/privileged/csri.sv | 1 + src/privileged/csrm.sv | 1 + src/privileged/csrs.sv | 1 + src/privileged/csrsr.sv | 1 + src/privileged/csru.sv | 1 + src/privileged/privdec.sv | 1 + src/privileged/privileged.sv | 1 + src/privileged/privmode.sv | 1 + src/privileged/privpiperegs.sv | 1 + src/privileged/trap.sv | 1 + src/uncore/ahbapbbridge.sv | 1 + src/uncore/clint_apb.sv | 1 + src/uncore/gpio_apb.sv | 1 + src/uncore/plic_apb.sv | 1 + src/uncore/ram_ahb.sv | 1 + src/uncore/rom_ahb.sv | 1 + src/uncore/uartPC16550D.sv | 1 + src/uncore/uart_apb.sv | 1 + src/uncore/uncore.sv | 1 + src/wally/wallypipelinedcore.sv | 1 + src/wally/wallypipelinedsoc.sv | 1 + studies/comparator.sv | 1 + synthDC/extractArea.pl | 1 + tests/coverage/WALLY-init-lib.h | 1 + tests/coverage/csrwrites.S | 1 + tests/coverage/dcache2.S | 1 + tests/coverage/ebu.S | 1 + tests/coverage/fpu.S | 1 + tests/coverage/ieu.S | 1 + tests/coverage/ifu.S | 1 + tests/coverage/ifuCamlineWrite.S | 1 + tests/coverage/lsu.S | 1 + tests/coverage/priv.S | 1 + tests/coverage/tlbASID.S | 1 + tests/coverage/tlbGLB.S | 1 + tests/coverage/tlbGP.S | 1 + tests/coverage/tlbKP.S | 1 + tests/coverage/tlbM3.S | 1 + tests/coverage/tlbMP.S | 1 + tests/coverage/tlbNAPOT.S | 1 + tests/coverage/tlbTP.S | 1 + tests/coverage/tlbmisc.S | 1 + tests/coverage/vm64check.S | 1 + tests/custom/cacheSimTest/CacheSimTest.py | 1 + 230 files changed, 379 insertions(+) create mode 100644 bin/derivgen.pl create mode 100755 bin/fparchtest.sh create mode 100644 config/derivlist.txt diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 479340eb2..20a65bf98 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean for btb accuracy ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 8253891bb..2fb7b164a 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 24857837b..f6b2cb7e1 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index c81ba32c9..87648589f 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -12,6 +12,7 @@ ## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/derivgen.pl b/bin/derivgen.pl new file mode 100644 index 000000000..fcb6f8179 --- /dev/null +++ b/bin/derivgen.pl @@ -0,0 +1,58 @@ +#!/bin/perl -W + +########################################### +## derivgen.pl +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh +## derivative configurations from the base configurations +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +use strict; +use warnings; +import os; + +if ($#ARGV != 0) { + die("Usage: $0 workpath [e.g. $0 \$WALLY/addins/riscv-arch-test/work") +} +my $mypath = $ARGV[0]; +my @dirs = glob($mypath.'/*/*'); +foreach my $dir (@dirs) { + $dir =~ /.*\/(.*)\/(.*)/; + my $arch = $1; + my $ext = $2; + my $contents = `grep --with-filename ":" $dir/*.objdump`; + my @lines = split('\n', $contents); + print "$arch/$ext"; + foreach my $line (@lines) { + $line =~ /.*\/(.*)\.elf.objdump:(\S*)/; + my $fname = $1; + my $adr = $2; + my $partialaddress = substr($adr, -6); + print ",\n\t\t\"$arch/$ext/$fname\", \"$partialaddress\""; + } + print("\n\n"); +} diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh index 56f286135..d36678e9c 100755 --- a/bin/elf2hex.sh +++ b/bin/elf2hex.sh @@ -9,6 +9,7 @@ ## Imperas and riscv-arch-test benchmarks ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 2af665bbd..4f04ff512 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -11,6 +11,7 @@ ## to read into a Verilog simulation with $readmemh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/fparchtest.sh b/bin/fparchtest.sh new file mode 100755 index 000000000..7ea690e96 --- /dev/null +++ b/bin/fparchtest.sh @@ -0,0 +1,21 @@ +#!/usr/bin/bash +# +# fparchtest.sh +# David_Harris@hmc.edu 26 December 2023 +# +# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests + +# Set up with (not retested) +# cd ~/repos +# git clone https://github.com/riscv/riscv-ctg.git +# git clone https://github.com/riscv/riscv-isac.git +# pip3 install git+https://github.com/riscv/riscv-ctg.git +# pip3 install git+https://github.com/riscv/riscv-isac.git +# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg + +RISCVCTG=/home/harris/repos/riscv-ctg + +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32 +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32 +riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug +#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh index 404636d7c..339b4c74f 100755 --- a/bin/imperas-one-time.sh +++ b/bin/imperas-one-time.sh @@ -9,6 +9,7 @@ ## Purpose: One time setup script for running imperas. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/libppa.pl b/bin/libppa.pl index ccf4f1548..9f1e8515d 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -13,6 +13,7 @@ ## and for TSMC change the $cellname to the actual name of the inverter. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 7e8eb7cde..73535c430 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -8,6 +8,7 @@ ## Purpose: Parses the performance counters from a modelsim trace. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testcount.pl b/bin/testcount.pl index e801ed0e4..139902dd3 100755 --- a/bin/testcount.pl +++ b/bin/testcount.pl @@ -12,6 +12,7 @@ ## and count how many tests are in each ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testlist.pl b/bin/testlist.pl index 655cdd6f8..c72b96961 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -11,6 +11,7 @@ ## and generate a list of tests and signature addresses for tests.vh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/vclean.pl b/bin/vclean.pl index f947ed9d0..294d1d435 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -11,6 +11,7 @@ ## verilator should do this, but it also reports partially used signals ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7ccb1a138..6e7e4c8e9 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -10,6 +10,7 @@ ## Purpose: Open source tool chain installation script ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/config/derivlist.txt b/config/derivlist.txt new file mode 100644 index 000000000..554697e62 --- /dev/null +++ b/config/derivlist.txt @@ -0,0 +1,73 @@ +########################################### +## derivlist.txt +## Wally Derivative Configuration List +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Used by sim/make deriv to generate derivative configurations +## in config/deriv that are variants of the base configurations. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Format: +# begin a derivative with "deriv +# Followed by a list of parameters and their new value in the derivative configuration +# All other parameter values are inherited from the original configuration +# If is not empty, all the list of parameter changes in the inherited +# configuration are also applied to this configuration + +deriv buildroot rv64gc +RESET_VECTOR 64'h1000 +UNCORE_RAM_RANGE 64'h0FFFFFFF +UNCORE_RAM_PRELOAD 1 +GPIO_LOOPBACK_TEST 0 +SPI_LOOBACK_TEST 0 +UART_PRESCALE 0 +PLIC_NUM_SRC 32'd53 + +deriv fpga rv64gc buildroot +BOOTROM_PRELOAD 1 +UNCORE_RAM_BASE 64'h2000 +UNCORE_RAM_RANGE 64'hFFF +EXT_MEM_SUPPORTED 1 +EXT_MEM_BASE 64'h80000000 +EXT_MEM_RANGE 64'h0FFFFFFF +SDC_SUPPORTED 1 +PLIC_SDC_ID 32'd20 +BPRED_SIZE 32'd12 + +deriv syn_rv32e rv32e +DTIM_RANGE 32'h1FF +IROM_RANGE 32'h1FF +BOOTROM_RANGE 32'h1FF +UNCORE_RAM_RANGE 32'h1FF +BOOTROM_RANGE 32'h1FF +WAYSIZEINBYTES 32'd512 +NUMWAYS 32'd1 +BPRED_SIZE 32'd5 +BTB_SIZE 32'd5 + +deriv syn_rv32i rv32i syn_rv32e +deriv syn_rv32imc rv32imc syn_rv32e +deriv syn_rv32gc rv32gc syn_rv32e +deriv syn_rv64i rv64i syn_rv32e +deriv syn_rv64gc rv64gc syn_rv32e diff --git a/docs/Dockerfile b/docs/Dockerfile index b06f9ad67..8df933363 100755 --- a/docs/Dockerfile +++ b/docs/Dockerfile @@ -7,6 +7,7 @@ ## Purpose: Dockerfile for Wally docker container creation ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 66c232e16..35fa05a02 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -7,6 +7,7 @@ ## Modified: 20 January 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probe b/fpga/probe index 21e5d8240..1cf1104c1 100755 --- a/fpga/probe +++ b/fpga/probe @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/proberange b/fpga/proberange index 715cba46e..73bfc3383 100755 --- a/fpga/proberange +++ b/fpga/proberange @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probes b/fpga/probes index 83c2ddf7c..1ea571057 100755 --- a/fpga/probes +++ b/fpga/probes @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/gitflow.txt b/gitflow.txt index 57300830a..f6f70de74 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -1,5 +1,6 @@ ########################################### ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index e39128f5a..b6eb0214f 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -7,6 +7,7 @@ #// For example, signals hardwired to 0 should not be checked for toggle coverage #// #// A component of the CORE-V-WALLY configurable RISC-V project. +#// https://github.com/openhwgroup/cvw #// #// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University #// diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 42f21c8c6..bc75fc13a 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Run the cache simulator on each rv64gc test suite in turn. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/sim-imperas b/sim/sim-imperas index aa1dc3a01..556cdebf6 100755 --- a/sim/sim-imperas +++ b/sim/sim-imperas @@ -10,6 +10,7 @@ ## Purpose: Run wally with imperas ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 86aba57a0..4a97a29d4 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index b593f2ae6..70f129d4b 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 07494c2a9..0d3b2c0e0 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 9c5523cec..b2be76838 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index db80cfc83..95920ec7e 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 5f2dff313..89135966e 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index df84175f0..8852b52c3 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 8d434c678..e9dadb515 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 81d11715e..e49a6313a 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 60df9e44b..67e4795a6 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 4a1b00b57..d9a95fc3d 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 302c4752f..55ba9a506 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index bfc7a53dd..f35f71869 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 227676203..0944090fc 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 705a112d1..60edbfd8a 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index a4e20f229..85a1a5494 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 1e6eda56c..2649632eb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index bbb2d9360..d24b490ab 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index cf398f570..bc9dce536 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index e2cec1ab4..a04523e58 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index cd890ed87..f7d21e5d8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 863d94837..20f88b6cb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5a40a3bdc..c3954bc0a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 939b9c133..1c56e04e5 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 40a2a5a01..c3d6e210c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index a24c1155f..0d7a722ff 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index c895fa2ce..032bb700e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index b12b9174b..19e322013 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index e4fcfeadf..2d4cd5e48 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index b44b34a35..63ea5aae2 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index ccb5e618a..c0cbe9b1c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index 14f8c945f..e68934294 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index e61415388..dedb230b0 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 16 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index a6e87a240..321bfe8bc 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 98ff21491..1ad3b0b83 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index efc4a4c5f..9001742e4 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index bb7bf2437..06ac7e290 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 66659665a..822f857c2 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -10,6 +10,7 @@ // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 91f255b87..8ce492f03 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index aca6c8f8c..2a8b827d2 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 05d5f2e00..90ec10dee 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 6ab14df20..2de41088b 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index cee13f4f9..4fe03522b 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 77b8543fd..d3ce45f2e 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index 9e5de7173..0a222d724 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index 40fe887ca..21160e0c5 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index b13b6d3da..e16f51615 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index d0aaf760b..5ca848b0b 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f24a75fe1..f235d4d5b 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 1d51fdf85..e30058538 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 0dd22c1f4..2d5587dcf 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index 445f563d9..aae3d68f4 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 6c1135602..521675ac4 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index f5860b42d..275ee4cff 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index ba30daaf2..0a787c27c 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 145d6a701..eab224dd9 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index b3d7f901e..ca58c9d9f 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/adder.sv b/src/generic/adder.sv index 4d341d6c1..f499eca88 100644 --- a/src/generic/adder.sv +++ b/src/generic/adder.sv @@ -7,6 +7,7 @@ // Purpose: Adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index f8d675b33..dc5f6450c 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -7,6 +7,7 @@ // Purpose: Determine if A+B = 0. Used in FP divider. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index dd473b307..cbff0e82b 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -10,6 +10,7 @@ // rising edge, but then syncs the falling edge to the posedge clk. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 89093ea5b..a9349879a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -6,6 +6,7 @@ // Purpose: one-hot to binary encoding. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index c0150133c..48282ccfa 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -7,6 +7,7 @@ // Purpose: Clock gater model. Must use standard cell for synthesis. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/counter.sv b/src/generic/counter.sv index faba2e5e5..cc20ae71e 100644 --- a/src/generic/counter.sv +++ b/src/generic/counter.sv @@ -7,6 +7,7 @@ // Purpose: Counter with reset and enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/csa.sv b/src/generic/csa.sv index 91aef44dd..ac9dfe098 100644 --- a/src/generic/csa.sv +++ b/src/generic/csa.sv @@ -7,6 +7,7 @@ // Purpose: 3:2 carry-save adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 6284a454c..78b816c3c 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -7,6 +7,7 @@ // Purpose: Binary encoding to one-hot decoder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index 97e0ac7e4..b7e7a82ee 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index 2e6432519..f1db84776 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 562c4565a..08b6590a8 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable and synchronous load // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 2c2144ab8..565fbfa7a 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index 94b2b3cb0..983fae5f2 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset, enabled clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index c4fc5d01b..11c128393 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous set // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index 2e39ee8d6..b3edcbdf9 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv index b35e9ccce..59f2e2862 100644 --- a/src/generic/flop/floprc.sv +++ b/src/generic/flop/floprc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset and clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index f99088af4..d4a63cd53 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -7,6 +7,7 @@ // Purpose: Two-stage flip-flop synchronizer // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index aa5381a22..855b64d88 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -6,6 +6,7 @@ // Purpose: Leading Zero Counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4af3c255c..ccfce5da2 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -13,6 +13,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index 55b1d75b0..64ddec259 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 5e7a4c5cf..1b5e1bdb7 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index a2c2c81fa..1744ba59f 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index e3746c181..ebe7e336b 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -11,6 +11,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 42435c607..0945684d3 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -12,6 +12,7 @@ // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 302277ed0..d499442b4 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index 6da7e06d6..a1633f8e9 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv index e181fdd07..54d0ee8dc 100644 --- a/src/generic/mem/ram2p1r1wbe_128x64.sv +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv index 442eff90d..95185346a 100644 --- a/src/generic/mem/ram2p1r1wbe_512x64.sv +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 4236bb3f6..db3cbc846 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index c298dba63..cc94f1b96 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -6,6 +6,7 @@ // Purpose: Single-ported ROM // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv index ea5b92054..0854f1557 100755 --- a/src/generic/mem/rom1p1r_128x32.sv +++ b/src/generic/mem/rom1p1r_128x32.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 6712d10fa..7a86bc50e 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 9c1dfe335..5a4767c87 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -7,6 +7,7 @@ // Purpose: Various flavors of multiplexers // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/neg.sv b/src/generic/neg.sv index e971fc232..8621e510e 100644 --- a/src/generic/neg.sv +++ b/src/generic/neg.sv @@ -7,6 +7,7 @@ // Purpose: 2's complement negator // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index b672a08e5..9b25feb65 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -7,6 +7,7 @@ // Purpose: Bin to one hot decoder. Power of 2 only. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv index 476b62586..56e693abb 100644 --- a/src/generic/or_rows.sv +++ b/src/generic/or_rows.sv @@ -7,6 +7,7 @@ // Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index 1cddb2bfc..65882dd75 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -17,6 +17,7 @@ // out 00000000000100000 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index f779d4748..23acfcfb3 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -13,6 +13,7 @@ // out 00000000000011111 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 3728ceb17..140c3e74e 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4c296fda2..51cf00b97 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4a5b4bfab..3f7d0ae7a 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index fc2530aab..3876c31e4 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 59a8e4a16..5b758f123 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 2879ba042..191919ecc 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 675387577..f32fcece9 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index d015c1195..eb54d6e3c 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 1feca6e1e..5ce1139fb 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 7701c0d65..903b67eeb 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 9ae3df42d..52ed8ef34 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 4dc3ad1bd..6e1948c33 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 0803d8b2f..466167fb3 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e5cfff9ed..b18df36ec 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index c2bcaf8c3..eb6fd1d81 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 4f7ee387f..b090c3f5e 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 870a37963..5a2b8d6dc 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 2b76bca17..bf6990ea9 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index bb0160c71..af44b6136 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index bc245d984..9f5dd2a43 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 64297c44a..faf537d91 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -9,6 +9,7 @@ // Prediction made during the fetch stage and corrected in the execution stage. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 567e4d3cd..2d0d30727 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index fcdf46655..7f5906084 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -10,6 +10,7 @@ // Purpose: gshare and Global History Branch predictors // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 7ae9f0282..1fa6f21f6 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -10,6 +10,7 @@ // Purpose: Global History Branch predictor with parameterized global history register // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index e4895d4b7..42bde6f4e 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -9,6 +9,7 @@ // Call, Return, Jump, and Branch // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 4d6d536a7..fd8acbc82 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -8,6 +8,7 @@ // Purpose: local history branch predictor with ahead pipelining and SRAM memories. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index d3a694c33..5c4485f3f 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -9,6 +9,7 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 95399e65a..3a730bd41 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -8,6 +8,7 @@ // Purpose: Local history branch predictor with speculation and repair using CBH. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index 470375adc..7dd33ffb3 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit starting counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 5b2fcb9b8..583b8d805 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit saturating counter predictor with parameterized table depth. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 50617d3c5..e6c4fcd9a 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -12,6 +12,7 @@ // *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 0bd899306..be2595ea6 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -8,6 +8,7 @@ // PC, branch prediction, instruction cache // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 0b29c72cf..e5e7a7f96 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -7,6 +7,7 @@ // // Purpose: simple instruction ROM // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 39b30abd1..ea045c43f 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 8710b1d6a..d516dad2a 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index c8b7ccee3..4d6330215 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 117a42c2b..7dbd0c8a2 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index a44086a15..1386db96f 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 551f08de4..7c042886a 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 66a9956dc..f7d1d4799 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 220a42eef..ca4e14f53 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index e5666eb84..82fb80fb1 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index ad21b3c25..705672ff7 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index 5737bdc9b..60164e081 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/div.sv b/src/mdu/div.sv index c550c06fc..2ae35d8f4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index 712e98866..f478ad86f 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index e152fc6de..886eaf2b3 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index a5946b95c..65eaefd82 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index 492d55372..05ac45bd0 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index 282918484..d71fef82a 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 2a99b14fd..0823dc7e0 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 6957ed315..e842016a2 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 896274554..84e41ba65 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f283772d..7226237f6 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 97cc6a18d..30a525744 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index a417bb530..5fbd10caf 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index e591498c4..aa569f2dd 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index 9471fb3d9..f5856ef56 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index aa9ec348a..83074deb3 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 18014155a..4776b5afb 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index 9652e21ef..4a8712da9 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 1a667d847..620f338a1 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 5e17e86eb..910db3aec 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index a089031c2..4a4e96387 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index e43712d81..e4dda5121 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index c3dbf1f6b..348ba1596 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -11,6 +11,7 @@ // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index ea7bf7afb..35b6f3fe6 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 056e8f2f9..9f5b29428 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index e107fc0f7..2357fc131 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 9935da179..3a28c5075 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 3a0f8c909..37891d009 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index a5bfde1cf..bc9f9235f 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 2d217b6d6..d6ef8d9d1 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index 5ac4cae78..f1c5bfd76 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index 5dea45972..ed43571bd 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 43ff8eadc..f20604379 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index 454f4d5df..dc7ceeab3 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -8,6 +8,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 6e35ffdaf..691ba372d 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 4ba3e1ccf..3b4ae1cb0 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8ced27319..4c0602353 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 896c2a4cb..0b15504c9 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index d94cd6e07..9576f33d7 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index ad1e0f259..f8aa4e016 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -16,6 +16,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index 6fab04189..eeecb7ea5 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 1675d5a38..22e0a35fc 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 79c4364cb..c0d08dd8c 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 4.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ab0071fff..d82a5c0d4 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/studies/comparator.sv b/studies/comparator.sv index a5dbb6cb6..01d38181b 100644 --- a/studies/comparator.sv +++ b/studies/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl index 5f595dad8..fa630a3e7 100755 --- a/synthDC/extractArea.pl +++ b/synthDC/extractArea.pl @@ -10,6 +10,7 @@ ## Purpose: Pull area statistics from run directory ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index fdf9be6cf..edf867240 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -6,6 +6,7 @@ // Purpose: Initialize stack, handle interrupts, terminate test case // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index ce5639bd7..3fe499abd 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -6,6 +6,7 @@ // Purpose: Test writes to CSRs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index 58f97a2e4..7d5905288 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -7,6 +7,7 @@ // (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index c6be8e4ef..fa7927d95 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for EBU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 0e3fd80d7..ca68e7275 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for FPU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 1e32a24ab..7ec318632 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for IEU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 0866326cc..4b085d845 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for IFU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index 4c11bf183..db873dec4 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -9,6 +9,7 @@ // Purpose: Test coverage for TLBCamlines in IFU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index 9ccb32aa8..0e065010e 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for lsu // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 39b3a8aeb..105a61e11 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for EBU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index 278568147..ecf66feed 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index e6ae534bd..de1541610 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -8,6 +8,7 @@ // Purpose: Coverage for the Page Table Entry Global flag check. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index ede79f13e..bbdb703b4 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -7,6 +7,7 @@ // Purpose: Create Page tables and access gigapages // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 5aaf5c195..4382673ea 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index ececa1f34..eba37ae99 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 043e5dc4a..f6dc4c597 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 15af7ea30..56d2943f4 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -8,6 +8,7 @@ // Purpose: Test coverage for LSU NAPOT // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index 54857afbd..f4b0a142e 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index eeb1c7d34..4bbb4958a 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for other TLB issues // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 55c4db959..2e03a4e1a 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -6,6 +6,7 @@ // Purpose: vm64check coverage // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/custom/cacheSimTest/CacheSimTest.py b/tests/custom/cacheSimTest/CacheSimTest.py index 44cc00b06..e81b87d55 100755 --- a/tests/custom/cacheSimTest/CacheSimTest.py +++ b/tests/custom/cacheSimTest/CacheSimTest.py @@ -10,6 +10,7 @@ ## Purpose: Confirm that the cache simulator behaves as expected. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## From fb35a865efe7a86cb438ceffda96203c26776a43 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Jan 2024 10:14:54 -0800 Subject: [PATCH 07/20] Progress on derivgen --- bin/derivgen.pl | 111 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 93 insertions(+), 18 deletions(-) mode change 100644 => 100755 bin/derivgen.pl diff --git a/bin/derivgen.pl b/bin/derivgen.pl old mode 100644 new mode 100755 index fcb6f8179..4074fd08e --- a/bin/derivgen.pl +++ b/bin/derivgen.pl @@ -35,24 +35,99 @@ use strict; use warnings; import os; -if ($#ARGV != 0) { - die("Usage: $0 workpath [e.g. $0 \$WALLY/addins/riscv-arch-test/work") +my $curderiv = ""; +my @derivlist = (); +my %derivs; +my %basederiv; + +if ($#ARGV != -1) { + die("Usage: $0") } -my $mypath = $ARGV[0]; -my @dirs = glob($mypath.'/*/*'); -foreach my $dir (@dirs) { - $dir =~ /.*\/(.*)\/(.*)/; - my $arch = $1; - my $ext = $2; - my $contents = `grep --with-filename ":" $dir/*.objdump`; - my @lines = split('\n', $contents); - print "$arch/$ext"; - foreach my $line (@lines) { - $line =~ /.*\/(.*)\.elf.objdump:(\S*)/; - my $fname = $1; - my $adr = $2; - my $partialaddress = substr($adr, -6); - print ",\n\t\t\"$arch/$ext/$fname\", \"$partialaddress\""; +my $derivlist = "$ENV{WALLY}/config/derivlist.txt"; +open(my $fh, $derivlist) or die "Could not open file '$derivlist' $!"; +foreach my $line (<$fh>) { + chomp $line; + my @tokens = split('\s+', $line); + if ($#tokens < 0 || $tokens[0] =~ /^#/) { # skip blank lines and comments + next; + } + if ($tokens[0] =~ /deriv/) { # start of a new derivative + &terminateDeriv(); + $curderiv = $tokens[1]; + $basederiv{$curderiv} = $tokens[2]; +# print("Found deriv $curderiv based on $basederiv{$curderiv}\n"); + @derivlist = (); + if ($#tokens > 2) { +# print(" with $tokens[3]\n"); + my $inherits = $derivs{$tokens[3]}; +# &printref($inherits); + @derivlist = @{$inherits}; +# foreach my $entry (@derivlist) { +# print(" Entry: @$entry\n"); +# } +# print (" dt3 = $inherits as array @derivlist\n"); +# print(" derivlist = @derivlist\n"); */ + } + } else { # add to the current derivative + my @entry = ($tokens[0], $tokens[1]); +# print(" Read Entry: @entry\n"); + push(@derivlist, \@entry); } - print("\n\n"); } +&terminateDeriv(); +close($fh); +#system("mkdir $ENV{WALLY}/config/deriv"); +foreach my $key (keys %derivs) { + my $dir = "$ENV{WALLY}/config/deriv/$key"; + system("mkdir -p $dir"); + my $configunmod = "$dir/config_unmod.vh"; + my $config = "$dir/config.vh"; + my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh"; + system("cp $base $configunmod"); + open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!"; + open(my $fh, '>>', $config) or die "Could not open file '$config' $!"; + + my $datestring = localtime(); + print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n"; + foreach my $line (<$unmod>) { + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = @ent[0]; + my $value = @ent[1]; + print(" In $config replace $param with $value\n"); +# $line =~ s/^\s*`define\s+$param\s+.*$/`define $param $value/; + $line =~ s/$param\s*=\s*.*;/$param = $value;/; + } + print $fh $line; + } + close($fh); + close($unmod); + + + +} + +#print("#######################\nKeys: ", join(' ', keys %derivs), "\n"); +#foreach my $key (keys %derivs) { +# print(" $key: $basederiv{$key} = "); +# &printref($derivs{$key}); +#} + +sub terminateDeriv { + if ($curderiv ne "") { # close out the previous derivative + my @dl = @derivlist; + $derivs{$curderiv} = \@dl; +# print("Finished: $curderiv = $derivs{$curderiv} "); +# &printref($derivs{$curderiv}); + } +}; + +sub printref { + my $ref = shift; + my @array = @{$ref}; +# print(" ## Printing ref $ref\n "); + foreach my $entry (@array) { + print join('_', @{$entry}), ', '; + } + print("\n"); +} \ No newline at end of file From d52d2d79832adccf3d6eac0b0cc54ab75a850ec1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Jan 2024 11:22:34 -0800 Subject: [PATCH 08/20] Initial derivgen working --- .gitignore | 1 + bin/derivgen.pl | 34 +++++++--------------------------- config/derivlist.txt | 5 +++++ 3 files changed, 13 insertions(+), 27 deletions(-) diff --git a/.gitignore b/.gitignore index 26cfe6b84..a01f1c07d 100644 --- a/.gitignore +++ b/.gitignore @@ -184,3 +184,4 @@ sim/cfi/* sim/branch/* sim/obj_dir examples/verilog/fulladder/obj_dir +config/deriv diff --git a/bin/derivgen.pl b/bin/derivgen.pl index 4074fd08e..6fe84fdfe 100755 --- a/bin/derivgen.pl +++ b/bin/derivgen.pl @@ -55,30 +55,21 @@ foreach my $line (<$fh>) { &terminateDeriv(); $curderiv = $tokens[1]; $basederiv{$curderiv} = $tokens[2]; -# print("Found deriv $curderiv based on $basederiv{$curderiv}\n"); @derivlist = (); if ($#tokens > 2) { -# print(" with $tokens[3]\n"); my $inherits = $derivs{$tokens[3]}; -# &printref($inherits); @derivlist = @{$inherits}; -# foreach my $entry (@derivlist) { -# print(" Entry: @$entry\n"); -# } -# print (" dt3 = $inherits as array @derivlist\n"); -# print(" derivlist = @derivlist\n"); */ } } else { # add to the current derivative my @entry = ($tokens[0], $tokens[1]); -# print(" Read Entry: @entry\n"); push(@derivlist, \@entry); } } &terminateDeriv(); close($fh); -#system("mkdir $ENV{WALLY}/config/deriv"); foreach my $key (keys %derivs) { my $dir = "$ENV{WALLY}/config/deriv/$key"; + system("rm -rf $dir"); system("mkdir -p $dir"); my $configunmod = "$dir/config_unmod.vh"; my $config = "$dir/config.vh"; @@ -92,40 +83,29 @@ foreach my $key (keys %derivs) { foreach my $line (<$unmod>) { foreach my $entry (@{$derivs{$key}}) { my @ent = @{$entry}; - my $param = @ent[0]; - my $value = @ent[1]; - print(" In $config replace $param with $value\n"); -# $line =~ s/^\s*`define\s+$param\s+.*$/`define $param $value/; - $line =~ s/$param\s*=\s*.*;/$param = $value;/; + my $param = $ent[0]; + my $value = $ent[1]; + if ($line =~ s/$param\s*=\s*.*;/$param = $value;/g) { + print("Hit: new line in $config is $line"); + #print $fh $line; + } } print $fh $line; } close($fh); close($unmod); - - - } -#print("#######################\nKeys: ", join(' ', keys %derivs), "\n"); -#foreach my $key (keys %derivs) { -# print(" $key: $basederiv{$key} = "); -# &printref($derivs{$key}); -#} - sub terminateDeriv { if ($curderiv ne "") { # close out the previous derivative my @dl = @derivlist; $derivs{$curderiv} = \@dl; -# print("Finished: $curderiv = $derivs{$curderiv} "); -# &printref($derivs{$curderiv}); } }; sub printref { my $ref = shift; my @array = @{$ref}; -# print(" ## Printing ref $ref\n "); foreach my $entry (@array) { print join('_', @{$entry}), ', '; } diff --git a/config/derivlist.txt b/config/derivlist.txt index 554697e62..0ba20e793 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -35,6 +35,7 @@ # If is not empty, all the list of parameter changes in the inherited # configuration are also applied to this configuration +# buildroot is used for the Linux boot deriv buildroot rv64gc RESET_VECTOR 64'h1000 UNCORE_RAM_RANGE 64'h0FFFFFFF @@ -44,6 +45,7 @@ SPI_LOOBACK_TEST 0 UART_PRESCALE 0 PLIC_NUM_SRC 32'd53 +# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM) deriv fpga rv64gc buildroot BOOTROM_PRELOAD 1 UNCORE_RAM_BASE 64'h2000 @@ -55,6 +57,7 @@ SDC_SUPPORTED 1 PLIC_SDC_ID 32'd20 BPRED_SIZE 32'd12 +# The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e DTIM_RANGE 32'h1FF IROM_RANGE 32'h1FF @@ -66,8 +69,10 @@ NUMWAYS 32'd1 BPRED_SIZE 32'd5 BTB_SIZE 32'd5 +# The other syn configurations have the same trimming deriv syn_rv32i rv32i syn_rv32e deriv syn_rv32imc rv32imc syn_rv32e deriv syn_rv32gc rv32gc syn_rv32e deriv syn_rv64i rv64i syn_rv32e deriv syn_rv64gc rv64gc syn_rv32e + From 32c102d89a493133e4fa843e330e43a6dc540cee Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Jan 2024 14:34:42 -0800 Subject: [PATCH 09/20] All deriv tests generated, use sim/make deriv --- bin/derivgen.pl | 19 +- config/buildroot/config.vh | 2 +- config/derivlist.txt | 441 +++++++++++++++++++++++++++++++++++- config/rv32e/config.vh | 5 + config/rv32gc/config.vh | 5 + config/rv32i/config.vh | 5 + config/rv32imc/config.vh | 5 + config/rv64fpquad/config.vh | 5 + config/rv64gc/config.vh | 6 + config/rv64i/config.vh | 5 + sim/Makefile | 6 +- sim/lint-wally | 4 +- 12 files changed, 498 insertions(+), 10 deletions(-) diff --git a/bin/derivgen.pl b/bin/derivgen.pl index 6fe84fdfe..096918400 100755 --- a/bin/derivgen.pl +++ b/bin/derivgen.pl @@ -34,6 +34,7 @@ use strict; use warnings; import os; +use Data::Dumper; my $curderiv = ""; my @derivlist = (); @@ -61,7 +62,8 @@ foreach my $line (<$fh>) { @derivlist = @{$inherits}; } } else { # add to the current derivative - my @entry = ($tokens[0], $tokens[1]); + $line =~ /\s*(\S+)\s*(.*)/; + my @entry = ($1, $2); push(@derivlist, \@entry); } } @@ -79,21 +81,30 @@ foreach my $key (keys %derivs) { open(my $fh, '>>', $config) or die "Could not open file '$config' $!"; my $datestring = localtime(); + my %hit = (); print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n"; foreach my $line (<$unmod>) { foreach my $entry (@{$derivs{$key}}) { my @ent = @{$entry}; my $param = $ent[0]; my $value = $ent[1]; - if ($line =~ s/$param\s*=\s*.*;/$param = $value;/g) { - print("Hit: new line in $config is $line"); - #print $fh $line; + if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) { + $hit{$param} = 1; +# print("Hit: new line in $config for $param is $line"); } } print $fh $line; } close($fh); close($unmod); + foreach my $entry (@{$derivs{$key}}) { + my @ent = @{$entry}; + my $param = $ent[0]; + if (!exists($hit{$param})) { + print("Unable to find $param in $key\n"); + } + } + system("rm -f $dir/config_unmod.vh"); } sub terminateDeriv { diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index de6e4800d..d334ab373 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -153,7 +153,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; - +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/derivlist.txt b/config/derivlist.txt index 0ba20e793..8b6eaf1d8 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -41,7 +41,7 @@ RESET_VECTOR 64'h1000 UNCORE_RAM_RANGE 64'h0FFFFFFF UNCORE_RAM_PRELOAD 1 GPIO_LOOPBACK_TEST 0 -SPI_LOOBACK_TEST 0 +SPI_LOOPBACK_TEST 0 UART_PRESCALE 0 PLIC_NUM_SRC 32'd53 @@ -63,7 +63,6 @@ DTIM_RANGE 32'h1FF IROM_RANGE 32'h1FF BOOTROM_RANGE 32'h1FF UNCORE_RAM_RANGE 32'h1FF -BOOTROM_RANGE 32'h1FF WAYSIZEINBYTES 32'd512 NUMWAYS 32'd1 BPRED_SIZE 32'd5 @@ -76,3 +75,441 @@ deriv syn_rv32gc rv32gc syn_rv32e deriv syn_rv64i rv64i syn_rv32e deriv syn_rv64gc rv64gc syn_rv32e +# The syn_sram configurations use SRAM macros +deriv syn_sram_rv32e rv32e +DTIM_RANGE 32'h1FF +IROM_RANGE 32'h1FF +USE_SRAM 1 + +# The other syn configurations have the same trimming +deriv syn_sram_rv32i rv32i syn_sram_rv32e +deriv syn_sram_rv32imc rv32imc syn_sram_rv32e +deriv syn_sram_rv32gc rv32gc syn_sram_rv32e +deriv syn_sram_rv64i rv64i syn_sram_rv32e +deriv syn_sram_rv64gc rv64gc syn_sram_rv32e + +# The following syn configurations gradually turn off features +deriv syn_pmp0_rv64gc rv64gc syn_rv64gc +PMP_ENTRIES 0 +deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc +PMP_ENTRIES 0 + +deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc +ZICSR_SUPPORTED 0 +deriv syn_sram_noPriv_rv64gc rv64gc syn_sram_pmp0_rv64gc +ZICSR_SUPPORTED 0 + +deriv syn_noFPU_rv64gc rv64gc syn_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +deriv syn_sram_noFPU_rv64gc rv64gc syn_sram_noPriv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) + +deriv syn_noMulDiv_rv64gc rv64gc syn_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) +deriv syn_sram_noMulDiv_rv64gc rv64gc syn_sram_noFPU_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0) + +deriv syn_noAtomic_rv64gc rv64gc syn_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) +deriv syn_sram_noAtomic_rv64gc rv64gc syn_sram_noMulDiv_rv64gc +MISA (32'h00000104 | 1 << 18 | 1 << 20) + +# Divider variants to check logical correctness + +deriv div_2_1_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd1 + +deriv div_2_2_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd2 + +deriv div_2_4_rv32gc rv32gc +RADIX 32'd2 +DIVCOPIES 32'd4 + +deriv div_4_1_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd1 + +deriv div_4_2_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd2 + +deriv div_4_4_rv32gc rv32gc +RADIX 32'd4 +DIVCOPIES 32'd4 + +deriv div_2_1i_rv32gc rv32gc div_2_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv32gc rv32gc div_2_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv32gc rv32gc div_2_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv32gc rv32gc div_4_1_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv32gc rv32gc div_4_2_rv32gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv32gc rv32gc div_4_4_rv32gc +IDIV_ON_FPU 1 + +deriv div_2_1_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd1 + +deriv div_2_2_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd2 + +deriv div_2_4_rv64gc rv64gc +RADIX 32'd2 +DIVCOPIES 32'd4 + +deriv div_4_1_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd1 + +deriv div_4_2_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd2 + +deriv div_4_4_rv64gc rv64gc +RADIX 32'd4 +DIVCOPIES 32'd4 + +deriv div_2_1i_rv64gc rv64gc div_2_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_2i_rv64gc rv64gc div_2_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_2_4i_rv64gc rv64gc div_2_4_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_1i_rv64gc rv64gc div_4_1_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_2i_rv64gc rv64gc div_4_2_rv64gc +IDIV_ON_FPU 1 + +deriv div_4_4i_rv64gc rv64gc div_4_4_rv64gc +IDIV_ON_FPU 1 + +# RAM latency and Burst mode for bus stress testing + +deriv ram_0_0_rv64gc rv64gc +RAM_LATENCY 0 +BURST_EN 0 + +deriv ram_1_0_rv64gc rv64gc +RAM_LATENCY 1 +BURST_EN 0 + +deriv ram_2_0_rv64gc rv64gc +RAM_LATENCY 2 +BURST_EN 0 + +deriv ram_1_1_rv64gc rv64gc +RAM_LATENCY 1 +BURST_EN 1 + +deriv ram_2_1_rv64gc rv64gc +RAM_LATENCY 2 +BURST_EN 1 + +# Branch predictor simulations + +deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc +BPRED_SIZE 6 + +deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc +BPRED_SIZE 8 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +BPRED_SIZE 10 + +deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc +BPRED_SIZE 12 + +deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc +BPRED_SIZE 14 + +deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc +BPRED_SIZE 16 + +deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc +BPRED_TYPE BP_TWOBIT + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 2 + +deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc +RAS_SIZE 3 + +deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc +RAS_SIZE 4 + +deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc +RAS_SIZE 6 + +deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +RAS_SIZE 10 + +deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc +RAS_SIZE 16 + +deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc +BTB_SIZE 6 + +deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc +BTB_SIZE 8 + +deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc +BTB_SIZE 12 + +deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc +BTB_SIZE 14 + +deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc +BTB_SIZE 16 + +deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc +ICLASSPRED 0 + +deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc +ICLASSPRED 0 + +# Cache configurations + +deriv noicache_rv32gc rv32gc +ICACHE_SUPPORTED 0 + +deriv nodcache_rv32gc rv32gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv32gc rv32gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv way_1_4096_512_rv32gc rv32gc +DCACHE_NUMWAYS 1 +DCACHE_WAYSIZEINBYTES 4096 +DCACHE_LINELENINBITS 512 +ICACHE_NUMWAYS 1 +ICACHE_WAYSIZEINBYTES 4096 +ICACHE_LINELENINBITS 512 + +deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 1 +ICACHE_NUMWAYS 1 + +deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 4 +ICACHE_NUMWAYS 4 + +deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_WAYSIZEINBYTES 2048 +ICACHE_WAYSIZEINBYTES 2048 + +deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 256 +ICACHE_LINELENINBITS 256 + +deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc +DCACHE_LINELENINBITS 1024 +ICACHE_LINELENINBITS 1024 + +deriv noicache_rv64gc rv64gc +ICACHE_SUPPORTED 0 + +deriv nodcache_rv64gc rv64gc +DCACHE_SUPPORTED 0 + +deriv nocache_rv64gc rv64gc +ICACHE_SUPPORTED 0 +DCACHE_SUPPORTED 0 + +deriv way_1_4096_512_rv64gc rv64gc +DCACHE_NUMWAYS 1 +DCACHE_WAYSIZEINBYTES 4096 +DCACHE_LINELENINBITS 512 +ICACHE_NUMWAYS 1 +ICACHE_WAYSIZEINBYTES 4096 +ICACHE_LINELENINBITS 512 + +deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 1 +ICACHE_NUMWAYS 1 + +deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 4 +ICACHE_NUMWAYS 4 + +deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_WAYSIZEINBYTES 2048 +ICACHE_WAYSIZEINBYTES 2048 + +deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 256 +ICACHE_LINELENINBITS 256 + +deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc +DCACHE_LINELENINBITS 1024 +ICACHE_LINELENINBITS 1024 + +# TLB Size variants + +deriv tlb2_rv32gc rv32gc +ITLB_ENTRIES 2 +DTLB_ENTRIES 2 + +deriv tlb16_rv32gc rv32gc +ITLB_ENTRIES 16 +DTLB_ENTRIES 16 + +deriv tlb2_rv64gc rv64gc +ITLB_ENTRIES 2 +DTLB_ENTRIES 2 + +deriv tlb16_rv64gc rv64gc +ITLB_ENTRIES 16 +DTLB_ENTRIES 16 + +# Feature variants + +deriv misaligned_rv32gc rv32gc +ZICCLSM_SUPPORTED 1 + +deriv nomisaligned_rv64gc rv64gc +ZICCLSM_SUPPORTED 0 + +deriv nobigendian_rv32gc rv32gc +BIGENDIAN_SUPPORTED 0 + +deriv nobigendian_rv64gc rv64gc +BIGENDIAN_SUPPORTED 0 + +# Floating-point modes supported + +deriv f_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdq_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv32gc rv32gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv f_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fd_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdqh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 70d455b4e..9abf11bf7 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 0; @@ -154,6 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 4baef0075..9a1ca7fea 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -133,6 +133,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -166,6 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; `endif +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 6e5d08803..a6ebe0985 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -132,6 +132,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -155,6 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index a32dc3bd6..5d8a3690b 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -131,6 +131,10 @@ localparam AHBW = 32'd32; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -153,6 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 09885808f..9a3416524 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 04a674b47..fa397471b 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; @@ -180,3 +185,4 @@ localparam ZCD_SUPPORTED = 0; localparam USE_SRAM = 0; `include "config-shared.vh" + diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 609a50f97..9061da2a5 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -134,6 +134,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes +// AHB +localparam RAM_LATENCY = 0; +localparam BURST_EN = 1; + // Tie GPIO outputs back to inputs localparam GPIO_LOOPBACK_TEST = 1; localparam SPI_LOOPBACK_TEST = 1; @@ -156,6 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; +localparam ICLASSPRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/sim/Makefile b/sim/Makefile index 5889d1df9..d7d259632 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,5 +1,5 @@ -all: riscoftests memfiles coveragetests +all: riscoftests memfiles coveragetests deriv # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired @@ -60,3 +60,7 @@ memfiles: coveragetests: make -C ../tests/coverage/ --jobs + +deriv: + derivgen.pl + \ No newline at end of file diff --git a/sim/lint-wally b/sim/lint-wally index eb6ad62b0..c82d1603b 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -5,10 +5,10 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do +for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do #for config in rv64gc; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi From 95a97faf3fc480793cc0dcca1ef01c2eea3e1b62 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 29 Jan 2024 16:46:34 -0600 Subject: [PATCH 10/20] Fixes testbench issues in testing against all vectors. Still a bug in ui32_to_f16_rz.sv - but will fix. Some things can be optimized. Overall, adds a FSM to test things more effectively. Actually is faster than previously as it assumed everything took the same number of cycles. Again, some things can be optimized --- testbench/testbench-fp.sv | 204 +++++++++++++++++--------------------- 1 file changed, 92 insertions(+), 112 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index b19542d62..46f261c0a 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -83,7 +83,7 @@ module testbenchfp; logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [P.DIVb:0] Quot; logic CvtResSubnormUfE; - logic DivStart; + logic DivStart=0; logic FDivBusyE; logic OldFDivBusyE; logic reset = 1'b0; @@ -120,7 +120,11 @@ module testbenchfp; logic ResMatch; // Check if result match logic FlagMatch; // Check if IEEE flags match logic CheckNow; // Final check - logic FMAop; // Is this a FMA operation? + logic FMAop; // Is this a FMA operation? + + // FSM for testing each item per clock + typedef enum logic [2:0] {S0, Start, S2, Done} statetype; + statetype state, nextstate; /////////////////////////////////////////////////////////////////////////////////////////////// @@ -676,7 +680,7 @@ module testbenchfp; .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, .Xs, .Ys, .Zs, .Unit(UnitVal), .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), - .Xm, .Ym, .Zm, .DivStart, + .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .ZSubnorm, @@ -748,16 +752,6 @@ module testbenchfp; clk = 1; #5; clk = 0; #5; end - // Provide reset for divsqrt to reset state to IDLE - // Previous version did not initiate a divide due to missing state - // information. This starts the FSM by putting the fdivsqrt into - // the IDLE state. - initial - begin - #0 reset = 1'b1; - #25 reset = 1'b0; - end - /////////////////////////////////////////////////////////////////////////////////////////////// // ||||| ||| |||||||||| ||||| ||| @@ -835,45 +829,64 @@ module testbenchfp; `CMPUNIT: ResFlg = CmpFlg; `CVTINTUNIT: ResFlg = Flg; `CVTFPUNIT: ResFlg = Flg; - endcase - end + endcase + // Use four state test sequence to handle div properly. + // Four states should allow other operations to finish + // properly and within time. + case (state) + S0: begin + DivStart = 1'b0; + nextstate = Start; + end + Start: begin + if (UnitVal == `DIVUNIT) + DivStart = 1'b1; + else + DivStart = 1'b0; + nextstate = S2; + end + S2: begin + DivStart = 1'b0; + if ((FDivBusyE)|(~DivDone)) + nextstate = S2; + else + nextstate = Done; + end + Done: begin + DivStart = 1'b0; + nextstate = S0; + end + endcase // case (state) + + end + + // Provide reset for divsqrt to reset state + initial + begin + #0 reset = 1'b1; + #25 reset = 1'b0; + end + + // Left-over from before - will remove soon always @(posedge clk) OldFDivBusyE = FDivDoneE; - // For FP division this adds extra clock cycles to make sure the - // computation completes. + // state machine to handle timing for testing due + // various cycle counts for different fp/int operations + // Adds vector at start of clock always @(posedge clk) begin - // Add extra clock cycles in beginning for fdivsqrt to adequate reset state - if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin - // This allows specific number of clocks to allow each vector - // to complete for division or square root. It is an - // arbitrary value and can be changed, if needed. - case (FmtVal) - // QP - 2'b11: begin - repeat (20) - @(posedge clk); - end - // HP - 2'b10: begin - repeat (14) - @(posedge clk); - end - // DP - 2'b01: begin - repeat (18) - @(posedge clk); - end - // SP - 2'b00: begin - repeat (16) - @(posedge clk); - end - endcase // case (FmtVal) - if (reset != 1'b1) - VectorNum += 1; // increment the vector - end + + // state machine element for testing + if (reset) + state <= S0; + else + state <= nextstate; + + // Increment the vector when Done with each test + if (state == Done) + VectorNum += 1; // increment the vector + end // check results on falling edge of clk @@ -904,7 +917,7 @@ module testbenchfp; (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]}))); endcase - else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + else if (UnitVal === `CVTFPUNIT) // if converting from FP to FP OpCtrl contains the final FP format case (OpCtrlVal[1:0]) 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | @@ -941,29 +954,22 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if result is correct - // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign FMAop = (OpCtrlVal == `FMAUNIT); assign DivDone = OldFDivBusyE & ~FDivBusyE; - - // Maybe change OpCtrl but for now just look at TEST for fma test - assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); - if (~(ResMatch & FlagMatch) & CheckNow) begin + assign CheckNow = ((DivDone | ~divsqrtop) | + (TEST == "all" | TEST == "add" | TEST == "fma" | TEST == "sub")) + & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); + + if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin errors += 1; $display("\nError in %s", Tests[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; - end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & - ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons - errors += 1; - $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; - end + end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof // increment the test @@ -979,11 +985,12 @@ module testbenchfp; // increment the rounding mode or loop back to rne if (FrmNum < 4) FrmNum += 1; else begin - FrmNum = 0; + FrmNum = 0; // Add some time as a buffer between tests at the end of each test - repeat (10) - @(posedge clk); - end + // (to be removed) + repeat (10) + @(posedge clk); + end // if no more Tests - finish if (Tests[TestNum] === "") begin $display("\nAll Tests completed with %d errors\n", errors); @@ -996,28 +1003,27 @@ endmodule module readvectors import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic [P.FLEN*4+7:0] TestVector, + input logic clk, + input logic [P.FLEN*4+7:0] TestVector, input logic [P.FMTBITS-1:0] ModFmt, - input logic [1:0] Fmt, - input logic [2:0] Unit, - input logic [31:0] VectorNum, - input logic [31:0] TestNum, - input logic [2:0] OpCtrl, - output logic [P.FLEN-1:0] Ans, - output logic [P.XLEN-1:0] SrcA, - output logic [4:0] AnsFlg, - output logic Xs, Ys, Zs, // sign bits of XYZ - output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) - output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) - output logic XNaN, YNaN, ZNaN, // is XYZ a NaN - output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN - output logic XSubnorm, ZSubnorm, // is XYZ denormalized - output logic XZero, YZero, ZZero, // is XYZ zero - output logic XInf, YInf, ZInf, // is XYZ infinity - output logic XExpMax, - output logic DivStart, - output logic [P.FLEN-1:0] X, Y, Z, XPostBox + input logic [1:0] Fmt, + input logic [2:0] Unit, + input logic [31:0] VectorNum, + input logic [31:0] TestNum, + input logic [2:0] OpCtrl, + output logic [P.FLEN-1:0] Ans, + output logic [P.XLEN-1:0] SrcA, + output logic [4:0] AnsFlg, + output logic Xs, Ys, Zs, // sign bits of XYZ + output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) + output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) + output logic XNaN, YNaN, ZNaN, // is XYZ a NaN + output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN + output logic XSubnorm, ZSubnorm, // is XYZ denormalized + output logic XZero, YZero, ZZero, // is XYZ zero + output logic XInf, YInf, ZInf, // is XYZ infinity + output logic XExpMax, + output logic [P.FLEN-1:0] X, Y, Z, XPostBox ); localparam Q_LEN = 32'd128; @@ -1030,8 +1036,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // apply test vectors on rising edge of clk // Format of vectors Inputs(1/2/3)_AnsFlg always @(VectorNum) begin - DivStart = 1'b0; - #1; AnsFlg = TestVector[4:0]; case (Unit) `FMAUNIT: @@ -1101,30 +1105,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b11: begin // quad X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; - if (~clk) #5; - DivStart = 1'b1; #10 // one clk cycle - DivStart = 1'b0; end 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; end 2'b00: if (P.S_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; end 2'b10: begin // half X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; end endcase else @@ -1133,33 +1125,21 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; - if (~clk) #5; - DivStart = 1'b1; #10 // one clk cycle - DivStart = 1'b0; end 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; end 2'b00: if (P.S_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; end 2'b10: begin // half X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; end endcase `CMPUNIT: From 3db5b6d9a9a76bab91d075853c59e9a4a1f37e8a Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 29 Jan 2024 14:51:21 -0800 Subject: [PATCH 11/20] Fix FLI to support quads --- sim/lint-wally | 2 +- src/fpu/fli.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/lint-wally b/sim/lint-wally index c82d1603b..3125e79ea 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -1,6 +1,6 @@ #!/bin/bash # check for warnings in Verilog code -# The verilator lint tool is faster and better than Modelsim so it is best to run this first. +# The verilator lint tool is faster and better than Questa so it is best to run this first. export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index dedb230b0..cf3b736d7 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -175,7 +175,7 @@ module fli import cvw::*; #(parameter cvw_t P) ( //////////////////////////// if (P.Q_SUPPORTED) begin - logic [63:0] QImm; + logic [127:0] QImm; always_comb begin case(Rs1) 0: QImm = 128'hBFFF0000000000000000000000000000; From 0d9e2fdf60c5af7ec05c73cd0900bd142851db77 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 29 Jan 2024 17:37:35 -0600 Subject: [PATCH 12/20] update Boolean logic for all testing for divide --- testbench/testbench-fp.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 46f261c0a..658107f56 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -848,7 +848,7 @@ module testbenchfp; end S2: begin DivStart = 1'b0; - if ((FDivBusyE)|(~DivDone)) + if ((FDivBusyE|~DivDone)&(UnitVal == `DIVUNIT)) nextstate = S2; else nextstate = Done; @@ -960,16 +960,16 @@ module testbenchfp; assign FMAop = (OpCtrlVal == `FMAUNIT); assign DivDone = OldFDivBusyE & ~FDivBusyE; assign CheckNow = ((DivDone | ~divsqrtop) | - (TEST == "all" | TEST == "add" | TEST == "fma" | TEST == "sub")) - & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); - + (TEST == "add" | TEST == "fma" | TEST == "sub") | + ((TEST == "all") & (DivDone | ~divsqrtop))); + if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin errors += 1; $display("\nError in %s", Tests[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; - end + end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof // increment the test From f37c7bb1f63c873fc23f6d4aa433f5b825bd4f23 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 30 Jan 2024 06:27:18 -0800 Subject: [PATCH 13/20] Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this --- config/buildroot/config.vh | 4 +++ config/rv32e/config.vh | 2 +- config/rv32gc/config.vh | 2 +- config/rv32i/config.vh | 2 +- config/rv32imc/config.vh | 2 +- config/rv64fpquad/config.vh | 2 +- config/rv64gc/config.vh | 2 +- config/rv64i/config.vh | 2 +- config/shared/parameter-defs.vh | 2 ++ src/cvw.sv | 2 ++ src/ebu/ahbcacheinterface.sv | 60 ++++++++++++++++----------------- src/ebu/buscachefsm.sv | 9 +++-- src/ebu/ebu.sv | 24 ++++++------- src/ifu/ifu.sv | 2 +- src/lsu/lsu.sv | 2 +- src/uncore/ram_ahb.sv | 6 ++-- src/wally/wallypipelinedcore.sv | 2 +- 17 files changed, 65 insertions(+), 62 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index d334ab373..2730a9706 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -130,6 +130,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Bus Interface width localparam AHBW = 32'd64; +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Test modes // Tie GPIO outputs back to inputs diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 9abf11bf7..60153fdd2 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -133,7 +133,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 9a1ca7fea..eb021ab0e 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -134,7 +134,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index a6ebe0985..fe2aa9e51 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -133,7 +133,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 5d8a3690b..3714f0749 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -132,7 +132,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 9a3416524..941e11382 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index fa397471b..c4e54e346 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 9061da2a5..3067e9eab 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 7dc0a0bcf..bf4c11198 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -8,6 +8,8 @@ localparam cvw_t P = '{ IEEE754 : IEEE754, MISA : MISA, AHBW : AHBW, + RAM_LATENCY : RAM_LATENCY, + BURST_EN : BURST_EN, ZICSR_SUPPORTED : ZICSR_SUPPORTED, ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED, COUNTERS : COUNTERS, diff --git a/src/cvw.sv b/src/cvw.sv index a9ee9d093..c9d737d8f 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -41,6 +41,8 @@ typedef struct packed { logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead) int MISA; // Machine Instruction Set Architecture int AHBW; // AHB bus width (usually = XLEN) + int RAM_LATENCY; // Latency to stress AHB + logic BURST_EN; // Support AHB Burst Mode // RISC-V Features logic ZICSR_SUPPORTED; diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 89135966e..f033b40cc 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -28,10 +28,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ahbcacheinterface #( - parameter AHBW, - parameter LLEN, - parameter PA_BITS, +module ahbcacheinterface import cvw::*; #( + parameter cvw_t P, parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline @@ -46,14 +44,14 @@ module ahbcacheinterface #( output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [AHBW-1:0] HRDATA, // AHB read data - output logic [PA_BITS-1:0] HADDR, // AHB address - output logic [AHBW-1:0] HWDATA, // AHB write data - output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask + input logic [P.AHBW-1:0] HRDATA, // AHB read data + output logic [P.PA_BITS-1:0] HADDR, // AHB address + output logic [P.AHBW-1:0] HWDATA, // AHB write data + output logic [P.AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic Cacheable, // Memory operation is cachable input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch @@ -63,8 +61,8 @@ module ahbcacheinterface #( output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface - input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation - input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store + input logic [P.PA_BITS-1:0] PAdr, // Physical address of uncached memory operation + input logic [P.LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic BusAtomic, // Uncache atomic memory operation input logic [2:0] Funct3, // Size of uncached memory operation @@ -78,12 +76,12 @@ module ahbcacheinterface #( localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data - logic [PA_BITS-1:0] PAdrZero; + logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data + logic [P.PA_BITS-1:0] PAdrZero; genvar index; @@ -91,38 +89,38 @@ module ahbcacheinterface #( for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW])); + flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW])); end - assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; - mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR; + assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; + mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); + assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [AHBW-1:0] CacheReadDataWordAHB; + logic [P.AHBW-1:0] CacheReadDataWordAHB; if(LLENPOVERAHBW > 1) begin - logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + logic [P.AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0]; - mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]), + mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e9dadb515..75f444e4b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -28,13 +28,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance. - // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE - parameter READ_ONLY_CACHE + parameter READ_ONLY_CACHE, // 1 for read-only instruction cache + parameter BURST_EN // burst mode supported )( input logic HCLK, input logic HRESETn, @@ -142,11 +141,11 @@ module buscachefsm #( assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CurrState == CACHE_WRITEBACK & |BeatCount); - assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; + assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin case(BeatCountThreshold) diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index d9a95fc3d..b91eb75b0 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -32,31 +32,31 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ebu #(parameter XLEN, PA_BITS, AHBW)( +module ebu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Signals from IFU input logic [1:0] IFUHTRANS, // IFU AHB transaction request input logic [2:0] IFUHSIZE, // IFU AHB transaction size input logic [2:0] IFUHBURST, // IFU AHB burst length - input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address + input logic [P.PA_BITS-1:0] IFUHADDR, // IFU AHB address output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant // Signals from LSU input logic [1:0] LSUHTRANS, // LSU AHB transaction request input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read input logic [2:0] LSUHSIZE, // LSU AHB size input logic [2:0] LSUHBURST, // LSU AHB burst length - input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address - input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN - input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask + input logic [P.PA_BITS-1:0] LSUHADDR, // LSU AHB address + input logic [P.XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [P.XLEN/8-1:0] LSUHWSTRB, // AHB byte mask output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored. - output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic [P.PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [P.AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [P.XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic HWRITE, // AHB transaction direction after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration @@ -72,13 +72,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( logic IFUDisable; logic IFUSelect; - logic [PA_BITS-1:0] IFUHADDROut; + logic [P.PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [PA_BITS-1:0] LSUHADDROut; + logic [P.PA_BITS-1:0] LSUHADDROut; logic [1:0] LSUHTRANSOut; logic [2:0] LSUHBURSTOut; logic [2:0] LSUHSIZEOut; @@ -97,14 +97,14 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index be2595ea6..4848b5ebb 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -255,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); - ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) + ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index ca4e14f53..c997d58ff 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -346,7 +346,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( + ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 0b15504c9..e14728513 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define RAM_LATENCY 0 - module ram_ahb import cvw::*; #(parameter cvw_t P, parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, @@ -76,7 +74,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); // use this to add arbitrary latency to ram. Helps test AHB controller correctness - if(`RAM_LATENCY > 0) begin + if(P.RAM_LATENCY > 0) begin logic [7:0] NextCycle, Cycle; logic CntEn, CntRst; logic CycleFlag; @@ -101,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == `RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index c0d08dd8c..ec0679f13 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -252,7 +252,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .LSUStallM); if(P.BUS_SUPPORTED) begin : ebu - ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections + ebu #(P) ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE, From 7e036e6f751c624a9a5c2fbb8316508375c2fdba Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 30 Jan 2024 10:51:07 -0600 Subject: [PATCH 14/20] Update cvt bug that was caught with new testbench-fp --- src/fpu/postproc/cvtshiftcalc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 77b8543fd..128f52253 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -98,6 +98,6 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) ( // determine if the result underflows ??? -> fp // - if the first 1 is shifted out of the result then the result underflows // - can't underflow an integer to fp conversions - assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero; // dh &~IntToFp not necessary because integer to float conversion never underflows + assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; endmodule From bf7e20e84650105fb3b6311273465c1d0ba52e54 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 30 Jan 2024 09:49:27 -0800 Subject: [PATCH 15/20] IEEE754 derivatives for testfloat --- config/buildroot/config.vh | 2 +- config/derivlist.txt | 82 ++++++++++++++++++++++++++----------- config/rv32e/config.vh | 2 +- config/rv32gc/config.vh | 2 +- config/rv32i/config.vh | 2 +- config/rv32imc/config.vh | 2 +- config/rv64fpquad/config.vh | 2 +- config/rv64gc/config.vh | 2 +- config/rv64i/config.vh | 2 +- sim/sim-testfloat | 2 +- sim/sim-testfloat-batch | 2 +- sim/testfloat.do | 2 +- testbench/testbench-fp.sv | 6 ++- 13 files changed, 74 insertions(+), 36 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index 2730a9706..6629af297 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/derivlist.txt b/config/derivlist.txt index 8b6eaf1d8..bcffb1ec5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -294,73 +294,73 @@ deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc BTB_SIZE 16 deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_8_16_10_0_rv32gc rv32gc bpred_GSHARE_8_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_12_16_10_0_rv32gc rv32gc bpred_GSHARE_12_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_14_16_10_0_rv32gc rv32gc bpred_GSHARE_14_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_TWOBIT_16_16_10_0_rv32gc rv32gc bpred_GSHARE_16_16_10_0_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_3_10_0_rv32gc rv32gc bpred_GSHARE_10_3_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_4_10_0_rv32gc rv32gc bpred_GSHARE_10_4_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc -ICLASSPRED 0 +INSTR_CLASS_PRED 0 # Cache configurations @@ -390,6 +390,10 @@ deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc DCACHE_NUMWAYS 4 ICACHE_NUMWAYS 4 +deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc +DCACHE_NUMWAYS 8 +ICACHE_NUMWAYS 8 + deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc DCACHE_WAYSIZEINBYTES 2048 ICACHE_WAYSIZEINBYTES 2048 @@ -513,3 +517,35 @@ ZFH_SUPPORTED 0 deriv fdqh_rv64gc rv64gc MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 1 + +# IEEE compatible variants for TestFloat + +deriv f_ieee_rv32gc rv32gc f_rv32gc +IEEE754 1 + +deriv fh_ieee_v32gc rv32gc fh_rv32gc +IEEE754 1 + +deriv fdh_ieee_rv32gc rv32gc fdh_rv32gc +IEEE754 1 + +deriv fdq_ieee_rv32gc rv32gc fdq_rv32gc +IEEE754 1 + +deriv fdqh_ieee_rv32gc rv32gc fdqh_rv32gc +IEEE754 1 + +deriv f_ieee_rv64gc rv64gc f_rv64gc +IEEE754 1 + +deriv fh_ieee_rv64gc rv64gc fh_rv64gc +IEEE754 1 + +deriv fd_ieee_rv64gc rv64gc fd_rv64gc +IEEE754 1 + +deriv fdq_ieee_rv64gc rv64gc fdq_rv64gc +IEEE754 1 + +deriv fdqh_ieee_rv64gc rv64gc fdqh_rv64gc +IEEE754 1 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 60153fdd2..9f0056fad 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -158,7 +158,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index eb021ab0e..8b4b78a4f 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -170,7 +170,7 @@ localparam RAS_SIZE = `RAS_SIZE; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; `endif -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index fe2aa9e51..81b25bc2b 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -159,7 +159,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 3714f0749..931725cc4 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -157,7 +157,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 941e11382..3f5c8683a 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index c4e54e346..7f038d87e 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -160,7 +160,7 @@ localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 1; +localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; localparam ZMMUL_SUPPORTED = 0; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3067e9eab..4dd540a9f 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -160,7 +160,7 @@ localparam BPRED_SIZE = 32'd10; localparam BPRED_NUM_LHR = 32'd6; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -localparam ICLASSPRED = 0; +localparam INSTR_CLASS_PRED = 0; localparam SVADU_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0; diff --git a/sim/sim-testfloat b/sim/sim-testfloat index 7f22690c0..b7da7104a 100755 --- a/sim/sim-testfloat +++ b/sim/sim-testfloat @@ -9,4 +9,4 @@ # sqrt - test square root # all - test everything -vsim -do "do testfloat.do rv64fpquad $1" +vsim -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch index 073553e52..96fb0f345 100755 --- a/sim/sim-testfloat-batch +++ b/sim/sim-testfloat-batch @@ -10,4 +10,4 @@ # sqrt - test square root # all - test everything -vsim -c -do "do testfloat.do rv64fpquad $1" \ No newline at end of file +vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1" diff --git a/sim/testfloat.do b/sim/testfloat.do index f21975389..796b540f3 100644 --- a/sim/testfloat.do +++ b/sim/testfloat.do @@ -25,7 +25,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP or all for all tests diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 658107f56..5eab7c7ec 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -35,6 +35,8 @@ module testbenchfp; `include "parameter-defs.vh" + parameter MAXVECTORS = 8388610; + // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls @@ -49,7 +51,7 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal @@ -975,7 +977,7 @@ module testbenchfp; // increment the test TestNum += 1; // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; + for(int i=0; i Date: Tue, 30 Jan 2024 09:52:23 -0800 Subject: [PATCH 16/20] Removed unused rv64fpquad config --- config/rv64fpquad/config.vh | 187 ------------------------------------ 1 file changed, 187 deletions(-) delete mode 100644 config/rv64fpquad/config.vh diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh deleted file mode 100644 index 3f5c8683a..000000000 --- a/config/rv64fpquad/config.vh +++ /dev/null @@ -1,187 +0,0 @@ -////////////////////////////////////////// -// config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "BranchPredictorType.vh" - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32'd64; - -// IEEE 754 compliance -localparam IEEE754 = 1; - -// MISA RISC-V configuration per specification -localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); -localparam ZICSR_SUPPORTED = 1; -localparam ZIFENCEI_SUPPORTED = 1; -localparam COUNTERS = 12'd32; -localparam ZICNTR_SUPPORTED = 1; -localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 1; -localparam ZFA_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 0; -localparam ZICBOM_SUPPORTED = 0; -localparam ZICBOZ_SUPPORTED = 0; -localparam ZICBOP_SUPPORTED = 0; -localparam ZICCLSM_SUPPORTED = 0; -localparam ZICOND_SUPPORTED = 0; -localparam SVPBMT_SUPPORTED = 0; -localparam SVNAPOT_SUPPORTED = 0; -localparam SVINVAL_SUPPORTED = 1; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 1; -localparam ICACHE_SUPPORTED = 1; -localparam VIRTMEM_SUPPORTED = 1; -localparam VECTORED_INTERRUPTS_SUPPORTED = 1 ; -localparam BIGENDIAN_SUPPORTED = 1; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 32'd32; -localparam DTLB_ENTRIES = 32'd32; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 32'd4; -localparam DCACHE_WAYSIZEINBYTES = 32'd4096; -localparam DCACHE_LINELENINBITS = 32'd512; -localparam ICACHE_NUMWAYS = 32'd4; -localparam ICACHE_WAYSIZEINBYTES = 32'd4096; -localparam ICACHE_LINELENINBITS = 32'd512; -localparam CACHE_SRAMLEN = 32'd128; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 32'd16; - -// Address space -localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; - -// Bus Interface width -localparam AHBW = 32'd64; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 32'd16; - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -localparam DTIM_SUPPORTED = 1'b0; -localparam logic [63:0] DTIM_BASE = 64'h80000000; -localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; -localparam IROM_SUPPORTED = 1'b0; -localparam logic [63:0] IROM_BASE = 64'h80000000; -localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; -localparam BOOTROM_PRELOAD = 1'b0; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; -localparam UNCORE_RAM_PRELOAD = 1'b0; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; -localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b1; -localparam logic [63:0] CLINT_BASE = 64'h02000000; -localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b1; -localparam logic [63:0] GPIO_BASE = 64'h10060000; -localparam logic [63:0] GPIO_RANGE = 64'h000000FF; -localparam UART_SUPPORTED = 1'b1; -localparam logic [63:0] UART_BASE = 64'h10000000; -localparam logic [63:0] UART_RANGE = 64'h00000007; -localparam PLIC_SUPPORTED = 1'b1; -localparam logic [63:0] PLIC_BASE = 64'h0C000000; -localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam logic [63:0] SDC_BASE = 64'h00013000; -localparam logic [63:0] SDC_RANGE = 64'h0000007F; -localparam SPI_SUPPORTED = 1'b1; -localparam logic [63:0] SPI_BASE = 64'h10040000; -localparam logic [63:0] SPI_RANGE = 64'h00000FFF; - -// Test modes - -// AHB -localparam RAM_LATENCY = 32'b0; -localparam BURST_EN = 1; - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 1; -localparam SPI_LOOPBACK_TEST = 1; - -// Hardware configuration -localparam UART_PRESCALE = 32'd1; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 32'd10; -// comment out the following if >=32 sources -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_GPIO_ID = 32'd3; -localparam PLIC_UART_ID = 32'd10; -localparam PLIC_SPI_ID = 32'd6; -localparam PLIC_SDC_ID = 32'd9; - -localparam BPRED_SUPPORTED = 1; -localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 32'd10; -localparam BPRED_NUM_LHR = 32'd6; -localparam BTB_SIZE = 32'd10; -localparam RAS_SIZE = 32'd16; -localparam INSTR_CLASS_PRED = 1; - -localparam SVADU_SUPPORTED = 0; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 32'h4; -localparam DIVCOPIES = 32'h4; - -// bit manipulation -localparam ZBA_SUPPORTED = 0; -localparam ZBB_SUPPORTED = 0; -localparam ZBC_SUPPORTED = 0; -localparam ZBS_SUPPORTED = 0; - -// New compressed instructions -localparam ZCB_SUPPORTED = 0; -localparam ZCA_SUPPORTED = 0; -localparam ZCF_SUPPORTED = 0; -localparam ZCD_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - -`include "config-shared.vh" From d9003da8e0c2e404c2597f3c1bad5b40bd4a7ee1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 30 Jan 2024 10:28:51 -0800 Subject: [PATCH 17/20] Moved some tests to wally-riscv-arch-test list that are simulated --- .../riscv-test-suite/rv32i_m/privilege/Makefrag | 9 ++++----- .../riscv-test-suite/rv64i_m/privilege/Makefrag | 10 +++++----- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 67f7c2f93..243d9011f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -36,11 +36,13 @@ rv32i_sc_tests = \ WALLY-lrsc-01 \ WALLY-status-mie-01 \ WALLY-trap-sret-01 \ - + WALLY-status-fp-enabled-01 \ + WALLY-minfo-01 \ + WALLY-cboz-01 \ + WALLY-cbom-01 \ target_tests_nosim = \ WALLY-pma-01 \ - WALLY-minfo-01 \ WALLY-mtvec-01 \ WALLY-stvec-01 \ WALLY-mie-01 \ @@ -49,7 +51,6 @@ target_tests_nosim = \ WALLY-trap-s-01 \ WALLY-trap-u-01 \ WALLY-wfi-01 \ - WALLY-status-fp-enabled-01 \ WALLY-status-sie-01 \ WALLY-status-tw-01 \ WALLY-gpio-01 \ @@ -57,8 +58,6 @@ target_tests_nosim = \ WALLY-plic-01 \ WALLY-uart-01 \ WALLY-spi-01 \ - WALLY-cbom-01 \ - WALLY-cboz-01 \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index a640e0c06..a96fae3db 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -39,12 +39,16 @@ rv64i_sc_tests = \ WALLY-status-mie-01 \ WALLY-status-sie-01 \ WALLY-status-tw-01 \ + WALLY-status-fp-enabled-01 \ + WALLY-misaligned-access-01 \ + WALLY-minfo-01 \ + WALLY-cboz-01 \ + WALLY-cbom-01 \ # Don't simulate these because they rely on SoC features that Spike does not offer. target_tests_nosim = \ WALLY-pma-01 \ - WALLY-minfo-01 \ WALLY-periph-01 \ WALLY-mtvec-01 \ WALLY-stvec-01 \ @@ -53,14 +57,10 @@ target_tests_nosim = \ WALLY-trap-01 \ WALLY-trap-s-01 \ WALLY-trap-u-01 \ - WALLY-status-fp-enabled-01 \ WALLY-spi-01 \ WALLY-gpio-01 \ WALLY-uart-01 \ WALLY-wfi-01 \ - WALLY-cbom-01 \ - WALLY-cboz-01 \ - WALLY-misaligned-access-01 \ # unclear why status-fp-enabled and wfi aren't simulating ok From 0abfe5cb5544f542531bbf15ed22d07a292655a9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 11:39:59 -0800 Subject: [PATCH 18/20] Fixed some lint errors in derived configs --- config/derivlist.txt | 156 ++++++++++++++++---------------- config/shared/parameter-defs.vh | 1 + sim/lint-wally | 18 +++- src/cache/cacheLRU.sv | 2 +- src/cvw.sv | 1 + src/fpu/fpu.sv | 14 +-- src/uncore/ram_ahb.sv | 2 +- 7 files changed, 105 insertions(+), 89 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index bcffb1ec5..53cb3b8f1 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -59,10 +59,10 @@ BPRED_SIZE 32'd12 # The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e -DTIM_RANGE 32'h1FF -IROM_RANGE 32'h1FF -BOOTROM_RANGE 32'h1FF -UNCORE_RAM_RANGE 32'h1FF +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF +BOOTROM_RANGE 64'h1FF +UNCORE_RAM_RANGE 64'h1FF WAYSIZEINBYTES 32'd512 NUMWAYS 32'd1 BPRED_SIZE 32'd5 @@ -77,8 +77,8 @@ deriv syn_rv64gc rv64gc syn_rv32e # The syn_sram configurations use SRAM macros deriv syn_sram_rv32e rv32e -DTIM_RANGE 32'h1FF -IROM_RANGE 32'h1FF +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF USE_SRAM 1 # The other syn configurations have the same trimming @@ -90,9 +90,9 @@ deriv syn_sram_rv64gc rv64gc syn_sram_rv32e # The following syn configurations gradually turn off features deriv syn_pmp0_rv64gc rv64gc syn_rv64gc -PMP_ENTRIES 0 +PMP_ENTRIES 32'd0 deriv syn_sram_pmp0_rv64gc rv64gc syn_sram_rv64gc -PMP_ENTRIES 0 +PMP_ENTRIES 32'd0 deriv syn_noPriv_rv64gc rv64gc syn_pmp0_rv64gc ZICSR_SUPPORTED 0 @@ -203,95 +203,95 @@ IDIV_ON_FPU 1 # RAM latency and Burst mode for bus stress testing deriv ram_0_0_rv64gc rv64gc -RAM_LATENCY 0 +RAM_LATENCY 32'd0 BURST_EN 0 deriv ram_1_0_rv64gc rv64gc -RAM_LATENCY 1 +RAM_LATENCY 32'd1 BURST_EN 0 deriv ram_2_0_rv64gc rv64gc -RAM_LATENCY 2 +RAM_LATENCY 32'd2 BURST_EN 0 deriv ram_1_1_rv64gc rv64gc -RAM_LATENCY 1 +RAM_LATENCY 32'd1 BURST_EN 1 deriv ram_2_1_rv64gc rv64gc -RAM_LATENCY 2 +RAM_LATENCY 32'd2 BURST_EN 1 # Branch predictor simulations deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc -BPRED_SIZE 6 +BPRED_SIZE 32'd6 deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc -BPRED_SIZE 8 +BPRED_SIZE 32'd8 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc -BPRED_SIZE 10 +BPRED_SIZE 32'd10 deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc -BPRED_SIZE 12 +BPRED_SIZE 32'd12 deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc -BPRED_SIZE 14 +BPRED_SIZE 32'd14 deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc -BPRED_SIZE 16 +BPRED_SIZE 32'd16 deriv bpred_TWOBIT_6_16_10_1_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_8_16_10_1_rv32gc rv32gc bpred_GSHARE_8_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_10_16_10_1_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_12_16_10_1_rv32gc rv32gc bpred_GSHARE_12_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_14_16_10_1_rv32gc rv32gc bpred_GSHARE_14_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_TWOBIT_16_16_10_1_rv32gc rv32gc bpred_GSHARE_16_16_10_1_rv32gc -BPRED_TYPE BP_TWOBIT +BPRED_TYPE `BP_TWOBIT deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc -RAS_SIZE 2 +RAS_SIZE 32'd2 deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc -RAS_SIZE 3 +RAS_SIZE 32'd3 deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc -RAS_SIZE 4 +RAS_SIZE 32'd4 deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc -RAS_SIZE 6 +RAS_SIZE 32'd6 deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc -RAS_SIZE 10 +RAS_SIZE 32'd10 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc -RAS_SIZE 16 +RAS_SIZE 32'd16 deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc -BTB_SIZE 6 +BTB_SIZE 32'd6 deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc -BTB_SIZE 8 +BTB_SIZE 32'd8 deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc -BTB_SIZE 12 +BTB_SIZE 32'd12 deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc -BTB_SIZE 14 +BTB_SIZE 32'd14 deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc -BTB_SIZE 16 +BTB_SIZE 32'd16 deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc INSTR_CLASS_PRED 0 @@ -375,36 +375,36 @@ ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 deriv way_1_4096_512_rv32gc rv32gc -DCACHE_NUMWAYS 1 -DCACHE_WAYSIZEINBYTES 4096 -DCACHE_LINELENINBITS 512 -ICACHE_NUMWAYS 1 -ICACHE_WAYSIZEINBYTES 4096 -ICACHE_LINELENINBITS 512 +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 deriv way_2_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 1 -ICACHE_NUMWAYS 1 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 deriv way_4_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 4 -ICACHE_NUMWAYS 4 +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 deriv way_8_4096_512_rv32gc rv32gc way_1_4096_512_rv32gc -DCACHE_NUMWAYS 8 -ICACHE_NUMWAYS 8 +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 deriv way_4_2048_512_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_WAYSIZEINBYTES 2048 -ICACHE_WAYSIZEINBYTES 2048 +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 deriv way_4_4096_256_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 256 -ICACHE_LINELENINBITS 256 +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 deriv way_4_4096_1024_rv32gc rv32gc way_4_4096_512_rv32gc -DCACHE_LINELENINBITS 1024 -ICACHE_LINELENINBITS 1024 +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 deriv noicache_rv64gc rv64gc ICACHE_SUPPORTED 0 @@ -417,50 +417,50 @@ ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 deriv way_1_4096_512_rv64gc rv64gc -DCACHE_NUMWAYS 1 -DCACHE_WAYSIZEINBYTES 4096 -DCACHE_LINELENINBITS 512 -ICACHE_NUMWAYS 1 -ICACHE_WAYSIZEINBYTES 4096 -ICACHE_LINELENINBITS 512 +DCACHE_NUMWAYS 32'd1 +DCACHE_WAYSIZEINBYTES 32'd4096 +DCACHE_LINELENINBITS 32'd512 +ICACHE_NUMWAYS 32'd1 +ICACHE_WAYSIZEINBYTES 32'd4096 +ICACHE_LINELENINBITS 32'd512 deriv way_2_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc -DCACHE_NUMWAYS 1 -ICACHE_NUMWAYS 1 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc -DCACHE_NUMWAYS 4 -ICACHE_NUMWAYS 4 +DCACHE_NUMWAYS 32'd4 +ICACHE_NUMWAYS 32'd4 deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_WAYSIZEINBYTES 2048 -ICACHE_WAYSIZEINBYTES 2048 +DCACHE_WAYSIZEINBYTES 32'd2048 +ICACHE_WAYSIZEINBYTES 32'd2048 deriv way_4_4096_256_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_LINELENINBITS 256 -ICACHE_LINELENINBITS 256 +DCACHE_LINELENINBITS 32'd256 +ICACHE_LINELENINBITS 32'd256 deriv way_4_4096_1024_rv64gc rv64gc way_4_4096_512_rv64gc -DCACHE_LINELENINBITS 1024 -ICACHE_LINELENINBITS 1024 +DCACHE_LINELENINBITS 32'd1024 +ICACHE_LINELENINBITS 32'd1024 # TLB Size variants deriv tlb2_rv32gc rv32gc -ITLB_ENTRIES 2 -DTLB_ENTRIES 2 +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 deriv tlb16_rv32gc rv32gc -ITLB_ENTRIES 16 -DTLB_ENTRIES 16 +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 deriv tlb2_rv64gc rv64gc -ITLB_ENTRIES 2 -DTLB_ENTRIES 2 +ITLB_ENTRIES 32'd2 +DTLB_ENTRIES 32'd2 deriv tlb16_rv64gc rv64gc -ITLB_ENTRIES 16 -DTLB_ENTRIES 16 +ITLB_ENTRIES 32'd16 +DTLB_ENTRIES 32'd16 # Feature variants diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index bf4c11198..464e3c0f9 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -102,6 +102,7 @@ localparam cvw_t P = '{ BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, RAS_SIZE : RAS_SIZE, + INSTR_CLASS_PRED : INSTR_CLASS_PRED, RADIX : RADIX, DIVCOPIES : DIVCOPIES, ZBA_SUPPORTED : ZBA_SUPPORTED, diff --git a/sim/lint-wally b/sim/lint-wally index 3125e79ea..3d28a62ec 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -1,14 +1,26 @@ #!/bin/bash # check for warnings in Verilog code # The verilator lint tool is faster and better than Questa so it is best to run this first. + export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc; do -#for config in rv64gc; do + +if [ "$1" == "-nightly" ]; then + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc + derivconfigs=`ls $WALLY/config/deriv` + for entry in $derivconfigs + do + configs[${#configs[@]}]=$entry + done +else + configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc) +fi + +for config in ${configs[@]}; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 70f129d4b..870633405 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -143,7 +143,7 @@ module cacheLRU // This is a two port memory. // Every cycle must read from CacheSetData and each load/store must write the new LRU. always_ff @(posedge clk) begin - if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; + if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; if(CacheEn) begin if(ClearValid & ~FlushStage) LRUMemory[PAdr] <= '0; diff --git a/src/cvw.sv b/src/cvw.sv index c9d737d8f..75f83f68b 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -162,6 +162,7 @@ typedef struct packed { int BPRED_SIZE; int BTB_SIZE; int RAS_SIZE; + logic INSTR_CLASS_PRED; // is class predictor enabled // FPU division architecture int RADIX; diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 90ec10dee..85021d269 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -270,9 +270,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( // floating-point load immediate: fli if (P.ZFA_SUPPORTED) begin logic [4:0] Rs1E; + logic [1:0] Fmt2E; // Two-bit format field from instruction flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E); - fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE)); + flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E); + fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); end else assign FliResE = '0; // fmv.*.x: NaN Box SrcA to extend integer to requested FP size @@ -287,7 +289,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( FmtE, PreIntSrcE); // NaN boxing zeroes end // fmvp.*.x: Select pair of registers - if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED)) + if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN)) assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x else assign IntSrcE = PreIntSrcE; @@ -311,11 +313,11 @@ module fpu import cvw::*; #(parameter cvw_t P) ( end // sign extend to XLEN if necessary - if (P.FLEN>P.XLEN) - if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* - else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; + if (P.FLEN >= 2*P.XLEN) + if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.* + else assign IntSrcXE = SgnExtXE[P.XLEN-1:0]; else - assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE}; + assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE}; mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); // E/M pipe registers diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index e14728513..98bdfcb09 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -99,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == P.RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY[7:0]; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; From 2af9282bbc598a55ffa320b274bd6292591cec6b Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 13:18:00 -0800 Subject: [PATCH 19/20] Starting to add nightly regression capability using derived configs --- config/derivlist.txt | 4 +++ sim/regression-wally | 65 +++++++++++++++++++++++++++++++++++--------- sim/wally-batch.do | 10 +++---- 3 files changed, 61 insertions(+), 18 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 53cb3b8f1..de10f7d52 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -432,6 +432,10 @@ deriv way_4_4096_512_rv64gc rv64gc way_1_4096_512_rv64gc DCACHE_NUMWAYS 32'd4 ICACHE_NUMWAYS 32'd4 +deriv way_8_4096_512_rv64gc rv32gc way_1_4096_512_rv64gc +DCACHE_NUMWAYS 32'd8 +ICACHE_NUMWAYS 32'd8 + deriv way_4_2048_512_rv64gc rv64gc way_4_4096_512_rv64gc DCACHE_WAYSIZEINBYTES 32'd2048 ICACHE_WAYSIZEINBYTES 32'd2048 diff --git a/sim/regression-wally b/sim/regression-wally index ea453d2c9..b1a50d1ab 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -29,6 +29,7 @@ os.chdir(regressionDir) coverage = '-coverage' in sys.argv fp = '-fp' in sys.argv +nightly = '-nightly' in sys.argv TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # name: the name of this test configuration (used in printing human-readable @@ -40,14 +41,19 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # be any pattern grep accepts, see `man 1 grep` for more info). # edit this list to add more test cases -configs = [ - TestCase( - name="lints", - variant="all", - cmd="./lint-wally | tee {}", - grepstr="All lints run with no errors or warnings" - ) -] +if (nightly): + nightMode = "-nightly"; +else: + nightMode = ""; + configs = [ + TestCase( + name="lints", + variant="all", + cmd="./lint-wally " + nightMode + " | tee {}", + grepstr="All lints run with no errors or warnings" + ) + ] + def getBuildrootTC(boot): INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. @@ -78,7 +84,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "arch32zfad", "wally32a", "wally32priv", "wally32periph"] #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( @@ -126,15 +132,15 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad", "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] if (coverage): # delete all but 64gc tests when running coverage configs = [] - tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", + tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zicboz", "arch64zcb", + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfaf", "arch64zfad"] # add when working: "arch64zcb", "arch64zicboz" if (fp): tests64gc.append("arch64f") tests64gc.append("arch64d") @@ -150,7 +156,40 @@ for test in tests64gc: cmd="vsim > {} -c < {} -c < {} -c <= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc if {$2 eq "buildroot"} { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation if { $coverage } { echo "wally-batch buildroot coverage" @@ -74,7 +74,7 @@ if {$2 eq "buildroot"} { run -all exec ./slack-notifier/slack-notifier.py } elseif {$2 eq "buildroot-no-trace"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 @@ -88,7 +88,7 @@ if {$2 eq "buildroot"} { exec ./slack-notifier/slack-notifier.py } elseif {$2 eq "ahb"} { - vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 + vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt @@ -112,7 +112,7 @@ if {$2 eq "buildroot"} { # **** fix this so we can pass any number of +defines. # only allows 3 right now - vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7 + vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt @@ -126,7 +126,7 @@ if {$2 eq "buildroot"} { # power off -r /dut/core/* } else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals if {$coverage} { From d3c886abaf22678d90dfeb16995dc20ff7e705a0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Jan 2024 14:07:41 -0800 Subject: [PATCH 20/20] regression-wally initial -nightly support --- sim/regression-wally | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index b1a50d1ab..7b0175841 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -43,6 +43,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # edit this list to add more test cases if (nightly): nightMode = "-nightly"; + configs = [] else: nightMode = ""; configs = [ @@ -84,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "arch32zfad", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase(