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Updated mmu's tlb and hptw to use Lim's parameterization.

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This commit is contained in:
Ross Thompson 2023-05-24 18:02:22 -05:00
parent 438c955d1c
commit 7c364d5a77
18 changed files with 90 additions and 96 deletions
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1
config/buildroot/config.vh
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@ -133,6 +133,7 @@ localparam PLIC_GPIO_ID = 32'd3;
localparam BPRED_SUPPORTED = 1; localparam BPRED_SUPPORTED = 1;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT; localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT;
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;

1
config/rv32e/config.vh
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@ -133,6 +133,7 @@ localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0; localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 0;

2
config/rv32gc/config.vh
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@ -139,7 +139,7 @@ localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd16; localparam BPRED_SIZE = 32'd16;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture // FPU division architecture

1
config/rv32i/config.vh
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@ -133,6 +133,7 @@ localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0; localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 0;

1
config/rv32imc/config.vh
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@ -132,6 +132,7 @@ localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0; localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N localparam BPRED_TYPE = "GSHARE_N"; // GSHARE_B, GLOBAL_N, GLOBAL_B, TWOBIT_N
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 0;

1
config/rv64fpquad/config.vh
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@ -135,6 +135,7 @@ localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 1; localparam BPRED_SUPPORTED = 1;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 0;

2
config/rv64gc/config.vh
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@ -140,7 +140,7 @@ localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BAS
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 1;
localparam ZMMUL_SUPPORTED = 0; localparam ZMMUL_SUPPORTED = 0;
// FPU division architecture // FPU division architecture

1
config/rv64i/config.vh
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@ -135,6 +135,7 @@ localparam PLIC_UART_ID = 32'd10;
localparam BPRED_SUPPORTED = 0; localparam BPRED_SUPPORTED = 0;
localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_TYPE = "GSHARE_N"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
localparam BPRED_NUM_LHR = 32'd6;
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam SVADU_SUPPORTED = 0; localparam SVADU_SUPPORTED = 0;

2
src/mmu/hptw.sv
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@ -169,7 +169,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
((EffectivePrivilegeMode == P.S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk)); ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
// Check for page faults // Check for page faults
vm64check vm64check(.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .VAdr(TranslationVAdr), vm64check #(P) vm64check(.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .VAdr(TranslationVAdr),
.SV39Mode(), .UpperBitsUnequal); .SV39Mode(), .UpperBitsUnequal);
assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable); assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
assign InvalidWrite = WriteAccess & ~Writable; assign InvalidWrite = WriteAccess & ~Writable;

10
src/mmu/mmu.sv
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@ -29,16 +29,16 @@
module mmu import cvw::*; #(parameter cvw_t P, module mmu import cvw::*; #(parameter cvw_t P,
parameter TLB_ENTRIES = 8, IMMU = 0) ( parameter TLB_ENTRIES = 8, IMMU = 0) (
input logic clk, reset, input logic clk, reset,
input logic [P.XLEN-1:0] SATP_REGW, // Current value of satp CSR (from privileged unit) input logic [P.XLEN-1:0] SATP_REGW, // Current value of satp CSR (from privileged unit)
input logic STATUS_MXR, // Status CSR: make executable page readable input logic STATUS_MXR, // Status CSR: make executable page readable
input logic STATUS_SUM, // Status CSR: Supervisor access to user memory input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
input logic STATUS_MPRV, // Status CSR: modify machine privilege input logic STATUS_MPRV, // Status CSR: modify machine privilege
input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
input logic [P.XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW input logic [P.XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW
input logic [1:0] Size, // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits input logic [1:0] Size, // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
input logic [P.XLEN-1:0] PTE, // page table entry input logic [P.XLEN-1:0] PTE, // page table entry
input logic [1:0] PageTypeWriteVal, // page type input logic [1:0] PageTypeWriteVal, // page type
input logic TLBWrite, // write TLB entry input logic TLBWrite, // write TLB entry
input logic TLBFlush, // Invalidate all TLB entries input logic TLBFlush, // Invalidate all TLB entries
@ -58,7 +58,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP addresses input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP addresses
); );
logic [P.PA_BITS-1:0] TLBPAdr; // physical address for TLB logic [P.PA_BITS-1:0] TLBPAdr; // physical address for TLB
logic PMAInstrAccessFaultF; // Instruction access fault from PMA logic PMAInstrAccessFaultF; // Instruction access fault from PMA
logic PMPInstrAccessFaultF; // Instruction access fault from PMP logic PMPInstrAccessFaultF; // Instruction access fault from PMP
logic PMALoadAccessFaultM; // Load access fault from PMA logic PMALoadAccessFaultM; // Load access fault from PMA
@ -76,7 +76,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
logic ReadAccess, WriteAccess; logic ReadAccess, WriteAccess;
assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
assign WriteAccess = WriteAccessM; assign WriteAccess = WriteAccessM;
tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb( tlb #(.P(P), .TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
.clk, .reset, .clk, .reset,
.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
.SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]), .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),

61
src/mmu/tlb/tlb.sv
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@ -49,36 +49,35 @@
* RSW(2) -- for OS * RSW(2) -- for OS
*/ */
`include "wally-config.vh"
// The TLB will have 2**ENTRY_BITS total entries // The TLB will have 2**ENTRY_BITS total entries
module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) ( module tlb import cvw::*; #(parameter cvw_t P,
input logic clk, reset, parameter TLB_ENTRIES = 8, ITLB = 0) (
input logic [`SVMODE_BITS-1:0] SATP_MODE, // Current address translation mode input logic clk, reset,
input logic [`ASID_BITS-1:0] SATP_ASID, input logic [P.SVMODE_BITS-1:0] SATP_MODE, // Current address translation mode
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [P.ASID_BITS-1:0] SATP_ASID,
input logic [1:0] STATUS_MPP, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] STATUS_MPP,
input logic ReadAccess, input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
input logic WriteAccess, input logic ReadAccess,
input logic DisableTranslation, input logic WriteAccess,
input logic [`XLEN-1:0] VAdr, // address input before translation (could be physical or virtual) input logic DisableTranslation,
input logic [`XLEN-1:0] PTE, input logic [P.XLEN-1:0] VAdr, // address input before translation (could be physical or virtual)
input logic [1:0] PageTypeWriteVal, input logic [P.XLEN-1:0] PTE,
input logic TLBWrite, input logic [1:0] PageTypeWriteVal,
input logic TLBFlush, input logic TLBWrite,
output logic [`PA_BITS-1:0] TLBPAdr, input logic TLBFlush,
output logic TLBMiss, output logic [P.PA_BITS-1:0] TLBPAdr,
output logic TLBHit, output logic TLBMiss,
output logic Translate, output logic TLBHit,
output logic TLBPageFault, output logic Translate,
output logic UpdateDA output logic TLBPageFault,
output logic UpdateDA
); );
logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex
// Sections of the virtual and physical addresses // Sections of the virtual and physical addresses
logic [`VPN_BITS-1:0] VPN; logic [P.VPN_BITS-1:0] VPN;
logic [`PPN_BITS-1:0] PPN; logic [P.PPN_BITS-1:0] PPN;
// Sections of the page table entry // Sections of the page table entry
logic [7:0] PTEAccessBits; logic [7:0] PTEAccessBits;
logic [1:0] HitPageType; logic [1:0] HitPageType;
@ -87,7 +86,7 @@ module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) (
logic Misaligned; logic Misaligned;
logic MegapageMisaligned; logic MegapageMisaligned;
if(`XLEN == 32) begin if(P.XLEN == 32) begin
assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned; assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned;
end else begin // 64-bit end else begin // 64-bit
@ -100,22 +99,22 @@ module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) (
((HitPageType == 2'b01) & MegapageMisaligned); ((HitPageType == 2'b01) & MegapageMisaligned);
end end
assign VPN = VAdr[`VPN_BITS+11:12]; assign VPN = VAdr[P.VPN_BITS+11:12];
tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
.PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault,
.UpdateDA, .SV39Mode, .Translate); .UpdateDA, .SV39Mode, .Translate);
tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables); tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS)
tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs,
.SATP_ASID, .Matches, .HitPageType, .CAMHit); .SATP_ASID, .Matches, .HitPageType, .CAMHit);
tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs); tlbram #(P, TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs);
// Replace segments of the virtual page number with segments of the physical // Replace segments of the virtual page number with segments of the physical
// page number. For 4 KB pages, the entire virtual page number is replaced. // page number. For 4 KB pages, the entire virtual page number is replaced.
// For superpages, some segments are considered offsets into a larger page. // For superpages, some segments are considered offsets into a larger page.
tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr); tlbmixer #(P) Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr);
endmodule endmodule

10
src/mmu/tlb/tlbcam.sv
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@ -29,17 +29,15 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" module tlbcam import cvw::*; #(parameter cvw_t P, TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
input logic clk, reset, input logic clk, reset,
input logic [`VPN_BITS-1:0] VPN, input logic [P.VPN_BITS-1:0] VPN,
input logic [1:0] PageTypeWriteVal, input logic [1:0] PageTypeWriteVal,
input logic SV39Mode, input logic SV39Mode,
input logic TLBFlush, input logic TLBFlush,
input logic [TLB_ENTRIES-1:0] WriteEnables, input logic [TLB_ENTRIES-1:0] WriteEnables,
input logic [TLB_ENTRIES-1:0] PTE_Gs, input logic [TLB_ENTRIES-1:0] PTE_Gs,
input logic [`ASID_BITS-1:0] SATP_ASID, input logic [P.ASID_BITS-1:0] SATP_ASID,
output logic [TLB_ENTRIES-1:0] Matches, output logic [TLB_ENTRIES-1:0] Matches,
output logic [1:0] HitPageType, output logic [1:0] HitPageType,
output logic CAMHit output logic CAMHit
@ -53,7 +51,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
// of page type. However, matches are determined based on a subset of the // of page type. However, matches are determined based on a subset of the
// page number segments. // page number segments.
tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0]( tlbcamline #(P, KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
.clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush, .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush,
.WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches));
assign CAMHit = |Matches & ~TLBFlush; assign CAMHit = |Matches & ~TLBFlush;

12
src/mmu/tlb/tlbcamline.sv
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@ -29,12 +29,10 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" module tlbcamline import cvw::*; #(parameter cvw_t P, KEY_BITS = 20, SEGMENT_BITS = 10) (
module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
input logic clk, reset, input logic clk, reset,
input logic [`VPN_BITS-1:0] VPN, // The requested page number to compare against the key input logic [P.VPN_BITS-1:0] VPN, // The requested page number to compare against the key
input logic [`ASID_BITS-1:0] SATP_ASID, input logic [P.ASID_BITS-1:0] SATP_ASID,
input logic SV39Mode, input logic SV39Mode,
input logic WriteEnable, // Write a new entry to this line input logic WriteEnable, // Write a new entry to this line
input logic PTE_G, input logic PTE_G,
@ -56,13 +54,13 @@ module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
logic [1:0] PageType; logic [1:0] PageType;
// Split up key and query into sections for each page table level. // Split up key and query into sections for each page table level.
logic [`ASID_BITS-1:0] Key_ASID; logic [P.ASID_BITS-1:0] Key_ASID;
logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1; logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
logic MatchASID, Match0, Match1; logic MatchASID, Match0, Match1;
assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G;
if (`XLEN == 32) begin: match if (P.XLEN == 32) begin: match
assign {Key_ASID, Key1, Key0} = Key; assign {Key_ASID, Key1, Key0} = Key;
assign {Query1, Query0} = VPN; assign {Query1, Query0} = VPN;

24
src/mmu/tlb/tlbcontrol.sv
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@ -26,11 +26,9 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
input logic [P.SVMODE_BITS-1:0] SATP_MODE,
module tlbcontrol #(parameter ITLB = 0) ( input logic [P.XLEN-1:0] VAdr,
input logic [`SVMODE_BITS-1:0] SATP_MODE,
input logic [`XLEN-1:0] VAdr,
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
@ -58,13 +56,13 @@ module tlbcontrol #(parameter ITLB = 0) (
// Grab the sv mode from SATP and determine whether translation should occur // Grab the sv mode from SATP and determine whether translation should occur
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; assign Translate = (SATP_MODE != P.NO_TRANSLATE[P.SVMODE_BITS-1:0]) & (EffectivePrivilegeMode != P.M_MODE) & ~DisableTranslation;
// Determine whether TLB is being used // Determine whether TLB is being used
assign TLBAccess = ReadAccess | WriteAccess; assign TLBAccess = ReadAccess | WriteAccess;
// Check that upper bits are legal (all 0s or all 1s) // Check that upper bits are legal (all 0s or all 1s)
vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal); vm64check #(P) vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal);
// unswizzle useful PTE bits // unswizzle useful PTE bits
assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
@ -74,9 +72,9 @@ module tlbcontrol #(parameter ITLB = 0) (
if (ITLB == 1) begin:itlb // Instruction TLB fault checking if (ITLB == 1) begin:itlb // Instruction TLB fault checking
// User mode may only execute user mode pages, and supervisor mode may // User mode may only execute user mode pages, and supervisor mode may
// only execute non-user mode pages. // only execute non-user mode pages.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U); ((EffectivePrivilegeMode == P.S_MODE) & PTE_U);
if(`SVADU_SUPPORTED) begin : hptwwrites if(P.SVADU_SUPPORTED) begin : hptwwrites
assign UpdateDA = Translate & TLBHit & ~PTE_A & ~TLBPageFault; assign UpdateDA = Translate & TLBHit & ~PTE_A & ~TLBPageFault;
assign TLBPageFault = Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V); assign TLBPageFault = Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V);
end else begin end else begin
@ -89,8 +87,8 @@ module tlbcontrol #(parameter ITLB = 0) (
// User mode may only load/store from user mode pages, and supervisor mode // User mode may only load/store from user mode pages, and supervisor mode
// may only access user mode pages when STATUS_SUM is low. // may only access user mode pages when STATUS_SUM is low.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM); ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & ~STATUS_SUM);
// Check for read error. Reads are invalid when the page is not readable // Check for read error. Reads are invalid when the page is not readable
// (and executable pages are not readable) or when the page is neither // (and executable pages are not readable) or when the page is neither
// readable nor executable (and executable pages are readable). // readable nor executable (and executable pages are readable).
@ -98,7 +96,7 @@ module tlbcontrol #(parameter ITLB = 0) (
// Check for write error. Writes are invalid when the page's write bit is // Check for write error. Writes are invalid when the page's write bit is
// low. // low.
assign InvalidWrite = WriteAccess & ~PTE_W; assign InvalidWrite = WriteAccess & ~PTE_W;
if(`SVADU_SUPPORTED) begin : hptwwrites if(P.SVADU_SUPPORTED) begin : hptwwrites
assign UpdateDA = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; assign UpdateDA = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault;
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V)); assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V));
end else begin end else begin

24
src/mmu/tlb/tlbmixer.sv
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@ -29,24 +29,22 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" module tlbmixer import cvw::*; #(parameter cvw_t P) (
input logic [P.VPN_BITS-1:0] VPN,
module tlbmixer ( input logic [P.PPN_BITS-1:0] PPN,
input logic [`VPN_BITS-1:0] VPN,
input logic [`PPN_BITS-1:0] PPN,
input logic [1:0] HitPageType, input logic [1:0] HitPageType,
input logic [11:0] Offset, input logic [11:0] Offset,
input logic TLBHit, input logic TLBHit,
output logic [`PA_BITS-1:0] TLBPAdr output logic [P.PA_BITS-1:0] TLBPAdr
); );
localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS; localparam EXTRA_BITS = P.PPN_BITS - P.VPN_BITS;
logic [`PPN_BITS-1:0] ZeroExtendedVPN; logic [P.PPN_BITS-1:0] ZeroExtendedVPN;
logic [`PPN_BITS-1:0] PageNumberMask; logic [P.PPN_BITS-1:0] PageNumberMask;
logic [`PPN_BITS-1:0] PPNMixed; logic [P.PPN_BITS-1:0] PPNMixed;
// produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages
if (`XLEN == 32) if (P.XLEN == 32)
// kilopage: 22 bits of PPN, 0 bits of VPN // kilopage: 22 bits of PPN, 0 bits of VPN
// megapage: 12 bits of PPN, 10 bits of VPN // megapage: 12 bits of PPN, 10 bits of VPN
mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask); mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask);
@ -60,10 +58,10 @@ module tlbmixer (
// merge low segments of VPN with high segments of PPN decided by the pagetype. // merge low segments of VPN with high segments of PPN decided by the pagetype.
assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN. assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; //
//mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed); //mux2 #(1) mixmux[P.PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed);
//assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask); //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
// Output the hit physical address if translation is currently on. // Output the hit physical address if translation is currently on.
// Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system mux2 #(P.PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
endmodule endmodule

19
src/mmu/tlb/tlbram.sv
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@ -28,27 +28,26 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module tlbram #(parameter TLB_ENTRIES = 8) ( module tlbram import cvw::*; #(parameter cvw_t P, TLB_ENTRIES = 8) (
input logic clk, reset, input logic clk, reset,
input logic [`XLEN-1:0] PTE, input logic [P.XLEN-1:0] PTE,
input logic [TLB_ENTRIES-1:0] Matches, WriteEnables, input logic [TLB_ENTRIES-1:0] Matches, WriteEnables,
output logic [`PPN_BITS-1:0] PPN, output logic [P.PPN_BITS-1:0] PPN,
output logic [7:0] PTEAccessBits, output logic [7:0] PTEAccessBits,
output logic [TLB_ENTRIES-1:0] PTE_Gs output logic [TLB_ENTRIES-1:0] PTE_Gs
); );
logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0]; logic [P.PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
logic [`PPN_BITS+9:0] PageTableEntry; logic [P.PPN_BITS+9:0] PageTableEntry;
// RAM implemented with array of flops and AND/OR read logic // RAM implemented with array of flops and AND/OR read logic
tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0] tlbramline #(P.PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
(.clk, .reset, .re(Matches), .we(WriteEnables), (.clk, .reset, .re(Matches), .we(WriteEnables),
.d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs)); .d(PTE[P.PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry); or_rows #(TLB_ENTRIES, P.PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
// Rename the bits read from the TLB RAM // Rename the bits read from the TLB RAM
assign PTEAccessBits = PageTableEntry[7:0]; assign PTEAccessBits = PageTableEntry[7:0];
assign PPN = PageTableEntry[`PPN_BITS+9:10]; assign PPN = PageTableEntry[P.PPN_BITS+9:10];
endmodule endmodule

2
src/mmu/tlb/tlbramline.sv
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@ -26,8 +26,6 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh"
module tlbramline #(parameter WIDTH = 22) module tlbramline #(parameter WIDTH = 22)
(input logic clk, reset, (input logic clk, reset,
input logic re, we, input logic re, we,

10
src/mmu/tlb/vm64check.sv
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@ -28,15 +28,15 @@
`include "wally-config.vh" `include "wally-config.vh"
module vm64check ( module vm64check import cvw::*; #(parameter cvw_t P) (
input logic [`SVMODE_BITS-1:0] SATP_MODE, input logic [P.SVMODE_BITS-1:0] SATP_MODE,
input logic [`XLEN-1:0] VAdr, input logic [P.XLEN-1:0] VAdr,
output logic SV39Mode, output logic SV39Mode,
output logic UpperBitsUnequal output logic UpperBitsUnequal
); );
if (`XLEN == 64) begin if (P.XLEN == 64) begin
assign SV39Mode = (SATP_MODE == `SV39); assign SV39Mode = (SATP_MODE == P.SV39);
// page fault if upper bits aren't all the same // page fault if upper bits aren't all the same
logic eq_63_47, eq_46_38; logic eq_63_47, eq_46_38;