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Working first cut of the cache changes moving the replay to a save/restore.

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The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
This commit is contained in:
Ross Thompson 2022-02-04 13:31:32 -06:00
parent ee3300bcd2
commit 7c1f7e335c
3 changed files with 96 additions and 71 deletions
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5
pipelined/src/cache/cache.sv vendored
View File

@ -106,6 +106,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic [NUMWAYS-1:0] VDWriteEnableWay; logic [NUMWAYS-1:0] VDWriteEnableWay;
logic SelFlush; logic SelFlush;
logic ResetOrFlushAdr, ResetOrFlushWay; logic ResetOrFlushAdr, ResetOrFlushWay;
logic save, restore;
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Read Path // Read Path
@ -125,7 +126,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
.WriteWordEnable(SRAMWordEnable), .WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMLineWayWriteEnable), .TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData), .WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay), .SelFlush, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .Victim(VictimWay), .Flush(FlushWay),
.save, .restore, .SelFlush,
.SelectedReadDataLine(ReadDataLineWay), .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay), .SelectedReadDataLine(ReadDataLineWay), .WayHit, .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
.InvalidateAll(InvalidateCacheM)); .InvalidateAll(InvalidateCacheM));
if(NUMWAYS > 1) begin:vict if(NUMWAYS > 1) begin:vict
@ -213,5 +215,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
.SRAMLineWriteEnable, .SelEvict, .SelFlush, .SRAMLineWriteEnable, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
.save, .restore,
.VDWriteEnable, .LRUWriteEn); .VDWriteEnable, .LRUWriteEn);
endmodule endmodule

25
pipelined/src/cache/cachefsm.sv vendored
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@ -74,6 +74,8 @@ module cachefsm
output logic FlushWayCntEn, output logic FlushWayCntEn,
output logic FlushAdrCntRst, output logic FlushAdrCntRst,
output logic FlushWayCntRst, output logic FlushWayCntRst,
output logic save,
output logic restore,
output logic VDWriteEnable output logic VDWriteEnable
); );
@ -141,7 +143,8 @@ module cachefsm
NextState = STATE_READY; NextState = STATE_READY;
CacheFetchLine = 1'b0; CacheFetchLine = 1'b0;
CacheWriteLine = 1'b0; CacheWriteLine = 1'b0;
save = 1'b0;
restore = 1'b0;
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
@ -178,7 +181,8 @@ module cachefsm
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO; NextState = STATE_CPU_BUSY_FINISH_AMO;
PreSelAdr = 2'b01; //PreSelAdr = 2'b01;
save = 1'b1;
end end
else begin else begin
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
@ -194,7 +198,8 @@ module cachefsm
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01; //PreSelAdr = 2'b01;
save = 1'b1;
end end
else begin else begin
NextState = STATE_READY; NextState = STATE_READY;
@ -210,7 +215,8 @@ module cachefsm
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01; //PreSelAdr = 2'b01;
save = 1'b1;
end end
else begin else begin
NextState = STATE_READY; NextState = STATE_READY;
@ -278,6 +284,7 @@ module cachefsm
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO; NextState = STATE_CPU_BUSY_FINISH_AMO;
save = 1'b1;
end end
else begin else begin
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
@ -289,7 +296,8 @@ module cachefsm
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01; //PreSelAdr = 2'b01;
save = 1'b1;
end end
else begin else begin
NextState = STATE_READY; NextState = STATE_READY;
@ -304,7 +312,8 @@ module cachefsm
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01; //PreSelAdr = 2'b01;
save = 1'b1;
end end
else begin else begin
NextState = STATE_READY; NextState = STATE_READY;
@ -325,9 +334,10 @@ module cachefsm
STATE_CPU_BUSY: begin STATE_CPU_BUSY: begin
PreSelAdr = 2'b00; PreSelAdr = 2'b00;
restore = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY; NextState = STATE_CPU_BUSY;
PreSelAdr = 2'b01; //PreSelAdr = 2'b01;
end end
else begin else begin
NextState = STATE_READY; NextState = STATE_READY;
@ -339,6 +349,7 @@ module cachefsm
SRAMWordWriteEnable = 1'b0; SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0; SetDirty = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
restore = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO; NextState = STATE_CPU_BUSY_FINISH_AMO;
end end

27
pipelined/src/cache/cacheway.sv vendored
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@ -51,6 +51,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
input logic InvalidateAll, input logic InvalidateAll,
input logic SelFlush, input logic SelFlush,
input logic Flush, input logic Flush,
input logic save, restore,
output logic [LINELEN-1:0] SelectedReadDataLine, output logic [LINELEN-1:0] SelectedReadDataLine,
output logic WayHit, output logic WayHit,
@ -59,10 +60,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits; logic [NUMLINES-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLine; logic [LINELEN-1:0] ReadDataLine, ReadDataLineRaw, ReadDataLineSaved;
logic [TAGLEN-1:0] ReadTag; logic [TAGLEN-1:0] ReadTag, ReadTagRaw, ReadTagSaved;
logic Valid; logic Valid, ValidRaw, ValidSaved;
logic Dirty; logic Dirty, DirtyRaw, DirtySaved;
logic SelData; logic SelData;
logic SelTag; logic SelTag;
@ -76,7 +77,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk), sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
.Adr(RAdr), .ReadData(ReadTag), .Adr(RAdr), .ReadData(ReadTagRaw),
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable)); .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
// AND portion of distributed tag multiplexer // AND portion of distributed tag multiplexer
@ -92,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
genvar words; genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr), sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), .ReadData(ReadDataLineRaw[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words])); .WriteEnable(WriteEnable & WriteWordEnable[words]));
end end
@ -115,7 +116,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable}, flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable},
{SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD}); {SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD});
assign Valid = ValidBits[RAdrD]; assign ValidRaw = ValidBits[RAdrD];
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Dirty Bits // Dirty Bits
@ -129,8 +130,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0;
end end
flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD}); flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
assign Dirty = DirtyBits[RAdrD]; assign DirtyRaw = DirtyBits[RAdrD];
flopenr #(1) cachedirtysavereg(clk, reset, save, DirtyRaw, DirtySaved);
mux2 #(1) saverestoredirtymux(DirtyRaw, DirtySaved, restore, Dirty);
end else assign Dirty = 1'b0; end else assign Dirty = 1'b0;
// save restore option of handling cpu busy
flopen #(TAGLEN+LINELEN) cachereadsavereg(clk, save, {ReadTagRaw, ReadDataLineRaw}, {ReadTagSaved, ReadDataLineSaved});
flopenr #(1) cachevalidsavereg(clk, reset, save, ValidRaw, ValidSaved);
mux2 #(1+TAGLEN+LINELEN) saverestoremux({ValidRaw, ReadTagRaw, ReadDataLineRaw}, {ValidSaved, ReadTagSaved, ReadDataLineSaved},
restore, {Valid, ReadTag, ReadDataLine});
endmodule endmodule