diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 6657079b7..608bf4668 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -255,60 +255,97 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
-add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
-add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
-add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
-add wave -noupdate -expand -group lsu -expand -group dcache -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Adr}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WAdr}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/MemPAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadDataBlockWayMaskedM}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadDataBlockWayMaskedM}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadDataBlockWayMaskedM}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadDataBlockWayMaskedM}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/BlockReplacementBits
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/ReplacementBits
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
@@ -452,8 +489,8 @@ add wave -noupdate /testbench/dut/hart/ExceptionM
add wave -noupdate /testbench/dut/hart/PendingInterruptM
add wave -noupdate /testbench/dut/hart/TrapM
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {3440406 ns} 0}
-quietly wave cursor active 1
+WaveRestoreCursors {{Cursor 6} {32245 ns} 0} {{Cursor 2} {32581 ns} 0} {{Cursor 3} {25666 ns} 0} {{Cursor 4} {2334 ns} 0}
+quietly wave cursor active 4
configure wave -namecolwidth 250
configure wave -valuecolwidth 297
configure wave -justifyvalue left
@@ -468,4 +505,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {0 ns} {12494134 ns}
+WaveRestoreZoom {2287 ns} {2569 ns}
diff --git a/wally-pipelined/src/cache/cacheLRU.sv b/wally-pipelined/src/cache/cacheLRU.sv
index e40deddc0..a7e7028ea 100644
--- a/wally-pipelined/src/cache/cacheLRU.sv
+++ b/wally-pipelined/src/cache/cacheLRU.sv
@@ -25,18 +25,36 @@
`include "wally-config.vh"
module cacheLRU
- #(NUMWAYS)
- (input logic [NUMWAYS-2:0] LRUIn,
- input logic [NUMWAYS-1:0] WayIn,
- output logic [NUMWAYS-2:0] LRUOut,
- output logic [NUMWAYS-1:0] VictimWay
+ #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
+ (input logic clk, reset,
+ input logic [NUMWAYS-1:0] WayIn,
+ output logic [NUMWAYS-1:0] VictimWay,
+ input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] MemPAdrM,
+ input logic [INDEXLEN-1:0] SRAMAdr,
+ input logic LRUWriteEn
);
// *** Only implements 2, 4, and 8 way
// I would like parametersize this in the future.
- logic [NUMWAYS-2:0] LRUEn, LRUMask;
- logic [$clog2(NUMWAYS)-1:0] EncVicWay;
+ logic [NUMWAYS-2:0] LRUEn, LRUMask;
+ logic [$clog2(NUMWAYS)-1:0] EncVicWay;
+ logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
+ logic [NUMWAYS-2:0] BlockReplacementBits;
+ logic [NUMWAYS-2:0] NewReplacement;
+
+ always_ff @(posedge clk, posedge reset) begin
+ if (reset) begin
+ for(int index = 0; index < NUMLINES; index++)
+ ReplacementBits[index] <= '0;
+ end else begin
+ BlockReplacementBits <= ReplacementBits[SRAMAdr];
+ if (LRUWriteEn) begin
+ ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
+ end
+ end
+ end
+
genvar index;
generate
@@ -44,10 +62,10 @@ module cacheLRU
assign LRUEn[0] = 1'b0;
- assign LRUOut[0] = WayIn[1];
+ assign NewReplacement[0] = WayIn[1];
- assign VictimWay[1] = ~LRUIn[0];
- assign VictimWay[0] = LRUIn[0];
+ assign VictimWay[1] = ~BlockReplacementBits[0];
+ assign VictimWay[0] = BlockReplacementBits[0];
end else if (NUMWAYS == 4) begin : FourWay
@@ -62,14 +80,14 @@ module cacheLRU
assign LRUMask[2] = WayIn[3] | WayIn[2];
for(index = 0; index < NUMWAYS-1; index++)
- assign LRUOut[index] = LRUEn[index] ? LRUMask[index] : LRUIn[index];
+ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index];
- assign EncVicWay[1] = LRUIn[2];
- assign EncVicWay[0] = LRUIn[2] ? LRUIn[0] : LRUIn[1];
+ assign EncVicWay[1] = BlockReplacementBits[2];
+ assign EncVicWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[0] : BlockReplacementBits[1];
onehotdecoder #(2)
waydec(.bin(EncVicWay),
- .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
+ .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
end else if (NUMWAYS == 8) begin : EightWay
@@ -92,21 +110,21 @@ module cacheLRU
assign LRUMask[0] = WayIn[0];
for(index = 0; index < NUMWAYS-1; index++)
- assign LRUOut[index] = LRUEn[index] ? LRUMask[index] : LRUIn[index];
+ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index];
- assign EncVicWay[2] = LRUIn[6];
- assign EncVicWay[1] = LRUIn[6] ? LRUIn[5] : LRUIn[2];
- assign EncVicWay[0] = LRUIn[6] ? LRUIn[5] ? LRUIn[4] : LRUIn[3] :
- LRUIn[2] ? LRUIn[1] : LRUIn[0];
+ assign EncVicWay[2] = BlockReplacementBits[6];
+ assign EncVicWay[1] = BlockReplacementBits[6] ? BlockReplacementBits[5] : BlockReplacementBits[2];
+ assign EncVicWay[0] = BlockReplacementBits[6] ? BlockReplacementBits[5] ? BlockReplacementBits[4] : BlockReplacementBits[3] :
+ BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0];
onehotdecoder #(3)
waydec(.bin(EncVicWay),
- .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
- VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
+ .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
+ VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
end
endgenerate
endmodule
-
+
diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index 3f2f08bf2..7ad9fa980 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -28,25 +28,25 @@
module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
parameter OFFSETLEN, parameter INDEXLEN)
(input logic clk,
- input logic reset,
+ input logic reset,
- input logic [$clog2(NUMLINES)-1:0] RAdr,
- input logic [`PA_BITS-1:OFFSETLEN+INDEXLEN] MemPAdrM,
- input logic WriteEnable,
- input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
- input logic TagWriteEnable,
- input logic [BLOCKLEN-1:0] WriteData,
- input logic SetValid,
- input logic ClearValid,
- input logic SetDirty,
- input logic ClearDirty,
- input logic SelEvict,
- input logic VictimWay,
+ input logic [$clog2(NUMLINES)-1:0] RAdr,
+ input logic [`PA_BITS-1:0] MemPAdrM,
+ input logic WriteEnable,
+ input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
+ input logic TagWriteEnable,
+ input logic [BLOCKLEN-1:0] WriteData,
+ input logic SetValid,
+ input logic ClearValid,
+ input logic SetDirty,
+ input logic ClearDirty,
+ input logic SelEvict,
+ input logic VictimWay,
- output logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM,
- output logic WayHit,
- output logic VictimDirtyWay,
- output logic [TAGLEN-1:0] VictimTagWay
+ output logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM,
+ output logic WayHit,
+ output logic VictimDirtyWay,
+ output logic [TAGLEN-1:0] VictimTagWay
);
logic [NUMLINES-1:0] ValidBits, DirtyBits;
@@ -74,7 +74,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
CacheTagMem(.clk(clk),
.Addr(RAdr),
.ReadData(ReadTag),
- .WriteData(MemPAdrM),
+ .WriteData(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.WriteEnable(TagWriteEnable));
assign WayHit = Valid & (ReadTag == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
@@ -87,16 +87,16 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
always_ff @(posedge clk, posedge reset) begin
if (reset)
ValidBits <= {NUMLINES{1'b0}};
- else if (SetValid & WriteEnable) ValidBits[RAdr] <= 1'b1;
- else if (ClearValid & WriteEnable) ValidBits[RAdr] <= 1'b0;
+ else if (SetValid & WriteEnable) ValidBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1'b1;
+ else if (ClearValid & WriteEnable) ValidBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1'b0;
Valid <= ValidBits[RAdr];
end
always_ff @(posedge clk, posedge reset) begin
if (reset)
DirtyBits <= {NUMLINES{1'b0}};
- else if (SetDirty & WriteEnable) DirtyBits[RAdr] <= 1'b1;
- else if (ClearDirty & WriteEnable) DirtyBits[RAdr] <= 1'b0;
+ else if (SetDirty & WriteEnable) DirtyBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1'b1;
+ else if (ClearDirty & WriteEnable) DirtyBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= 1'b0;
Dirty <= DirtyBits[RAdr];
end
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 00034d43a..cb0375281 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -93,19 +93,15 @@ module dcache
logic [INDEXLEN-1:0] SRAMAdr;
logic [BLOCKLEN-1:0] SRAMWriteData;
logic [BLOCKLEN-1:0] DCacheMemWriteData;
- logic SetValidM, ClearValidM;
- logic SetDirtyM, ClearDirtyM;
+ logic SetValid, ClearValid;
+ logic SetDirty, ClearDirty;
logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit;
logic CacheHit;
- logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
- logic [NUMWAYS-2:0] BlockReplacementBits;
- logic [NUMWAYS-2:0] NewReplacement;
logic [BLOCKLEN-1:0] ReadDataBlockM;
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
- logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
logic [WORDSPERLINE-1:0] SRAMWordEnable;
@@ -206,15 +202,15 @@ module dcache
MemWay[NUMWAYS-1:0](.clk,
.reset,
.RAdr(SRAMAdr),
- .MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
+ .MemPAdrM(MemPAdrM[`PA_BITS-1:0]),
.WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMBlockWayWriteEnableM),
.WriteData(SRAMWriteData),
- .SetValid(SetValidM),
- .ClearValid(ClearValidM),
- .SetDirty(SetDirtyM),
- .ClearDirty(ClearDirtyM),
+ .SetValid,
+ .ClearValid,
+ .SetDirty,
+ .ClearDirty,
.SelEvict,
.VictimWay,
.ReadDataBlockWayMaskedM,
@@ -222,28 +218,16 @@ module dcache
.VictimDirtyWay,
.VictimTagWay);
- always_ff @(posedge clk, posedge reset) begin
- if (reset) begin
- for(int index = 0; index < NUMLINES; index++)
- ReplacementBits[index] <= '0;
- end else begin
- BlockReplacementBits <= ReplacementBits[SRAMAdr];
- if (LRUWriteEn) begin
- ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
- end
- end
- end
-
- // *** TODO only supports 1, 2, 4, and 8 way
generate
if(NUMWAYS > 1) begin
- cacheLRU #(NUMWAYS)
- cacheLRU(.LRUIn(BlockReplacementBits),
+ cacheLRU #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
+ cacheLRU(.clk, .reset,
.WayIn(WayHit),
- .LRUOut(NewReplacement),
- .VictimWay(VictimWay));
+ .VictimWay,
+ .MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+ .SRAMAdr,
+ .LRUWriteEn);
end else begin
- assign NewReplacement = '0;
assign VictimWay = 1'b1;
end
endgenerate
@@ -339,25 +323,14 @@ module dcache
assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
-
-
- // mux between the CPU's write and the cache fetch.
- generate
- for(index = 0; index < WORDSPERLINE; index++) begin
- assign FinalWriteDataWordsM[((index+1)*`XLEN)-1 : (index*`XLEN)] = FinalWriteDataM;
- end
- endgenerate
- mux2 #(BLOCKLEN) WriteDataMux(.d0(FinalWriteDataWordsM),
+
+ mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}),
.d1(DCacheMemWriteData),
.s(SRAMBlockWriteEnableM),
.y(SRAMWriteData));
- // control path *** eventually move to own module.
-
-
-
localparam FetchCountThreshold = WORDSPERLINE - 1;
@@ -375,6 +348,9 @@ module dcache
assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
+
+ // control path *** eventually move to own module.
+
always_ff @(posedge clk, posedge reset)
if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState;
@@ -385,10 +361,10 @@ module dcache
DCacheStall = 1'b0;
SelAdrM = 2'b00;
PreCntEn = 1'b0;
- SetValidM = 1'b0;
- ClearValidM = 1'b0;
- SetDirtyM = 1'b0;
- ClearDirtyM = 1'b0;
+ SetValid = 1'b0;
+ ClearValid = 1'b0;
+ SetDirty = 1'b0;
+ ClearDirty = 1'b0;
SRAMWordWriteEnableM = 1'b0;
SRAMBlockWriteEnableM = 1'b0;
CntReset = 1'b0;
@@ -427,7 +403,7 @@ module dcache
end
else begin
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
@@ -451,7 +427,7 @@ module dcache
SelAdrM = 2'b01;
DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
LRUWriteEn = 1'b1;
if(StallWtoDCache) begin
@@ -522,8 +498,8 @@ module dcache
DCacheStall = 1'b1;
NextState = STATE_MISS_READ_WORD;
SelAdrM = 2'b01;
- SetValidM = 1'b1;
- ClearDirtyM = 1'b1;
+ SetValid = 1'b1;
+ ClearDirty = 1'b1;
CommittedM = 1'b1;
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
end
@@ -551,7 +527,7 @@ module dcache
end
else begin
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
@@ -569,7 +545,7 @@ module dcache
STATE_MISS_WRITE_WORD: begin
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
SelAdrM = 2'b01;
CommittedM = 1'b1;
LRUWriteEn = 1'b1;
@@ -703,8 +679,8 @@ module dcache
DCacheStall = 1'b1;
NextState = STATE_PTW_READ_MISS_READ_WORD;
SelAdrM = 2'b01;
- SetValidM = 1'b1;
- ClearDirtyM = 1'b1;
+ SetValid = 1'b1;
+ ClearDirty = 1'b1;
CommittedM = 1'b1;
//LRUWriteEn = 1'b1;
end
@@ -749,7 +725,7 @@ module dcache
end
else begin
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
@@ -824,7 +800,7 @@ module dcache
SelAdrM = 2'b01;
DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
LRUWriteEn = 1'b1;
if(StallWtoDCache) begin
@@ -908,8 +884,8 @@ module dcache
DCacheStall = 1'b1;
NextState = STATE_PTW_FAULT_MISS_READ_WORD;
SelAdrM = 2'b01;
- SetValidM = 1'b1;
- ClearDirtyM = 1'b1;
+ SetValid = 1'b1;
+ ClearDirty = 1'b1;
CommittedM = 1'b1;
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
end
@@ -942,7 +918,7 @@ module dcache
STATE_PTW_FAULT_MISS_WRITE_WORD: begin
SRAMWordWriteEnableM = 1'b1;
- SetDirtyM = 1'b1;
+ SetDirty = 1'b1;
SelAdrM = 2'b01;
DCacheStall = 1'b1;
CommittedM = 1'b1;