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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)

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Kip Macsai-Goren 2022-04-22 22:45:23 +00:00
parent 27920d3504
commit 7bc6943527
4 changed files with 5 additions and 9 deletions
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2
pipelined/src/ifu/ifu.sv
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@ -65,7 +65,6 @@ module ifu (
output logic InstrPageFaultF, output logic InstrPageFaultF,
output logic IllegalIEUInstrFaultD, output logic IllegalIEUInstrFaultD,
output logic InstrMisalignedFaultM, output logic InstrMisalignedFaultM,
output logic [`XLEN-1:0] InstrMisalignedAdrM,
input logic ExceptionM, input logic ExceptionM,
// mmu management // mmu management
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
@ -330,7 +329,6 @@ module ifu (
// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec. // Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE; assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
// Instruction and PC/PCLink pipeline registers // Instruction and PC/PCLink pipeline registers
mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD); mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);

4
pipelined/src/privileged/privileged.sv
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@ -57,7 +57,7 @@ module privileged (
input logic StoreAmoMisalignedFaultM, input logic StoreAmoMisalignedFaultM,
input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, input logic TimerIntM, MExtIntM, SExtIntM, SwIntM,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [`XLEN-1:0] IEUAdrM,
input logic [4:0] SetFflagsM, input logic [4:0] SetFflagsM,
// Trap signals from pmp/pma in mmu // Trap signals from pmp/pma in mmu
@ -222,7 +222,7 @@ module privileged (
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW,
.STATUS_MIE, .STATUS_SIE, .STATUS_MIE, .STATUS_SIE,
.PCM, .PCM,
.InstrMisalignedAdrM, .IEUAdrM, .IEUAdrM,
.InstrM, .InstrM,
.InstrValidM, .CommittedM, .DivE, .InstrValidM, .CommittedM, .DivE,
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,

4
pipelined/src/privileged/trap.sv
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@ -44,7 +44,7 @@ module trap (
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW,
input logic STATUS_MIE, STATUS_SIE, input logic STATUS_MIE, STATUS_SIE,
input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [`XLEN-1:0] IEUAdrM,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic InstrValidM, CommittedM, DivE, input logic InstrValidM, CommittedM, DivE,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
@ -152,7 +152,7 @@ module trap (
// Technically // Technically
always_comb always_comb
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM; if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM; else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM; else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
else if (BreakpointFaultM) NextFaultMtvalM = PCM; else if (BreakpointFaultM) NextFaultMtvalM = PCM;

4
pipelined/src/wally/wallypipelinedcore.sv
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@ -82,7 +82,6 @@ module wallypipelinedcore (
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
logic LoadMisalignedFaultM, LoadAccessFaultM; logic LoadMisalignedFaultM, LoadAccessFaultM;
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
logic [`XLEN-1:0] InstrMisalignedAdrM;
logic InvalidateICacheM, FlushDCacheM; logic InvalidateICacheM, FlushDCacheM;
logic PCSrcE; logic PCSrcE;
logic CSRWritePendingDEM; logic CSRWritePendingDEM;
@ -190,7 +189,6 @@ module wallypipelinedcore (
// Faults // Faults
.IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalBaseInstrFaultD, .InstrPageFaultF,
.IllegalIEUInstrFaultD, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
.InstrMisalignedAdrM,
// mmu management // mmu management
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
@ -332,7 +330,7 @@ module wallypipelinedcore (
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM,
.MTIME_CLINT, .MTIME_CLINT,
.InstrMisalignedAdrM, .IEUAdrM, .IEUAdrM,
.SetFflagsM, .SetFflagsM,
// Trap signals from pmp/pma in mmu // Trap signals from pmp/pma in mmu
// *** do these need to be split up into one for dmem and one for ifu? // *** do these need to be split up into one for dmem and one for ifu?