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Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.

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This commit is contained in:
Rose Thompson 2024-07-23 13:18:03 -05:00
parent f20b82b14e
commit 7bc04702a7
2 changed files with 6 additions and 3 deletions
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0
src/wally/priorityaomux.sv → src/rvvi/priorityaomux.sv
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7
src/rvvi/rvvisynth.sv
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@ -30,7 +30,8 @@
`define FPGA 0
module rvvisynth import cvw::*; #(parameter cvw_t P,
parameter integer MAX_CSRS, TOTAL_CSRS = 36)(
parameter integer MAX_CSRS = 3,
parameter integer TOTAL_CSRS = 36)(
input logic clk, reset,
input logic StallE, StallM, StallW, FlushE, FlushM, FlushW,
// required
@ -64,6 +65,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
logic [TOTAL_CSRS-1:0] CSRWen [MAX_CSRS-1:0];
logic [11:0] CSRAddr [MAX_CSRS-1:0];
logic [MAX_CSRS-1:0] EnabledCSRs;
logic [MAX_CSRS-1:0] CSRCountShort;
logic [11:0] CSRCount;
logic [177+P.XLEN-1:0] Required;
logic [10+2*P.XLEN-1:0] Registers;
@ -109,7 +111,8 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
assign CSRs[(index+1) * (P.XLEN + 12)- 1: index * (P.XLEN + 12)] = {CSRValue[index], CSRAddr[index]};
assign EnabledCSRs[index] = |CSRWenShort;
end
assign CSRCount = +EnabledCSRs;
assign CSRCountShort = +EnabledCSRs;
assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort};
assign rvvi = {CSRs, Registers, Required};
endmodule