fix spacing in sha_instructions for style

src/ieu/sha_instructions/sha256sig0.sv

@@ -25,9 +25,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha256sig0 #(parameter WIDTH=32) (
+module sha256sig0 #(parameter WIDTH=32) 
-  input  logic [WIDTH-1:0] rs1,
+   (input  logic [WIDTH-1:0] rs1,
-  output logic [WIDTH-1:0] result);
+    output logic [WIDTH-1:0] result);
 
    logic [31:0] 	   ror7;
    logic [31:0] 	   ror18;

src/ieu/sha_instructions/sha512sig0.sv

@@ -25,7 +25,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig0 (input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sig0(input  logic [63:0] rs1, output logic [63:0] result);
 
    logic [63:0] ror1;
    logic [63:0] ror8;

src/ieu/sha_instructions/sha512sig1.sv

@@ -25,7 +25,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig1 (input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sig1(input  logic [63:0] rs1, output logic [63:0] result);
 
    logic [63:0] ror19;
    logic [63:0] ror61;

src/ieu/sha_instructions/sha512sum0.sv

@@ -25,7 +25,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sum0 (input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sum0(input  logic [63:0] rs1, output logic [63:0] result);
 
    logic [63:0] ror28;
    logic [63:0] ror34;

src/ieu/sha_instructions/sha512sum1.sv

@@ -25,7 +25,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sum1 (input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sum1(input  logic [63:0] rs1, output logic [63:0] result);
 
    logic [63:0] ror14;
    logic [63:0] ror18;