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Moved cacheable signal into cache.

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This commit is contained in:
Ross Thompson 2022-03-08 16:34:02 -06:00
parent 099fc34c10
commit 7b96b3f73c
4 changed files with 18 additions and 20 deletions
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6
pipelined/src/cache/cache.sv vendored
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@ -51,6 +51,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
// lsu control // lsu control
input logic IgnoreRequestTLB, input logic IgnoreRequestTLB,
input logic IgnoreRequestTrapM, input logic IgnoreRequestTrapM,
input logic Cacheable,
// Bus fsm interface // Bus fsm interface
output logic CacheFetchLine, output logic CacheFetchLine,
output logic CacheWriteLine, output logic CacheWriteLine,
@ -99,6 +100,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
logic ResetOrFlushAdr, ResetOrFlushWay; logic ResetOrFlushAdr, ResetOrFlushWay;
logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SelectedWay;
logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
logic [1:0] CacheRW, CacheAtomic;
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Read Path // Read Path
@ -174,8 +176,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Cache FSM // Cache FSM
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
assign CacheRW = Cacheable ? RW : 2'b00;
assign CacheAtomic = Cacheable ? Atomic : 2'b00;
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
.RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty, .ClearValid, .ClearDirty, .SetDirty,

18
pipelined/src/cache/cachefsm.sv vendored
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@ -34,8 +34,8 @@ module cachefsm
(input logic clk, (input logic clk,
input logic reset, input logic reset,
// inputs from IEU // inputs from IEU
input logic [1:0] RW, input logic [1:0] CacheRW,
input logic [1:0] Atomic, input logic [1:0] CacheAtomic,
input logic FlushCache, input logic FlushCache,
// hazard inputs // hazard inputs
input logic CPUBusy, input logic CPUBusy,
@ -109,10 +109,10 @@ module cachefsm
// using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB.
assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
assign AMO = Atomic[1] & (&RW); assign AMO = CacheAtomic[1] & (&CacheRW);
assign DoAMO = AMO & ~IgnoreRequest; assign DoAMO = AMO & ~IgnoreRequest;
assign DoRead = RW[1] & ~IgnoreRequest; assign DoRead = CacheRW[1] & ~IgnoreRequest;
assign DoWrite = RW[0] & ~IgnoreRequest; assign DoWrite = CacheRW[0] & ~IgnoreRequest;
assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit;
assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit;
@ -145,7 +145,7 @@ module cachefsm
STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY;
else NextState = STATE_MISS_WRITE_CACHE_LINE; else NextState = STATE_MISS_WRITE_CACHE_LINE;
STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD;
STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; STATE_MISS_READ_WORD: if(CacheRW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD;
else NextState = STATE_MISS_READ_WORD_DELAY; else NextState = STATE_MISS_READ_WORD_DELAY;
STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY; STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY; else NextState = STATE_READY;
@ -213,14 +213,14 @@ module cachefsm
// handle cpu stall. // handle cpu stall.
assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY; assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY;
assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) | assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) |
(CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) | (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | CacheRW[1]) & CPUBusy) |
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
// **** can this be simplified? // **** can this be simplified?
assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
// use the raw requests as we don't want IgnoreRequestTrapM in the critical path // use the raw requests as we don't want IgnoreRequestTrapM in the critical path
(CurrState == STATE_READY & ((AMO | RW[0]) & CacheHit)) | // changes if store delay hazard removed (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
(CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |
(CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_FETCH_DONE) |

7
pipelined/src/ifu/ifu.sv
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@ -210,9 +210,6 @@ module ifu (
if(CACHE_ENABLED) begin : icache if(CACHE_ENABLED) begin : icache
logic [1:0] IFURWF;
assign IFURWF = CacheableF ? 2'b10 : 2'b00;
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
@ -221,10 +218,10 @@ module ifu (
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheFetchLine(ICacheFetchLine), .CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(), .ReadDataLine(ReadDataLine), .CacheWriteLine(), .ReadDataLine(ReadDataLine),
.save, .restore, .save, .restore, .Cacheable(CacheableF),
.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
.FinalWriteData('0), .FinalWriteData('0),
.RW(IFURWF), .RW(2'b10),
.Atomic('0), .FlushCache('0), .Atomic('0), .FlushCache('0),
.NextAdr(PCNextFSpill[11:0]), .NextAdr(PCNextFSpill[11:0]),
.PAdr(PCPF), .PAdr(PCPF),

7
pipelined/src/lsu/lsu.sv
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@ -230,14 +230,11 @@ module lsu (
if(CACHE_ENABLED) begin : dcache if(CACHE_ENABLED) begin : dcache
logic [1:0] RW, Atomic;
assign RW = CacheableM ? LSURWM : 2'b00; // AND gate // *** move and gates into cache
assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache(
.clk, .reset, .CPUBusy, .save, .restore, .RW, .Atomic, .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM),
.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
.FinalWriteData(FinalWriteDataM), .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM), .CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM),