diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
index 8b08e275d..4042326a8 100644
--- a/sim/verilator/Makefile
+++ b/sim/verilator/Makefile
@@ -30,17 +30,21 @@ obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
 	mkdir -p obj_dir_non_profiling
 	time verilator \
 	--Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \
+	-cc --binary \
 	$(OPT) $(PARAMS) $(NONPROF) \
-	--timescale "1ns/1ns" --timing --binary --top-module testbench  --relative-includes \
+	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
 	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
+	wrapper.c \
 	${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
 	
 obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
 	mkdir -p obj_dir_profiling
 	time verilator \
 	--Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \
+	-cc --binary \
 	--prof-cfuncs $(OPT) $(PARAMS) \
-	--timescale "1ns/1ns" --timing --binary --top-module testbench  --relative-includes \
+	--timescale "1ns/1ns" --timing --top-module testbench  --relative-includes \
+	wrapper.c \
 	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
 
 questa:
diff --git a/sim/verilator/wrapper.c b/sim/verilator/wrapper.c
new file mode 100644
index 000000000..6589a3848
--- /dev/null
+++ b/sim/verilator/wrapper.c
@@ -0,0 +1,7 @@
+#include <stdlib.h>
+
+#include "Vtestbench__Dpi.h"
+
+const char *getenvval(const char *pszName) {
+    return ((const char *) getenv(pszName));
+}
\ No newline at end of file
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 035e625b7..3a4eeb617 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -34,7 +34,11 @@
 `endif
 
 import cvw::*;
+`ifdef VERILATOR
+import "DPI-C" function string getenvval(input string env_name);
+`else
 import "DPI-C" function string getenv(input string env_name);
+`endif
 
 module testbench;
   /* verilator lint_off WIDTHTRUNC */
@@ -60,7 +64,12 @@ module testbench;
   // Variables that can be overwritten with $value$plusargs at start of simulation
   string       TEST;
   integer      INSTR_LIMIT;
+`ifdef VERILATOR
+  string       RISCV_DIR = getenvval("RISCV"); // "/opt/riscv";
+`else
   string       RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
+`endif
+  // string       RISCV_DIR = "/opt/riscv";
 
   // DUT signals
   logic [P.AHBW-1:0]    HRDATAEXT;