Merge branch 'main' into cache

wally-pipelined/config/rv32ic/wally-config.vh

@@ -98,4 +98,5 @@
 
 `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
-`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0

wally-pipelined/config/rv64ic/wally-config.vh

@@ -101,4 +101,5 @@
 
 `define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
-`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -97,4 +97,5 @@
 
 `define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
 `define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
-`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0

wally-pipelined/config/rv64imc/wally-config.vh

@@ -99,6 +99,7 @@
 /* verilator lint_off ASSIGNDLY */
 /* verilator lint_off PINCONNECTEMPTY */
 
-`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
+`define TWO_BIT_PRELOAD "../config/rv64imc/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
+`define BTB_PRELOAD "../config/rv64imc/BTBPredictor.txt"
 `define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0

wally-pipelined/src/ifu/bpred.sv

@@ -102,6 +102,19 @@ module bpred
 				   .PCSrcE(PCSrcE),
 				   .UpdatePrediction(UpdateBPPredE));
     end 
+    else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
+
+      localHistoryPredictor DirPredictor(.clk(clk),
+				   .reset(reset),
+				   .*, // Stalls and flushes
+				   .LookUpPC(PCNextF),
+				   .Prediction(BPPredF),
+				   // update
+				   .UpdatePC(PCE),
+				   .UpdateEN(InstrClassE[0] & ~StallE),
+				   .PCSrcE(PCSrcE),
+				   .UpdatePrediction(UpdateBPPredE));
+    end 
   endgenerate
 
 

wally-pipelined/src/ifu/globalHistoryPredictor.sv

@@ -37,16 +37,17 @@ module globalHistoryPredictor
    output logic [1:0] 	   Prediction,
    // update
    input logic [`XLEN-1:0] UpdatePC,
-   input logic 		   UpdateEN, PCSrcE, /// *** need to add as input from bpred.sv 
+   input logic 		   UpdateEN, PCSrcE, 
    input logic [1:0] 	   UpdatePrediction
    
    );
-   logic [k-1:0] GHRF, GHRD, GHRE;
+   logic [k-1:0] GHRF, GHRD, GHRE, GHRENext;
+   assign GHRENext = {PCSrcE, GHRE[k-1:1]}; 
 
     flopenr #(k) GlobalHistoryRegister(.clk(clk),
             .reset(reset),
             .en(UpdateEN),
-            .d({PCSrcE, GHRF[k-1:1] }),
+            .d(GHRENext),
             .q(GHRF));
 
 
@@ -54,11 +55,8 @@ module globalHistoryPredictor
   logic [1:0] 		   PredictionMemory;
   logic 		   DoForwarding, DoForwardingF;
   logic [1:0] 		   UpdatePredictionF;
-  
+ 
-  // for gshare xor the PC with the GHR 
+
-  // TODO: change in sram memory2 module
-  // assign UpdatePCIndex = GHRE ^ UpdatePC;
-  //  assign LookUpPCIndex = LookUpPC ^ GHR;  
   // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
   // GHR referes to the address that the past k branches points to in the prediction stage 
   // GHRE refers to the address that the past k branches points to in the exectution stage
@@ -66,8 +64,8 @@ module globalHistoryPredictor
 				.reset(reset),
 				.RA1(GHRF),
 				.RD1(PredictionMemory),
-				.REN1(1'b1),
+				.REN1(~StallF),
-				.WA1(GHRE),
+				.WA1(GHRENext),
 				.WD1(UpdatePrediction),
 				.WEN1(UpdateEN),
 				.BitWEN1(2'b11));

wally-pipelined/src/ifu/localHistoryPredictor.sv

@@ -0,0 +1,138 @@
+///////////////////////////////////////////
+// locallHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module localHistoryPredictor
+  #(  parameter int m = 6, // 2^m = number of local history branches
+      parameter int k = 10 // number of past branches stored
+    )
+  (input logic clk,
+   input logic 		   reset,
+   input logic 		    StallF, StallD, StallE, FlushF, FlushD, FlushE,
+   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0] 	   Prediction,
+   // update
+   input logic [`XLEN-1:0] UpdatePC,
+   input logic 		   UpdateEN, PCSrcE, 
+   input logic [1:0] 	   UpdatePrediction
+   
+   );
+
+   logic [2**m-1:0][k-1:0] LHRNextF;
+   logic [k-1:0]       LHRF, LHRD, LHRE, LHRENext, ForwardLHRNext;
+   logic [m-1:0] 	   LookUpPCIndex, UpdatePCIndex;
+   logic [1:0] 		   PredictionMemory;
+   logic 		   DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
+   logic [1:0] 		   UpdatePredictionF;
+
+   assign LHRENext = {PCSrcE, LHRE[k-1:1]}; 
+   assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
+   assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};  
+
+// INCASE we do ahead pipelining
+//    SRAM2P1R1W #(m,k) LHR(.clk(clk)),
+//                 .reset(reset),
+//                 .RA1(LookUpPCIndex), // need hashing function to get correct PC address 
+//                 .RD1(LHRF),
+//                 .REN1(~StallF),
+//                 .WA1(UpdatePCIndex),
+//                 .WD1(LHRENExt),
+//                 .WEN1(UpdateEN),
+//                 .BitWEN1(2'b11));  
+
+genvar index;
+generate
+    for (index = 0; index < 2**m; index = index +1) begin
+      
+        flopenr #(k) LocalHistoryRegister(.clk(clk),
+                .reset(reset),
+                .en(UpdateEN && (index == UpdatePCIndex)),
+                .d(LHRENext),
+                .q(LHRNextF[index]));
+    end 
+endgenerate
+
+// need to forward when updating to the same address as reading.
+// first we compare to see if the update and lookup addreses are the same
+assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
+assign ForwardLHRNext = DoForwarding ? LHRENext :LHRNextF[LookUpPCIndex]; 
+
+  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
+  // LHR referes to the address that the past k branches points to in the prediction stage 
+  // LHRE refers to the address that the past k branches points to in the exectution stage
+    SRAM2P1R1W #(k, 2) PHT(.clk(clk), 
+				.reset(reset),
+				.RA1(ForwardLHRNext),
+				.RD1(PredictionMemory),
+				.REN1(~StallF),
+				.WA1(LHRENext),
+				.WD1(UpdatePrediction),
+				.WEN1(UpdateEN),
+				.BitWEN1(2'b11));
+
+
+  
+assign DoForwardingPHT = LHRENext == ForwardLHRNext; 
+
+  // register the update value and the forwarding signal into the Fetch stage
+  // TODO: add stall logic ***
+  flopr #(1) DoForwardingReg(.clk(clk),
+			     .reset(reset),
+			     .d(DoForwardingPHT),
+			     .q(DoForwardingPHTF));
+  
+  flopr #(2) UpdatePredictionReg(.clk(clk),
+				 .reset(reset),
+				 .d(UpdatePrediction),
+				 .q(UpdatePredictionF));
+
+  assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
+  
+  //pipeline for LHR
+  flopenrc #(k) LHRFReg(.clk(clk),
+      .reset(reset),
+      .en(~StallF),
+      .clear(FlushF),
+      .d(ForwardLHRNext),
+      .q(LHRF));
+
+  flopenrc #(k) LHRDReg(.clk(clk),
+        .reset(reset),
+        .en(~StallD),
+        .clear(FlushD),
+        .d(LHRF),
+        .q(LHRD));
+    
+   flopenrc #(k) LHREReg(.clk(clk),
+        .reset(reset),
+        .en(~StallE),
+        .clear(FlushE),
+        .d(LHRD),
+        .q(LHRE));
+
+endmodule

wally-pipelined/src/privileged/csri.sv

@@ -41,6 +41,7 @@ module csri #(parameter
     input  logic [`XLEN-1:0] CSRWriteValM
   );
 
+  logic [9:0]      IP_REGW_writeable;
   logic [11:0]     IntInM, IP_REGW, IE_REGW;
   logic [11:0]     MIP_WRITE_MASK, SIP_WRITE_MASK;
   logic            WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
@@ -49,13 +50,13 @@ module csri #(parameter
   // assumes no N-mode user interrupts
 
   always_comb begin
-    IntInM      = 0; // *** does this overwriting technique really synthesize
+    IntInM     = 0; // *** does this overwriting technique really synthesize
-    IP_REGW[11] = ExtIntM & ~MIDELEG_REGW[9];   // MEIP
+    IntInM[11] = ExtIntM & ~MIDELEG_REGW[9];   // MEIP
-    IntInM[9]   = ExtIntM &  MIDELEG_REGW[9];   // SEIP
+    IntInM[9]  = ExtIntM &  MIDELEG_REGW[9];   // SEIP
-    IntInM[7]   = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
+    IntInM[7]  = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
-    IntInM[5]   = TimerIntM &  MIDELEG_REGW[5]; // STIP
+    IntInM[5]  = TimerIntM &  MIDELEG_REGW[5]; // STIP
-    IntInM[3]   = SwIntM & ~MIDELEG_REGW[1];    // MSIP
+    IntInM[3]  = SwIntM & ~MIDELEG_REGW[1];    // MSIP
-    IntInM[1]   = SwIntM &  MIDELEG_REGW[1];    // SSIP
+    IntInM[1]  = SwIntM &  MIDELEG_REGW[1];    // SSIP
    end
 
   // Interrupt Write Enables
@@ -77,11 +78,11 @@ module csri #(parameter
       assign SIP_WRITE_MASK = 12'h000;
     end
     always @(posedge clk, posedge reset) begin
-      if (reset)          IP_REGW[9:0] <= 10'b0;
+      if (reset)          IP_REGW_writeable <= 10'b0;
-      else if (WriteMIPM) IP_REGW[9:0] <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
+      else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
-      else if (WriteSIPM) IP_REGW[9:0] <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
+      else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
 //      else if (WriteUIPM) IP_REGW = (CSRWriteValM & 12'hBBB) | (NextIPM & 12'h080); // MTIP unclearable
-      else                IP_REGW[9:0] <= IP_REGW[9:0] | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes
+      else                IP_REGW_writeable <= IP_REGW_writeable | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes
     end
     always @(posedge clk, posedge reset) begin
       if (reset)          IE_REGW <= 12'b0;
@@ -94,6 +95,9 @@ module csri #(parameter
   // restricted views of registers
   generate
     always_comb begin
+      // Add MEIP read-only signal
+      IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
+
       // Machine Mode
       MIP_REGW = IP_REGW;
       MIE_REGW = IE_REGW;

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -72,6 +72,9 @@ module wallypipelinedsoc (
   // instantiate processor and memories
   wallypipelinedhart hart(.*);
 
-  imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
+  // *** Temporary driving of access fault to low until PMA checker is complete
+  assign InstrAccessFaultF = '0;
+  // instructions now come from uncore memory. This line can be removed at any time.
+  // imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
   uncore uncore(.HWDATAIN(HWDATA), .*);
 endmodule

wally-pipelined/testbench/testbench-busybear.sv

@@ -99,8 +99,6 @@ module testbench_busybear();
   initial begin
     $readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
     $readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.uncore.dtim.RAM);
-    $readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.imem.bootram, 'h1000 >> 3);
-    $readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.imem.RAM);
     $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
   end

wally-pipelined/testbench/testbench-coremark.sv

@@ -78,7 +78,6 @@ module testbench();
       totalerrors = 0;
       // read test vectors into memory
       memfilename = tests[0];
-      $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       for(j=18710; j < 65535; j = j+1)
         dut.uncore.dtim.RAM[j] = 64'b0;

wally-pipelined/testbench/testbench-coremark_bare.sv

@@ -80,7 +80,6 @@ module testbench();
       totalerrors = 0;
       // read test vectors into memory
       memfilename = tests[0];
-      $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       for(j=268437702; j < 268566528; j = j+1)
         dut.uncore.dtim.RAM[j] = 64'b0;

wally-pipelined/testbench/testbench-imperas.sv

@@ -451,7 +451,6 @@ module testbench();
       end
       // read test vectors into memory
       memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-      $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
@@ -526,7 +525,6 @@ module testbench();
         end
         else begin
           memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-          $readmemh(memfilename, dut.imem.RAM);
           $readmemh(memfilename, dut.uncore.dtim.RAM);
           $display("Read memfile %s", memfilename);
 	  ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};

wally-pipelined/testbench/testbench-privileged.sv

@@ -116,7 +116,6 @@ module testbench();
       end
       // read test vectors into memory
       memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-      $readmemh(memfilename, dut.imem.RAM);
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
@@ -191,7 +190,6 @@ module testbench();
         end
         else begin
           memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-          $readmemh(memfilename, dut.imem.RAM);
           $readmemh(memfilename, dut.uncore.dtim.RAM);
           $display("Read memfile %s", memfilename);
     ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};