diff --git a/wally-pipelined/src/datapath.sv b/wally-pipelined/src/datapath.sv
index 77b9b6f10..1ca042e83 100644
--- a/wally-pipelined/src/datapath.sv
+++ b/wally-pipelined/src/datapath.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module datapath (
+module datapath #(parameter PCSTART = 32'h80000000) (
   input logic clk, reset,
   // Fetch stage signals
   input  logic        StallF,
@@ -110,7 +110,7 @@ module datapath (
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
 
   // Fetch stage pipeline register and logic; also Ex stage for branches
-  pclogic pclogic(.*);
+  pclogic #(PCSTART) pclogic(.*);
 
   // Decode stage pipeline register and logic
   flopenl #(32)    InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD);
diff --git a/wally-pipelined/src/pclogic.sv b/wally-pipelined/src/pclogic.sv
index 290c00591..5ae83181f 100644
--- a/wally-pipelined/src/pclogic.sv
+++ b/wally-pipelined/src/pclogic.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module pclogic (
+module pclogic #(parameter PCSTART) (
   input  logic            clk, reset,
   input  logic            StallF, PCSrcE, 
   input  logic [31:0]     InstrF,
@@ -39,7 +39,7 @@ module pclogic (
   logic [`XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE;
 //  logic [`XLEN-1:0] ResetVector = 'h100;
 //  logic [`XLEN-1:0] ResetVector = 'he4;
-  logic [`XLEN-1:0] ResetVector = {{(`XLEN-32){1'b0}}, 32'h80000000};
+  logic [`XLEN-1:0] ResetVector = {{(`XLEN-32){1'b0}}, PCSTART};
   logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
   logic StallExceptResolveBranchesF, PrivilegedChangePCM;
   logic [`XLEN-3:0] PCPlusUpperF;
diff --git a/wally-pipelined/src/testbench-busybear.sv b/wally-pipelined/src/testbench-busybear.sv
index 405feaefa..e6c8cb289 100644
--- a/wally-pipelined/src/testbench-busybear.sv
+++ b/wally-pipelined/src/testbench-busybear.sv
@@ -1,15 +1,15 @@
-`include "wally-macros.sv"
+`include "wally-config.vh"
 
-module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOUNTERS = 1)();
+module testbench_busybear();
 
   logic            clk, reset;
-  logic [XLEN-1:0] WriteDataM, DataAdrM;
+  logic [`XLEN-1:0] WriteDataM, DataAdrM;
   logic [1:0]      MemRWM;
   logic [31:0]     GPIOPinsIn;
   logic [31:0]     GPIOPinsOut, GPIOPinsEn;
 
   // instantiate device to be tested
-  logic [XLEN-1:0] PCF, ReadDataM;
+  logic [`XLEN-1:0] PCF, ReadDataM;
   logic [31:0] InstrF;
   logic [7:0]  ByteMaskM;
   logic        InstrAccessFaultF, DataAccessFaultM;
@@ -21,7 +21,7 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
   assign DataAccessFaultM = 0;
    
   // instantiate processor and memories
-  wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) dut(.ALUResultM(DataAdrM), .*);
+  wallypipelinedhart #(.PCSTART('h1000)) dut(.ALUResultM(DataAdrM), .*);
 
   // initialize test
   initial
@@ -127,7 +127,7 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
   string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
   logic [31:0] InstrW;
   instrNameDecTB dec(InstrF, InstrFName);
-  instrTrackerTB #(XLEN) it(clk, reset, dut.dp.FlushE,
+  instrTrackerTB it(clk, reset, dut.dp.FlushE,
                 dut.dp.InstrDecompD, dut.dp.InstrE,
                 dut.dp.InstrM,  InstrW,
                 InstrDName, InstrEName, InstrMName, InstrWName);
diff --git a/wally-pipelined/src/wallypipelinedhart.sv b/wally-pipelined/src/wallypipelinedhart.sv
index 25702a84a..54e55d756 100644
--- a/wally-pipelined/src/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wallypipelinedhart.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module wallypipelinedhart (
+module wallypipelinedhart #(parameter PCSTART = 32'h80000000) (
   input  logic            clk, reset,
   output logic [`XLEN-1:0] PCF,
   input  logic [31:0]     InstrF,
@@ -70,7 +70,7 @@ module wallypipelinedhart (
   logic       FloatRegWriteW;
            
   controller c(.*);
-  datapath   dp(.*);
+  datapath #(PCSTART) dp(.*);
   hazard     hz(.*);	
 
   // add FPU here, with SetFflagsM, FRM_REGW