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Modified dcache to ensure nontranslated index is used.

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This commit is contained in:
Ross Thompson 2022-01-04 10:53:53 -06:00
parent 1ea267cab5
commit 7ac412eb8e
3 changed files with 5 additions and 4 deletions
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5
wally-pipelined/src/cache/dcache.sv vendored
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@ -38,9 +38,10 @@ module dcache
input logic FlushDCacheM, input logic FlushDCacheM,
input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits. input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] LsuPAdrM, // physical address input logic [`PA_BITS-1:0] LsuPAdrM, // physical address
input logic [11:0] PreLsuPAdrM, // physical or virtual address
input logic [`XLEN-1:0] FinalWriteDataM, input logic [`XLEN-1:0] FinalWriteDataM,
output logic [`XLEN-1:0] ReadDataWordM, output logic [`XLEN-1:0] ReadDataWordM,
output logic DCacheCommittedM, output logic DCacheCommittedM,
// Bus fsm interface // Bus fsm interface
input logic IgnoreRequest, input logic IgnoreRequest,
@ -122,7 +123,7 @@ module dcache
mux3 #(INDEXLEN) mux3 #(INDEXLEN)
AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** optimize change to virtual address. .d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** optimize change to virtual address.
.d2(FlushAdr), .d2(FlushAdr),
.s(SelAdrM), .s(SelAdrM),
.y(RAdr)); .y(RAdr));

2
wally-pipelined/src/cache/dcachefsm.sv vendored
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@ -35,7 +35,7 @@ module dcachefsm
// hazard inputs // hazard inputs
input logic CPUBusy, input logic CPUBusy,
input logic CacheableM, input logic CacheableM,
// hptw inputs // interlock fsm
input logic IgnoreRequest, input logic IgnoreRequest,
// Bus inputs // Bus inputs
input logic DCacheBusAck, input logic DCacheBusAck,

2
wally-pipelined/src/lsu/lsu.sv
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@ -307,7 +307,7 @@ module lsu
generate generate
if(`MEM_DCACHE) begin : dcache if(`MEM_DCACHE) begin : dcache
dcache dcache(.clk, .reset, .CPUBusy, dcache dcache(.clk, .reset, .CPUBusy,
.LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
.FinalWriteDataM, .ReadDataWordM, .DCacheStall, .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
.DCacheMiss, .DCacheAccess, .DCacheMiss, .DCacheAccess,
.IgnoreRequest, .CacheableM, .DCacheCommittedM, .IgnoreRequest, .CacheableM, .DCacheCommittedM,