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				https://github.com/openhwgroup/cvw
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	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
This commit is contained in:
		
						commit
						7ab747dc43
					
				@ -6,20 +6,21 @@ NAME := synth
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# defaults
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export DESIGN ?= wallypipelinedcore
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export FREQ ?= 3000
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export CONFIG ?= rv32gc
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export CONFIG ?= rv32e_FPUoff
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TITLE = shreya
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# sky130 and sky90 presently supported
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export TECH ?= tsmc28
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export TECH ?= sky90
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# MAXCORES allows parallel compilation, which is faster but less CPU-efficient
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# Avoid when doing sweeps of many optimization points in parallel
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export MAXCORES ?= 4
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export MAXCORES ?= 1
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# MAXOPT turns on flattening, boundary optimization, and retiming
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# The output netlist is hard to interpret, but significantly better PPA
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export MAXOPT ?= 1
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export MAXOPT ?= 0
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export DRIVE ?= FLOP
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time := $(shell date +%F-%H-%M)
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hash := $(shell git rev-parse --short HEAD)
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export OUTPUTDIR := newRuns/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash)
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export OUTPUTDIR := newRuns/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
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export SAIFPOWER ?= 0
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CONFIGDIR ?= ${WALLY}/pipelined/config
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@ -50,9 +51,10 @@ rv%.log: rv%
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	echo $<
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DIRS = rv64gc rv32e rv32gc rv64ic rv32ic 
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# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic
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# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig
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DIRS32 = rv32e rv32gc rv32ic 
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DIRS64 = rv64ic rv64gc
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DIRS = $(DIRS32) $(DIRS64)
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# bpred:
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# 	@$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
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# 	@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
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@ -63,9 +65,11 @@ copy:
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	@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
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	@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
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	@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
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	@$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
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	@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
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	@$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
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	@$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
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del:
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	rm -rf $(CONFIGDIR)/*_*
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@ -104,10 +108,10 @@ freqs:
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allsynth: $(CONFIGFILESTRIM)
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$(CONFIGFILESTRIM):
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	make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=1000 MAXCORES=1
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	make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=3000 MAXCORES=1
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synth:
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synth: clean
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	@echo "DC Synthesis"
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	@mkdir -p hdl/
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	@mkdir -p $(OUTPUTDIR)
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@ -129,5 +133,9 @@ clean:
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	rm -f Synopsys_stack_trace_*.txt
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	rm -f crte_*.txt
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fresh:
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	rm -rf  WORK
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	rm -f hdl/*
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@ -158,11 +158,11 @@ def areaDelay(tech, freq, width=None, config=None, special=None):
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# ending freq in 42 means fpu was turned off manually
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if __name__ == '__main__':
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    # synthsintocsv()
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    synthsintocsv()
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    synthsfromcsv('Summary.csv')
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    freqPlot('tsmc28', 'rv32', 'e')
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    freqPlot('sky90', 'rv32', 'e')
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    areaDelay('tsmc28', testFreq[1], width= 'rv64', config='gc')
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    areaDelay('tsmc28', testFreq[1], special='')
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    areaDelay('sky90', testFreq[0], width='rv64', config='gc')
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    areaDelay('sky90', testFreq[0], special='')
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    areaDelay('tsmc28', testFreq[1], special='FPUoff')
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    areaDelay('sky90', testFreq[0], special='FPUoff')
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@ -1,7 +1,11 @@
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#!/usr/bin/bash
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make clean
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mv runs runArchive/$(date +"%Y_%m_%d_%I_%M_%p")
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mv newRuns runs
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mkdir newRuns
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# mv runs runArchive/$(date +"%Y_%m_%d_%I_%M_%p")
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# mv newRuns runs
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# mkdir newRuns
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make del
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make copy 
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make configs 
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./wallySynth.py
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@ -3,6 +3,9 @@
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# james.stine@okstate.edu 27 Sep 2015
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#
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# start run clock
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set t1 [clock seconds]
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# Ignore unnecessary warnings:
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# intraassignment delays for nonblocking assignments are ignored
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suppress_message {VER-130} 
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@ -132,8 +135,13 @@ if {$tech == "sky130"} {
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}
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# Set input/output delay
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set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
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set_output_delay 0.0 -max -clock $my_clk [all_outputs]
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if {$drive == "FLOP"} {
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    set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
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    set_output_delay 0.1 -max -clock $my_clk [all_outputs]
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} else {
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    set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
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    set_output_delay 0.0 -max -clock $my_clk [all_outputs]
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}
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# Setting load constraint on output ports 
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if {$tech == "sky130"} {
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@ -375,4 +383,9 @@ redirect $filename { report_constraint }
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set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_hier.rep"]
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# redirect $filename { report_hierarchy }
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# end run clock and echo run time in minutes
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set t2 [clock seconds]
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set t [expr $t2 - $t1]
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echo [expr $t/60]
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quit 
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@ -3,31 +3,37 @@
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import subprocess
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from multiprocessing import Pool
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import time
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def runCommand(config, tech, freq):
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    command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT=0 MAXCORES=1".format(config, tech, freq)
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    subprocess.Popen(command, shell=True)
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    commands = ["make fresh", "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT=0 MAXCORES=1".format(config, tech, freq)]
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    for c in commands:
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        subprocess.Popen(c, shell=True)
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    time.sleep(60)
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testFreq = [3000, 10000]
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if __name__ == '__main__':
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    techs = ['sky90', 'tsmc28']
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    sweepCenter = [870, 3000]
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    sweepCenter = [870, 2940]
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    synthsToRun = []
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    arr = [-8, -6, -4, -2, 0, 2, 4, 6, 8]
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    for i in [0, 1]:
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    pool = Pool()
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    for i in [0]: 
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        tech = techs[i]
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        sc = sweepCenter[i]
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        f = testFreq[i]
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        for freq in [round(sc+sc*x/100) for x in arr]: # rv32e freq sweep
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            synthsToRun += [['rv32e', tech, freq]]
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        for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64i', 'rv64ic', 'rv32e']: # configs
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            synthsToRun += [[config, tech, f]]
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        for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations
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        # for freq in [round(sc+sc*x/100) for x in arr]: # rv32e freq sweep
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        #     synthsToRun += [['rv32e', tech, freq]]
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        # for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs
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        #     config = config + '_FPUoff' # while FPU under rennovation
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        #     synthsToRun += [[config, tech, f]]
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        for mod in ['noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations
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            config = 'rv64gc_' + mod
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            synthsToRun += [[config, tech, f]]
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    pool = Pool()
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    pool.starmap(runCommand, synthsToRun)
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        for x in synthsToRun:
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            pool.starmap(runCommand, [x])
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