mcause test fixes and s-mode interrupt bugfix

wally-pipelined/src/privileged/csr.sv

@@ -55,7 +55,7 @@ module csr #(parameter
   output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
   output logic [`XLEN-1:0]      MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
   output logic [`XLEN-1:0] SATP_REGW,
-  output logic [11:0]      MIP_REGW, MIE_REGW,
+  output logic [11:0]      MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
   output logic             STATUS_MIE, STATUS_SIE,
   output logic             STATUS_MXR, STATUS_SUM,
   output logic             STATUS_MPRV,
@@ -80,7 +80,6 @@ module csr #(parameter
   logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
 
   logic [11:0] CSRAdrM;
-  logic [11:0] SIP_REGW, SIE_REGW;
   //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported
   logic        IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM;
   logic IllegalCSRMWriteReadonlyM;

wally-pipelined/src/privileged/privileged.sv

@@ -96,7 +96,7 @@ module privileged (
   logic [1:0] STATUS_MPP;
   logic       STATUS_SPP, STATUS_TSR, STATUS_MPRV; // **** status mprv is unused outside of the csr module as of 4 June 2021. should it be deleted alltogether from the module, or should I leav the pin here in case someone needs it? 
   logic       STATUS_MIE, STATUS_SIE;
-  logic [11:0] MIP_REGW, MIE_REGW;
+  logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
   logic md, sd;
 
 

wally-pipelined/src/privileged/trap.sv

@@ -35,7 +35,7 @@ module trap (
   input  logic             mretM, sretM, uretM,
   input  logic [1:0]       PrivilegeModeW, NextPrivilegeModeM,
   input  logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
-  input  logic [11:0]      MIP_REGW, MIE_REGW,
+  input  logic [11:0]      MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
   input  logic             STATUS_MIE, STATUS_SIE,
   input  logic [`XLEN-1:0] PCM,
   input  logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, 
@@ -58,7 +58,7 @@ module trap (
   // Determine pending enabled interrupts
   assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
   assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
-  assign PendingIntsM = (MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888) | ({12{SIntGlobalEnM}} & 12'h222);
+  assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
   assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM;
   // interrupt if any sources are pending
   // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)

wally-pipelined/src/uncore/clint.sv

@@ -32,10 +32,10 @@ module clint (
   input  logic [15:0]      HADDR,
   input  logic             HWRITE,
   input  logic [`XLEN-1:0] HWDATA,
-  output logic [`XLEN-1:0] HREADCLINT,
-  output logic 		   HRESPCLINT, HREADYCLINT,
   input  logic             HREADY,
   input  logic [1:0]       HTRANS,
+  output logic [`XLEN-1:0] HREADCLINT,
+  output logic             HRESPCLINT, HREADYCLINT,
   output logic             TimerIntM, SwIntM);
 
   logic [63:0] MTIMECMP, MTIME;

wally-pipelined/testgen/privileged/testgen-CAUSE.py

@@ -53,7 +53,7 @@ def writeVectors(storecmd, returningInstruction):
         csrrs x0, {fromMode}status, x1
 
         la x18, {clintAddr}
-        lw x11, 0(x18)
+        {loadcmd} x11, 0(x18)
         li x1, 0x3fffffffffffffff
         {storecmd} x1, 0(x18)
 
@@ -310,9 +310,11 @@ for xlen in xlens:
   formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
   if (xlen == 32):
     storecmd = "sw"
+    loadcmd = "lw"
     wordsize = 4
   else:
     storecmd = "sd"
+    loadcmd = "ld"
     wordsize = 8
 
   # testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]