From 7a56a66927339c960225858e2541d5bc99ae625e Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Fri, 3 Nov 2023 06:37:05 -0700
Subject: [PATCH] set default USE_SRAM=0 in memories; cleaned up synthesis
 script grep for cvw_t

---
 src/generic/mem/ram1p1rwbe.sv  | 2 +-
 src/generic/mem/ram1p1rwe.sv   | 2 +-
 src/generic/mem/ram2p1r1wbe.sv | 2 +-
 src/generic/mem/rom1p1r.sv     | 4 +---
 synthDC/scripts/synth.tcl      | 8 +++-----
 5 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index bf246bfe6..4af3c255c 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -32,7 +32,7 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-module ram1p1rwbe import cvw::*; #(parameter USE_SRAM, DEPTH=64, WIDTH=44, PRELOAD_ENABLED=0) (
+module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRELOAD_ENABLED=0) (
   input logic                     clk,
   input logic                     ce,
   input logic [$clog2(DEPTH)-1:0] addr,
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
index 645141b01..e3746c181 100644
--- a/src/generic/mem/ram1p1rwe.sv
+++ b/src/generic/mem/ram1p1rwe.sv
@@ -30,7 +30,7 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-module ram1p1rwe import cvw::* ; #(parameter USE_SRAM, DEPTH=64, WIDTH=44) (
+module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
   input logic                     clk,
   input logic                     ce,
   input logic [$clog2(DEPTH)-1:0] addr,
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 15155fd0f..1ac11a633 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -31,7 +31,7 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM, DEPTH=1024, WIDTH=68) (
+module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) (
   input  logic                     clk,
   input  logic                     ce1, ce2,
   input  logic [$clog2(DEPTH)-1:0] ra1,
diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index 60d041423..93f8c82df 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -25,9 +25,7 @@
 
 // This model actually works correctly with vivado.
 
-module rom1p1r #(parameter ADDR_WIDTH = 8,
-     parameter DATA_WIDTH = 32, 
-     parameter PRELOAD_ENABLED = 0)
+module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
   (input  logic                  clk,
    input  logic                  ce,
    input  logic [ADDR_WIDTH-1:0] addr,
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 91ec44e2a..9be076edf 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -32,17 +32,15 @@ eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
-# Check if a wrapper is needed (when cvw_t parameters are used)
+# Check if a wrapper is needed and create it (to pass parameters when cvw_t parameters are used)
 set wrapper 0
-if {[eval exec grep "cvw_t" {$outputDir/hdl/$::env(DESIGN).sv}] ne ""} {
+if {[catch {eval exec grep "cvw_t" $outputDir/hdl/$::env(DESIGN).sv}] == 0} {
+    echo "Creating wrapper"
     set wrapper 1
     # make the wrapper
 	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN) $outputDir/hdl
 }
 
-# Only for FMA class project; comment out when done
-# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
-
 # Enables name mapping
 if { $saifpower == 1 } {
     saif_map -start