diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index d3cd98341..919b882fe 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -131,6 +131,7 @@ module ahblite (
             else                   NextBusState = IDLE;  // if (InstrReadF still high)
       INSTRREADC: if (~HREADY)     NextBusState = INSTRREADC; // "C" for "competing", meaning please don't mess up the memread in the W stage.
             else                   NextBusState = IDLE;
+      default:                     NextBusState = IDLE;
     endcase
 
   // stall signals