From 7a3c78a80d4916c74d293d64ffd9e5717494eecb Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Mon, 12 Jun 2023 13:08:54 -0700
Subject: [PATCH] Update atomic.sv

Program clean up
---
 src/lsu/atomic.sv | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv
index 5c2035699..117a42c2b 100644
--- a/src/lsu/atomic.sv
+++ b/src/lsu/atomic.sv
@@ -28,24 +28,24 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module atomic import cvw::*;  #(parameter cvw_t P) (
-  input logic                clk,
-  input logic                reset, 
-  input logic                StallW,
+  input logic                 clk,
+  input logic                 reset, 
+  input logic                 StallW,
   input logic [P.XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
   input logic [P.XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
   input logic [P.PA_BITS-1:0] PAdrM,          // Physical memory address
-  input logic [6:0]          LSUFunct7M,     // AMO alu operation gated by HPTW
-  input logic [2:0]          LSUFunct3M,     // IEU or HPTW memory operation size
-  input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
-  input logic [1:0]          PreLSURWM,      // IEU or HPTW Read/Write signal
-  input logic                IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
+  input logic [6:0]           LSUFunct7M,     // AMO alu operation gated by HPTW
+  input logic [2:0]           LSUFunct3M,     // IEU or HPTW memory operation size
+  input logic [1:0]           LSUAtomicM,     // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
+  input logic [1:0]           PreLSURWM,      // IEU or HPTW Read/Write signal
+  input logic                 IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
   output logic [P.XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
-  output logic               SquashSCW,      // Store conditional failed disable write to GPR
-  output logic [1:0]         LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
+  output logic                SquashSCW,      // Store conditional failed disable write to GPR
+  output logic [1:0]          LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
 );
 
   logic [P.XLEN-1:0]          AMOResultM;
-  logic                      MemReadM;
+  logic                       MemReadM;
 
   amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);