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Add wrapper passing automatically for individual designs vs. Wally

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This commit is contained in:
James E. Stine 2023-11-15 08:45:25 -06:00
parent 9dce08a743
commit 79d6fe8c93
2 changed files with 36 additions and 8 deletions
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40
synthDC/Makefile
View File

@ -1,7 +1,28 @@
# #####################
# Makefile for synthesis # Makefile
# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 #
# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 # Written: ssanghai@hmc.edu, mmasserfrye@hmc.edu, james.stine@okstate.edu 15 November 2023
#
# Purpose: Makefile to be used for synthesis using DC
#
# A component of the Wally configurable RISC-V project.
#
# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
#
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
#
# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
# except in compliance with the License, or, at your option, the Apache License version 2.0. You
# may obtain a copy of the License at
#
# https:#solderpad.org/licenses/SHL-2.1/
#
# Unless required by applicable law or agreed to in writing, any work distributed under the
# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
# either express or implied. See the License for the specific language governing permissions
# and limitations under the License.
################################################
NAME := synth NAME := synth
# defaults # defaults
export DESIGN ?= wallypipelinedcore export DESIGN ?= wallypipelinedcore
@ -21,11 +42,18 @@ export MAXOPT ?= 0
export DRIVE ?= FLOP export DRIVE ?= FLOP
export USESRAM ?= 0 export USESRAM ?= 0
export WIDTH ?= 32 export WIDTH ?= 32
export WRAPPER ?= 1
export SAIFPOWER ?= 0
time := $(shell date +%F-%H-%M) time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD) hash := $(shell git rev-parse --short HEAD)
export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) # This is done to create different naming conventions to help the PPA python
export SAIFPOWER ?= 0 # TODO: cleanup later to utilize better parsing/lexing
ifeq ($(WRAPPER), 0)
export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
else
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
endif
OLDCONFIGDIR ?= ${WALLY}/config OLDCONFIGDIR ?= ${WALLY}/config
export CONFIGDIR ?= $(OUTPUTDIR)/config export CONFIGDIR ?= $(OUTPUTDIR)/config

4
synthDC/ppa/ppaSynth.py
View File

@ -11,7 +11,7 @@ from multiprocessing import Pool
from ppaAnalyze import synthsfromcsv from ppaAnalyze import synthsfromcsv
def runCommand(module, width, tech, freq): def runCommand(module, width, tech, freq):
command = "make synth DESIGN={} WIDTH={} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1".format(module, width, tech, freq) command = "make synth DESIGN={} WIDTH={} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1 WRAPPER=0".format(module, width, tech, freq)
subprocess.call(command, shell=True) subprocess.call(command, shell=True)
def deleteRedundant(synthsToRun): def deleteRedundant(synthsToRun):
@ -95,4 +95,4 @@ if __name__ == '__main__':
pool.starmap(runCommand, synthsToRun) pool.starmap(runCommand, synthsToRun)
pool.close() pool.close()
pool.join() pool.join()