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Progress toward run_vcs

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This commit is contained in:
David Harris 2024-04-03 14:05:07 -07:00
parent 811e760d7e
commit 79cccfca82
2 changed files with 6 additions and 2 deletions
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5
site-setup.sh
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@ -12,11 +12,12 @@
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin
# Tools
# Questa and Synopsys
export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH
export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
# GCC
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib

3
src/uncore/clint_apb.sv
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@ -150,6 +150,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
endmodule
/*
module timeregsync import cvw::*; #(parameter cvw_t P) (
input logic clk, resetn,
input logic we0, we1,
@ -169,6 +170,7 @@ module timeregsync import cvw::*; #(parameter cvw_t P) (
else q <= q + 1;
endmodule
module timereg import cvw::*; #(parameter cvw_t P) (
input logic PCLK, PRESETn, TIMECLK,
input logic we0, we1,
@ -245,3 +247,4 @@ module graytobinary #(parameter N) (
assign b[i] = g[i] ^ b[i+1];
end
endmodule
*/