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Fix erroneous implicit sckcs and cssck phase delays

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naichewa 2024-11-07 10:47:51 -08:00
parent 7637f3e33b
commit 7964358651
1 changed files with 5 additions and 23 deletions
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24
src/uncore/spi_controller.sv
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@ -75,7 +75,6 @@ module spi_controller (
logic ShiftEdgePulse; logic ShiftEdgePulse;
logic SampleEdgePulse; logic SampleEdgePulse;
logic EndOfFramePulse; logic EndOfFramePulse;
logic PhaseOneOffset;
// Frame stuff // Frame stuff
logic [3:0] BitNum; logic [3:0] BitNum;
@ -212,34 +211,17 @@ module spi_controller (
always_ff @(posedge ~PCLK) begin always_ff @(posedge ~PCLK) begin
if (~PRESETn | TransmitStart) begin if (~PRESETn | TransmitStart) begin
ShiftEdge <= 0; ShiftEdge <= 0;
PhaseOneOffset <= 0;
SampleEdge <= 0; SampleEdge <= 0;
EndOfFrame <= 0; EndOfFrame <= 0;
end else begin end else if (^SckMode) begin
PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrame;
case(SckMode)
2'b00: begin
ShiftEdge <= SPICLK & ShiftEdgePulse;
SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse;
end
2'b01: begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse & PhaseOneOffset;
SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse;
end
2'b10: begin
ShiftEdge <= ~SPICLK & ShiftEdgePulse; ShiftEdge <= ~SPICLK & ShiftEdgePulse;
SampleEdge <= SPICLK & SampleEdgePulse; SampleEdge <= SPICLK & SampleEdgePulse;
EndOfFrame <= ~SPICLK & EndOfFramePulse; EndOfFrame <= ~SPICLK & EndOfFramePulse;
end end else begin
2'b11: begin ShiftEdge <= SPICLK & ShiftEdgePulse;
ShiftEdge <= SPICLK & ShiftEdgePulse & PhaseOneOffset;
SampleEdge <= ~SPICLK & SampleEdgePulse; SampleEdge <= ~SPICLK & SampleEdgePulse;
EndOfFrame <= SPICLK & EndOfFramePulse; EndOfFrame <= SPICLK & EndOfFramePulse;
end end
endcase
end
end end
// Logic for continuing to transmit through Delay states after end of frame // Logic for continuing to transmit through Delay states after end of frame