From 7960f26e846c2a20194d0ffcd919967cbcad97d6 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 17:44:37 -0500 Subject: [PATCH] Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. --- src/rvvi/rvvisynth.sv | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index f42e9c1a8..0c0214b3f 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -88,6 +88,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, {FPRWen, GPRWen} == 2'b10 ? {XLENZeros, 5'b0, FPRValue, FPRAddr} : '0; + /* verilator lint_off UNOPTFLAT */ + // For some reason verilator complains about CSRWenFilterMatrix being in a circular loop when it is not. + // the CSRs are complex // 1. we need to get the CSR values // 2. we check if the CSR value changes by registering the value then XORing with the old value. @@ -121,9 +124,12 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, always_comb begin CSRCountShort = '0; for(index2 = 0; index2 < MAX_CSRS; index2++) begin + /* verilator lint_off WIDTHEXPAND */ CSRCountShort += EnabledCSRs[index2]; + /* verilator lint_on WIDTHEXPAND */ end end + /* verilator lint_on UNOPTFLAT */ assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort}; assign rvvi = {CSRs, Registers, Required};