Merge pull request #748 from ross144/main

FPGA fixex required after regress updates and added compatiblity for cygwin.
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David Harris 2024-04-22 08:53:50 -07:00 committed by GitHub
commit 7944459fc9
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2 changed files with 10 additions and 18 deletions

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@ -57,7 +57,8 @@ PreProcessFiles:
# modify config *** RT: eventually setup for variably defined sized memory # modify config *** RT: eventually setup for variably defined sized memory
#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh #sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA # This line allows the Bootloader to be loaded in a Block RAM on the FPGA
sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
$(dst)/%.log: %.tcl $(dst)/%.log: %.tcl
mkdir -p IP mkdir -p IP

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@ -4,7 +4,7 @@
## ##
## Written: Rose Thompson ross1728@gmail.com ## Written: Rose Thompson ross1728@gmail.com
## Created: 20 January 2023 ## Created: 20 January 2023
## Modified: 16 April 2024 ## Modified: 22 April 2024
## ##
## A component of the CORE-V-WALLY configurable RISC-V project. ## A component of the CORE-V-WALLY configurable RISC-V project.
## https://github.com/openhwgroup/cvw ## https://github.com/openhwgroup/cvw
@ -29,21 +29,12 @@
# Then it processes them to add mark_debug on signals needed by the FPGA's ILA. # Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
copiedDir="../src/CopiedFiles_do_not_add_to_repo" copiedDir="../src/CopiedFiles_do_not_add_to_repo"
while read line; do while read line; do
# older versions of bash are incompatible with readarray -d :( readarray -d ":" -t StrArray <<< "$line"
#readarray -d ":" -t StrArray <<< "$line" file="${copiedDir}/${StrArray[0]}"
#file="${copiedDir}/${StrArray[0]}" signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
#signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
fileName=`echo $line | cut -d ":" -f 1`
file=${copiedDir}/$fileName
signal=`echo $line | cut -d ":" -f 2`
echo $file
echo $signal
readarray -d " " -t SigArray <<< $signal readarray -d " " -t SigArray <<< $signal
sigType=`echo $signal | cut -d " " -f 1` sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
sigType=`echo $sigType | awk '{$1=$1};1'` sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1' | tr -d "\015"`
sigName=`echo $signal | cut -d " " -f 2` filepath=`find $copiedDir -wholename $file`
sigName=`echo $sigName | awk '{$1=$1};1'` sed -i "s/\(.*${sigType}.*${sigName}.*\)/(\* mark_debug = \"true\" \*)\1/g" $filepath
#sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
#sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g"
done < ../constraints/marked_debug.txt done < ../constraints/marked_debug.txt