mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
793670d878
@ -4,10 +4,12 @@ imageDir=$RISCV/buildroot/output/images
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outDir=$RISCV/linux-testvectors
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outDir=$RISCV/linux-testvectors
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recordFile="$outDir/all.qemu"
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recordFile="$outDir/all.qemu"
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traceFile="$outDir/all.txt"
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traceFile="$outDir/all.txt"
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interruptsFile="$outDir/interrupts.txt"
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read -p "Warning: running this script will overwrite the contents of:
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read -p "Warning: running this script will overwrite the contents of:
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* $recordFile
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* $recordFile
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* $traceFile
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* $traceFile
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* $interruptsFile
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Would you like to proceed? (y/n) " -n 1 -r
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Would you like to proceed? (y/n) " -n 1 -r
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echo
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echo
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if [[ $REPLY =~ ^[Yy]$ ]]
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if [[ $REPLY =~ ^[Yy]$ ]]
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@ -17,8 +19,10 @@ then
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sudo chown cad $outDir
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sudo chown cad $outDir
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sudo touch $recordFile
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sudo touch $recordFile
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sudo touch $traceFile
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sudo touch $traceFile
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sudo touch $interruptsFile
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sudo chmod a+rw $recordFile
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sudo chmod a+rw $recordFile
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sudo chmod a+rw $traceFile
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sudo chmod a+rw $traceFile
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sudo chmod a+rw $interruptsFile
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# Compile Devicetree from Source
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# Compile Devicetree from Source
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dtc -I dts -O dtb ../devicetree/virt-trimmed.dts > ../devicetree/virt-trimmed.dtb
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dtc -I dts -O dtb ../devicetree/virt-trimmed.dts > ../devicetree/virt-trimmed.dtb
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@ -29,15 +33,17 @@ then
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-nographic -serial /dev/null \
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-nographic -serial /dev/null \
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-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
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-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
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-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \
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-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \
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-d nochain,cpu,in_asm \
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-d nochain,cpu,in_asm,int \
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-gdb tcp::$tcpPort -S \
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-gdb tcp::$tcpPort -S \
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2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py | ./remove_dup.awk > $traceFile) \
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2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) \
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& riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\""
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& riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\""
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# Cleanup
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# Cleanup
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sudo chown cad $recordFile
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sudo chown cad $recordFile
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sudo chown cad $traceFile
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sudo chown cad $traceFile
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sudo chown cad $interruptsFile
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sudo chmod o-w $recordFile
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sudo chmod o-w $recordFile
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sudo chmod o-w $traceFile
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sudo chmod o-w $traceFile
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sudo chmod o-w $interruptsFile
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fi
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fi
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@ -130,6 +130,13 @@ def PrintInstr(instr, fp):
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fp.write(' CSR {}'.format(CSRStr))
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fp.write(' CSR {}'.format(CSRStr))
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fp.write('\n')
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fp.write('\n')
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# =========
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# Main Code
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# =========
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# Parse argument for interrupt file
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if len(sys.argv) != 2:
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sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n <interrupt filename>>')
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interruptFname = sys.argv[1]
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# reg number
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# reg number
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RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45}
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RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45}
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# initial state
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# initial state
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@ -144,14 +151,24 @@ numInstrs = 0
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#instructions = []
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#instructions = []
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MemAdr = 0
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MemAdr = 0
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lines = []
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lines = []
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interrupts=open('interrupts.txt','w')
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interrupts=open(interruptFname,'w')
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interrupts.close()
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interrupts.close()
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for line in fileinput.input('-'):
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for line in fileinput.input('-'):
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if line.startswith('riscv_cpu_do_interrupt'):
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if line.startswith('riscv_cpu_do_interrupt'):
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with open('interrupts.txt','a') as interrupts:
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with open(interruptFname,'a') as interrupts:
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interrupts.write(str(numInstrs)+': '+line.strip('riscv_cpu_do_interrupt'))
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# Write line
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break
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# Example line: hart:0, async:0, cause:0000000000000002, epc:0x0000000080008548, tval:0x0000000000000000, desc=illegal_instruction
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interrupts.write(line)
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# Write instruction count
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interrupts.write(str(numInstrs)+'\n')
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# Convert line to rows of info for easier Verilog parsing
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vals=line.strip('riscv_cpu_do_interrupt: ').strip('\n').split(',')
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vals=[val.split(':')[-1].strip(' ') for val in vals]
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vals=[val.split('=')[-1].strip(' ') for val in vals]
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for val in vals:
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interrupts.write(val+'\n')
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continue
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lines.insert(lineNum, line)
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lines.insert(lineNum, line)
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if InstrStartDelim in line:
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if InstrStartDelim in line:
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lineNum = 0
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lineNum = 0
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@ -204,8 +221,8 @@ for line in fileinput.input('-'):
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#instructions.append(MoveInstrToRegWriteLst)
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#instructions.append(MoveInstrToRegWriteLst)
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PrintInstr(MoveInstrToRegWriteLst, sys.stdout)
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PrintInstr(MoveInstrToRegWriteLst, sys.stdout)
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numInstrs +=1
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numInstrs +=1
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if (numInstrs % 1e4 == 0):
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if (numInstrs % 1e5 == 0):
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sys.stderr.write('Trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n')
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sys.stderr.write('GDB trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n')
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sys.stderr.flush()
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sys.stderr.flush()
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lineNum += 1
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lineNum += 1
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@ -115,7 +115,6 @@ for l in fileinput.input():
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if l.startswith('riscv_cpu_do_interrupt'):
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if l.startswith('riscv_cpu_do_interrupt'):
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sys.stderr.write(l)
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sys.stderr.write(l)
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interrupt_line = l.strip('\n')
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interrupt_line = l.strip('\n')
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continue
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elif l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'):
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elif l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'):
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break
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break
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elif l.startswith('IN:'):
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elif l.startswith('IN:'):
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16
pipelined/src/cache/cachefsm.sv
vendored
16
pipelined/src/cache/cachefsm.sv
vendored
@ -105,14 +105,14 @@ module cachefsm
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(* mark_debug = "true" *) statetype CurrState, NextState;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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assign DoFlush = FlushCache & ~IgnoreRequest;
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assign DoFlush = FlushCache & ~IgnoreRequest; // *** have to fix ignorerequest timing path
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assign DoAMO = Atomic[1] & (&RW) & ~IgnoreRequest;
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assign DoAMO = Atomic[1] & (&RW) & ~IgnoreRequest; // ***
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assign DoAMOHit = DoAMO & CacheHit;
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assign DoAMOHit = DoAMO & CacheHit;
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assign DoAMOMiss = DoAMOHit & ~CacheHit;
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assign DoAMOMiss = DoAMO & ~CacheHit;
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assign DoRead = RW[1] & ~IgnoreRequest;
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assign DoRead = RW[1] & ~IgnoreRequest; // ***
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assign DoReadHit = DoRead & CacheHit;
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assign DoReadHit = DoRead & CacheHit;
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assign DoReadMiss = DoRead & ~CacheHit;
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assign DoReadMiss = DoRead & ~CacheHit;
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assign DoWrite = RW[0] & ~IgnoreRequest;
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assign DoWrite = RW[0] & ~IgnoreRequest; // ***
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assign DoWriteHit = DoWrite & CacheHit;
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assign DoWriteHit = DoWrite & CacheHit;
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assign DoWriteMiss = DoWrite & ~CacheHit;
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assign DoWriteMiss = DoWrite & ~CacheHit;
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@ -225,15 +225,15 @@ module cachefsm
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(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
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(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
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// **** can this be simplified?
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// **** can this be simplified?
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assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequest) |
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assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequest) | // *** ignorerequest comes from TrapM. Have to fix. why is ignorerequest here anyway?
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(CurrState == STATE_READY & DoAMOHit) |
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(CurrState == STATE_READY & DoAMOHit) | //<opHit> also depends on ignorerequest
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(CurrState == STATE_READY & DoReadHit & (CPUBusy & `REPLAY)) |
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(CurrState == STATE_READY & DoReadHit & (CPUBusy & `REPLAY)) |
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(CurrState == STATE_READY & DoWriteHit) |
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(CurrState == STATE_READY & DoWriteHit) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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(CurrState == STATE_MISS_FETCH_DONE) |
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(CurrState == STATE_MISS_FETCH_DONE) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_MISS_READ_WORD) |
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(CurrState == STATE_MISS_READ_WORD) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | (CPUBusy & `REPLAY))) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | (CPUBusy & `REPLAY))) | // ***
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(CurrState == STATE_MISS_WRITE_WORD) |
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(CurrState == STATE_MISS_WRITE_WORD) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_MISS_EVICT_DIRTY) |
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(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
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(CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |
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11
pipelined/src/cache/cacheway.sv
vendored
11
pipelined/src/cache/cacheway.sv
vendored
@ -121,13 +121,12 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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always_ff @(posedge clk) begin // Valid bit array,
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always_ff @(posedge clk) begin // Valid bit array,
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if (reset | InvalidateAll) ValidBits <= #1 '0;
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if (reset | InvalidateAll) ValidBits <= #1 '0;
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else if (SetValidD) ValidBits[RAdrD] <= #1 1'b1;
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else if (SetValid) ValidBits[RAdr] <= #1 1'b1;
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else if (ClearValidD) ValidBits[RAdrD] <= #1 1'b0;
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else if (ClearValid) ValidBits[RAdr] <= #1 1'b0;
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end
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end
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// *** consider revisiting whether these delays are the best option?
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// *** consider revisiting whether these delays are the best option?
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flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
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flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
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flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid},
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//flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid}, {SetValidD, ClearValidD});
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{SetValidD, ClearValidD});
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assign Valid = ValidBits[RAdrD];
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assign Valid = ValidBits[RAdrD];
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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@ -138,8 +137,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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if (DIRTY_BITS) begin:dirty
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if (DIRTY_BITS) begin:dirty
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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else if (SetDirtyD) DirtyBits[RAdrD] <= #1 1'b1;
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else if (SetDirty) DirtyBits[RAdr] <= #1 1'b1;
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else if (ClearDirtyD) DirtyBits[RAdrD] <= #1 1'b0;
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else if (ClearDirty) DirtyBits[RAdr] <= #1 1'b0;
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end
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end
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flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
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flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
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assign Dirty = DirtyBits[RAdrD];
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assign Dirty = DirtyBits[RAdrD];
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|
17
pipelined/src/cache/sram1rw.sv
vendored
17
pipelined/src/cache/sram1rw.sv
vendored
@ -41,22 +41,25 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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output logic [WIDTH-1:0] ReadData);
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output logic [WIDTH-1:0] ReadData);
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logic [WIDTH-1:0] StoredData[DEPTH-1:0];
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logic [WIDTH-1:0] StoredData[DEPTH-1:0];
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logic [$clog2(DEPTH)-1:0] AddrD;
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logic [$clog2(DEPTH)-1:0] AdrD;
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logic [WIDTH-1:0] WriteDataD;
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logic [WIDTH-1:0] WriteDataD;
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logic WriteEnableD;
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logic WriteEnableD;
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//*** model as single port
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//*** model as single port
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// *** merge with simpleram
|
// *** merge with simpleram
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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AddrD <= Adr;
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AdrD <= Adr;
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WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere
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//WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere
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WriteEnableD <= WriteEnable;
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//WriteEnableD <= WriteEnable;
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if (WriteEnableD) begin
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//if (WriteEnableD) begin
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StoredData[AddrD] <= #1 WriteDataD;
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//StoredData[AddrD] <= #1 WriteDataD;
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//end
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if (WriteEnable) begin
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StoredData[Adr] <= #1 WriteData;
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end
|
end
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end
|
end
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|
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assign ReadData = StoredData[AddrD];
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assign ReadData = StoredData[AdrD];
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/*
|
/*
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always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
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ReadData <= RAM[Adr];
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ReadData <= RAM[Adr];
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|
@ -112,7 +112,6 @@ module interlockfsm
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assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
|
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
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(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
|
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
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assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | TrapM)) |
|
assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | TrapM)) |
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((InterlockCurrState == STATE_T0_REPLAY)
|
((InterlockCurrState == STATE_T0_REPLAY) & (TrapM));
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& (TrapM));
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
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