diff --git a/wally-pipelined/testgen/privileged/testgen-IE.py b/wally-pipelined/testgen/privileged/testgen-IE.py
index 5195006ee..67bdf67e5 100644
--- a/wally-pipelined/testgen/privileged/testgen-IE.py
+++ b/wally-pipelined/testgen/privileged/testgen-IE.py
@@ -2,6 +2,175 @@
 ##################################
 # testgen-IE.py
 #
+# ushakya@hmc.edu 31 March 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def writeTrapHandlers(storecmd):
+  global testnum
+  reg1 = 30
+  reg2 = 29
+  reg3 = 28
+  lines = "\n# Trap Handler: Timer Interupt\n"
+  lines += "_timer_trap_handler:\n"
+  lines += "li x" + str(reg1) + ", MASK_XLEN(0x2A)\n"
+  lines += str(storecmd) + " x" + str(reg1) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += "la x" + str(reg2) + ", 0x2004000\n"
+  lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
+  lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
+  lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+  lines += "mret\n"
+
+  f.write(lines)
+
+def writeVector(a, xlen, storecmd):
+  global testnum
+
+  [reg1, reg2, reg3] = [1, 2, 3]
+  [reg5, reg8] = [5, 8]
+  [reg9, reg10, reg11, reg12] = [9, 10, 11, 12]
+
+  lines = "\n# Testcase 0: Timer Interupt\n"
+
+  # Page 6 of unpriviledged spec
+  # For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
+  
+  # mcause code
+  b = 1 << (xlen-1)
+  b = b + 0x7
+  expected = b
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+
+  if (testnum == 0): expected = 0
+
+  # set interupt enable bit in mstatus
+  lines += "li x" + str(reg3) + ", MASK_XLEN(0x8)\n"
+  lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
+
+  # set machine timer interupt enable bit in mie
+  lines += "li x" + str(reg9) + ", MASK_XLEN(0x80)\n"
+  lines += "csrrs x0, mie, x" + str(reg3) + "\n"
+
+  # Save and set trap handler address for machine mode timer interrupt
+  lines += "la x" + str(reg5) + ", _timer_trap_handler\n"
+  
+  # save orignal mtvec address
+  lines += "csrrw x" + str(reg12) + ", mtvec, x" + str(reg5) + "\n"
+  
+  # cause timer interupt
+  #if (testnum == 0):
+  lines += "li x" + str(reg8) + ", MASK_XLEN(0)\n"
+  lines += str(storecmd) + " x" + str(reg8) + ", " + str(wordsize*testnum)+ "(x6)\n"
+  
+  lines += "la x" + str(reg8) + ", 0x2004000\n"
+
+  lines += "li x" + str(reg3) + ", MASK_XLEN(0)\n"
+
+  # save old value of mtimecmp and then set mtimecmp to zero
+  lines += "lw x" + str(reg11) + ", 0(x" + str(reg8) + ")\n"
+  lines += str(storecmd) + " x" + str(reg3) + ",  0(x" + str(reg8) + ")\n"
+  #lines += "wfi\n" # wait for interupt to be taken
+  lines += "nop\nnop\n"
+
+  lines += "csrrw " + " x" + str(reg2) + ", mcause, x" + str(reg1) + "\n"
+  
+  # reset mtvec
+  lines += "csrrw x0, mtvec, x" + str(reg12) + "\n"
+
+  lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg2) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["timer"]
+author = "ushakya@hmc.edu"
+xlens = [64, 32]
+numrand = 100;
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-IE" 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(xlen)
+      writeVector(a, xlen, storecmd)
+
+    writeTrapHandlers(storecmd)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+"""
+#!/usr/bin/python3
+##################################
+# testgen-IE.py
+#
 # ushakya@hmc.edu 24 Mar 2021
 #
 # Generate tests for mie CSR for RISC-V Design Validation.
@@ -34,23 +203,23 @@ def writeVectors(storecmd):
   reg1, reg2, reg3 = randRegs()
 
   # Set interupt enable bit in mstatus
-  lines = """
+  lines = ""
   li x2, 0x8
   csrrs x3, mstatus, x2
-  """
+  ""
 
   f.write(lines)
 
  # Save and set trap handler address for machine mode timer interrupt
-  lines += """
+  lines += ""
   la x1, _timer_trap_handler
   csrrw x31, mtvec, x1
-  """
+  ""
   f.write(lines)
 
   # Machine Mode Timer Interrupt (when interupt is enabled)
   # is this not working because mtimecmp isn't implemented????
-  write(f"""
+  write(f""
     li x2, 0x0
 
     li x4, 0x80
@@ -64,7 +233,7 @@ def writeVectors(storecmd):
     lw x5, 0(x2)
     sd x3, 0(x2)
     wfi
-  """, storecmd, True, 4, "m")
+  "", storecmd, True, 4, "m")
 
   # Supervisor Timer Interrupt
   # user timer interupt
@@ -75,14 +244,14 @@ def writeVectors(storecmd):
   # Supervisor external interrupt True, 9
 
   # Save and set trap handler address for machine mode software interrupt
- # lines = """
+ # lines = ""
  # la x1, _interupt_trap_handler
  # csrrw x31, mtvec, x1
- # """
+ # ""
  # f.write(lines)
  
   # Machine Mode software interupt (write to the CLINT)
-  #write(f"""
+  #write(f""
   #  li x6, 0x0
 #
 #    li x4, 0x8
@@ -92,23 +261,23 @@ def writeVectors(storecmd):
 #    lw x4, clint
 #    or x3, x4, x3
 #    {storecmd} x3, clint
-#  """, storecmd, True, 3, "m")
+#  "", storecmd, True, 3, "m")
 
   # supervisor mode software interupt
   # user mode software interupt
   
   # timer interupt trap handler
-  lines = f"""
+  lines = f""
   _timer_trap_handler:
   li x2, 0x2A
   {storecmd} x2, {str(wordsize*testnum)}(x6)
   la x3, 0x2004000
   {storecmd} x2, 0(x3)
   mret
-  """
+  ""
 
   # software interupt trap handler
-  #lines += f"""
+  #lines += f""
   #_interupt_trap_handler:
   #li x6, 0x2A
   #li x3, 0x0
@@ -116,8 +285,8 @@ def writeVectors(storecmd):
   #xor x3, x4, x3
   #{storecmd} x3, 0(clint)
  #mret
-  #"""
-  lines += storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  #""
+  lines += storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)"
 
   f.write(lines)
 
@@ -129,14 +298,14 @@ def write(lines, storecmd, interrupt, code, mode = "m"):
   #(0 if not interrupt else (2**31 if xlen == 32 else 2**63)) + code
   # go back and fix expected
 
-  lines = f"""
+  lines = f""
     # Testcase {testnum}
     li x31, 0
     {lines}
 
     {storecmd} x31, {str(wordsize*testnum)}(x6)
     # RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)})
-  """
+  ""
 
   #if mode == "s":
     # go to supervisor mode
@@ -146,9 +315,9 @@ def write(lines, storecmd, interrupt, code, mode = "m"):
   f.write(lines)
 
   if (xlen == 32):
-    line = formatrefstr.format(expected)+"\n"
+    line = formatrefstr.format(expected)+""
   else:
-    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+    line = formatrefstr.format(expected % 2**32)+"" + formatrefstr.format(expected >> 32) + ""
   r.write(line)
   testnum = testnum+1
 
@@ -187,7 +356,7 @@ for xlen in xlens:
     storecmd = "sd"
     wordsize = 8
 
-  imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/"""
+  imperaspath = f"../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/""
   basename = "WALLY-IE"
   fname = imperaspath + "src/" + basename + ".S"
   refname = imperaspath + "references/" + basename + ".reference_output"
@@ -196,9 +365,9 @@ for xlen in xlens:
   # print custom header part
   f = open(fname, "w")
   r = open(refname, "w")
-  line = "///////////////////////////////////////////\n"
+  line = "///////////////////////////////////////////"
   f.write(line)
-  lines="// "+fname+ "\n// " + author + "\n"
+  lines="// "+fname+ "// " + author + ""
   f.write(lines)
   line ="// Created " + str(datetime.now()) 
   f.write(line)
@@ -218,8 +387,9 @@ for xlen in xlens:
     f.write(line)
 
   # Finish
-  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
-  lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1"
+  lines = lines + "RV_COMPLIANCE_DATA_END" 
    f.write(lines)
   f.close()
   r.close()
+  """