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Merge pull request #1051 from naichewa/main

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Fixed spi tests
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David Harris 2024-11-01 13:41:01 -07:00 committed by GitHub
commit 78666e51dd
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2 changed files with 2 additions and 2 deletions
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2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S
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@ -553,7 +553,7 @@ test_cases:
# Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables # Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
SETUP_PLIC SETUP_PLIC
.4byte fmt, 0x00080000, write32_test # reset format register
.4byte delay1, 0x0000001, write32_test # reset delay1 register .4byte delay1, 0x0000001, write32_test # reset delay1 register
.4byte cs_mode, 0x00000000, write32_test # reset cs_mode .4byte cs_mode, 0x00000000, write32_test # reset cs_mode
.4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off) .4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S
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@ -564,7 +564,7 @@ test_cases:
# Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables # Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
SETUP_PLIC SETUP_PLIC
.8byte fmt, 0x00080000, write32_test # reset format register
.8byte delay1, 0x0000001, write32_test # reset delay1 register .8byte delay1, 0x0000001, write32_test # reset delay1 register
.8byte cs_mode, 0x00000000, write32_test # reset cs_mode .8byte cs_mode, 0x00000000, write32_test # reset cs_mode
.8byte sck_div, 0x00000100, write32_test # lower SPI clock rate so reads are done at correct time when ICACHE not supported .8byte sck_div, 0x00000100, write32_test # lower SPI clock rate so reads are done at correct time when ICACHE not supported