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https://github.com/openhwgroup/cvw
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Renamed special case
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@ -65,6 +65,8 @@ module fdivsqrtfsm(
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logic WZero;
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logic WZero;
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//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
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//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
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logic [`DIVb+3:0] W;
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logic [`DIVb+3:0] W;
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logic SpecialCase;
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//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
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//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
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assign DivBusy = (state == BUSY);
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assign DivBusy = (state == BUSY);
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// calculate sticky bit
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// calculate sticky bit
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@ -90,13 +92,16 @@ module fdivsqrtfsm(
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assign NegSticky = W[`DIVb+3];
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assign NegSticky = W[`DIVb+3];
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assign EarlyTermShiftE = step;
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assign EarlyTermShiftE = step;
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// terminate immediately on special cases
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assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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state <= #1 IDLE;
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state <= #1 IDLE;
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end else if (DivStart&~StallE) begin
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end else if (DivStart&~StallE) begin
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step <= Dur;
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step <= Dur;
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if (XZeroE|(YZeroE&~SqrtE)|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE;
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if (SpecialCase) state <= #1 DONE;
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else state <= #1 BUSY;
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else state <= #1 BUSY;
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end else if (state == BUSY) begin
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end else if (state == BUSY) begin
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if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin
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if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin
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state <= #1 DONE;
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state <= #1 DONE;
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