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VCD support in all simulators

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This commit is contained in:
Jordan Carlin 2024-12-02 13:52:44 -08:00
parent d5159d35a2
commit 783b81f8b8
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2 changed files with 6 additions and 5 deletions
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2
bin/wsim
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@ -78,7 +78,7 @@ def elfFileCheck(args):
def prepSim(args, ElfFile): def prepSim(args, ElfFile):
flags = "" flags = ""
if args.vcd: if args.vcd:
args.args += " -DMAKEVCD=1" args.params += " MAKE_VCD=1 "
if args.rvvi: if args.rvvi:
args.params += " RVVI_SYNTH_SUPPORTED=1 " args.params += " RVVI_SYNTH_SUPPORTED=1 "
if args.tb == "testbench_fp": if args.tb == "testbench_fp":

9
testbench/testbench.sv
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@ -44,6 +44,7 @@ module testbench;
parameter I_CACHE_ADDR_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0;
parameter RVVI_SYNTH_SUPPORTED=0; parameter RVVI_SYNTH_SUPPORTED=0;
parameter MAKE_VCD=0;
`ifdef USE_IMPERAS_DV `ifdef USE_IMPERAS_DV
import idvPkg::*; import idvPkg::*;
@ -230,10 +231,10 @@ module testbench;
end end
$finish; $finish;
end end
`ifdef MAKEVCD if (MAKE_VCD) begin
$dumpfile("testbench.vcd"); $dumpfile("testbench.vcd");
$dumpvars; $dumpvars;
`endif end
end // initial begin end // initial begin
// Model the testbench as an fsm. // Model the testbench as an fsm.