Annotated the final changes required to move sram address off the critial path.

pipelined/src/cache/cachefsm.sv

@@ -105,14 +105,14 @@ module cachefsm
 
   (* mark_debug = "true" *) statetype CurrState, NextState;
 
-  assign DoFlush = FlushCache & ~IgnoreRequest;
+  assign DoFlush = FlushCache & ~IgnoreRequest; // *** have to fix ignorerequest timing path
-  assign DoAMO = Atomic[1] & (&RW) & ~IgnoreRequest;
+  assign DoAMO = Atomic[1] & (&RW) & ~IgnoreRequest; // ***
   assign DoAMOHit = DoAMO & CacheHit;
-  assign DoAMOMiss = DoAMOHit & ~CacheHit;  
+  assign DoAMOMiss = DoAMO & ~CacheHit;  
-  assign DoRead = RW[1] & ~IgnoreRequest;
+  assign DoRead = RW[1] & ~IgnoreRequest; // ***
   assign DoReadHit = DoRead & CacheHit;
   assign DoReadMiss = DoRead & ~CacheHit;
-  assign DoWrite = RW[0] & ~IgnoreRequest;
+  assign DoWrite = RW[0] & ~IgnoreRequest; // ***
   assign DoWriteHit = DoWrite & CacheHit;
   assign DoWriteMiss = DoWrite & ~CacheHit;
 
@@ -225,15 +225,15 @@ module cachefsm
                  (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
 
   // **** can this be simplified?
-  assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequest) | 
+  assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequest) | // *** ignorerequest comes from TrapM. Have to fix.  why is ignorerequest here anyway?
-                      (CurrState == STATE_READY & DoAMOHit) |
+                      (CurrState == STATE_READY & DoAMOHit) |  //<opHit> also depends on ignorerequest
                       (CurrState == STATE_READY & DoReadHit & (CPUBusy & `REPLAY)) |
                       (CurrState == STATE_READY & DoWriteHit) |
                       (CurrState == STATE_MISS_FETCH_WDV) |
                       (CurrState == STATE_MISS_FETCH_DONE) | 
                       (CurrState == STATE_MISS_WRITE_CACHE_LINE) | 
                       (CurrState == STATE_MISS_READ_WORD) |
-                      (CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | (CPUBusy & `REPLAY))) |
+                      (CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | (CPUBusy & `REPLAY))) | // ***
                       (CurrState == STATE_MISS_WRITE_WORD) |
                       (CurrState == STATE_MISS_EVICT_DIRTY) |
                       (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) |

pipelined/src/cache/cacheway.sv

@@ -121,13 +121,12 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   
   always_ff @(posedge clk) begin // Valid bit array, 
     if (reset | InvalidateAll)                              ValidBits        <= #1 '0;
-    else if (SetValidD)                                     ValidBits[RAdrD] <= #1 1'b1;
+    else if (SetValid)                                     ValidBits[RAdr] <= #1 1'b1;
-    else if (ClearValidD) ValidBits[RAdrD] <= #1 1'b0;
+    else if (ClearValid) ValidBits[RAdr] <= #1 1'b0;
 	end
   // *** consider revisiting whether these delays are the best option? 
   flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
-  flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid},
+  //flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid}, {SetValidD, ClearValidD});
-    {SetValidD, ClearValidD});
   assign Valid = ValidBits[RAdrD];
 
   /////////////////////////////////////////////////////////////////////////////////////////////
@@ -138,8 +137,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   if (DIRTY_BITS) begin:dirty
     always_ff @(posedge clk) begin
       if (reset)                                              DirtyBits        <= #1 {NUMLINES{1'b0}};
-      else if (SetDirtyD) DirtyBits[RAdrD] <= #1 1'b1;
+      else if (SetDirty) DirtyBits[RAdr] <= #1 1'b1;
-      else if (ClearDirtyD) DirtyBits[RAdrD] <= #1 1'b0;
+      else if (ClearDirty) DirtyBits[RAdr] <= #1 1'b0;
     end
     flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
     assign Dirty = DirtyBits[RAdrD];

pipelined/src/cache/sram1rw.sv

@@ -41,22 +41,25 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
   output logic [WIDTH-1:0] 	       ReadData);
 
   logic [WIDTH-1:0] StoredData[DEPTH-1:0];
-  logic [$clog2(DEPTH)-1:0] 	 AddrD;
+  logic [$clog2(DEPTH)-1:0] 	 AdrD;
   logic [WIDTH-1:0] 		 WriteDataD;
   logic 			 WriteEnableD;
 
     //*** model as single port
     // *** merge with simpleram
     always_ff @(posedge clk) begin
-      AddrD <= Adr;
+      AdrD <= Adr;
-      WriteDataD <= WriteData;    /// ****** this is not right. there should not need to be a delay.  Implement alternative cache stall to avoid this.  Eliminates a bunch of delay flops elsewhere
+      //WriteDataD <= WriteData;    /// ****** this is not right. there should not need to be a delay.  Implement alternative cache stall to avoid this.  Eliminates a bunch of delay flops elsewhere
-      WriteEnableD <= WriteEnable;
+      //WriteEnableD <= WriteEnable;
-        if (WriteEnableD) begin
+      //if (WriteEnableD) begin
-            StoredData[AddrD] <= #1 WriteDataD;
+        //StoredData[AddrD] <= #1 WriteDataD;
-        end
+      //end
+      if (WriteEnable) begin
+        StoredData[Adr] <= #1 WriteData;
+      end
     end
 
-  assign ReadData = StoredData[AddrD];
+  assign ReadData = StoredData[AdrD];
 /*
   always_ff @(posedge clk) begin
     ReadData <= RAM[Adr];

pipelined/src/lsu/interlockfsm.sv

@@ -112,7 +112,6 @@ module interlockfsm
 	  assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
 					   (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
 	  assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | TrapM)) |
-							 ((InterlockCurrState == STATE_T0_REPLAY)
+							 ((InterlockCurrState == STATE_T0_REPLAY) & (TrapM));
-							  & (TrapM));
 
 endmodule