Merge pull request #443 from davidharrishmc/dev

Wrapper synthesis fix.

.gitignore

@@ -62,6 +62,7 @@ examples/fp/fpcalc/fpcalc
 examples/C/inline/inline
 examples/C/sum_mixed/sum_mixed
 examples/asm/trap/trap
+examples/asm/etc/pause
 src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh

examples/asm/etc/Makefile

@@ -0,0 +1,11 @@
+TARGET = pause
+
+$(TARGET).objdump: $(TARGET)
+	riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump
+    
+pause: pause.S Makefile
+	riscv64-unknown-elf-gcc -o pause -march=rv32ia_zihintpause -mabi=ilp32 -mcmodel=medany \
+	    -nostartfiles -T../../link/link.ld  pause.S
+
+clean:
+	rm -f $(TARGET) $(TARGET).objdump

examples/asm/etc/pause.S

@@ -0,0 +1,25 @@
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+
+
+la a0, lock
+
+spinlock:				# address of lock is in a0
+	lr.w t0, (a0)		# read the lock
+	bnez t0, retry	    # spin until free
+	li   t1, 1          
+	sc.w t0, t1, (a0)	# try to write a 1 to take lock
+	bnez t0, retry	    # spin until successful
+	ret				    # got the lock!
+retry:				    # no lock yet
+	pause				# pause hint to reduce spin power
+	j spinlock			# try again
+
+
+self_loop:
+    j self_loop
+
+.data
+lock:   
+    .word 1

src/ebu/ebufsmarb.sv

@@ -116,5 +116,5 @@ module ebufsmarb (
   //  11          16     15
   always_comb 
     if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
-    else                      Threshold = (2 << HBURST[2:1]) - 1;
+    else                      Threshold = ('d2 << HBURST[2:1]) - 'd1;
 endmodule

src/ifu/ifu.sv

@@ -402,7 +402,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
 
   flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
   flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
-  assign PCLinkE = PCE + (CompressedE ? 2 : 4);
+  assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
 
   // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
   flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);

src/lsu/swbytemask.sv

@@ -33,7 +33,7 @@ module swbytemask #(parameter WORDLEN)(
   output logic [WORDLEN/8-1:0]         ByteMask
 );
   
-  assign ByteMask = ((2**(2**Size))-1) << Adr;
+  assign ByteMask =(('d2**('d2**Size))-'d1) << Adr; // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion
 
 /* Equivalent to the following
 

synthDC/scripts/synth.tcl

@@ -12,6 +12,8 @@ suppress_message {VER-130}
 # statements in initial blocks are ignored
 suppress_message {VER-281} 
 suppress_message {VER-173} 
+ # Unsupported system task '$warn'
+suppress_message {VER-274}
 
 # Enable Multicore
 set_host_options -max_cores $::env(MAXCORES)
@@ -107,6 +109,7 @@ if { $saifpower == 1 } {
 if {$drive != "INV"} {
     set_false_path -from [get_ports reset]
 }
+# for PPA multiplexer synthesis
 if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} {
     set_false_path -from {s}
 }
@@ -124,12 +127,13 @@ if {  $find_clock != [list] } {
     set my_clk $my_clock_pin
     create_clock -period $my_period $my_clk
     set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
-} else {
+ } else {
     echo "Did not find clock! Design is probably combinational!"
     set my_clk vclk
     create_clock -period $my_period -name $my_clk
 }
 
+
 # Optimize paths that are close to critical
 set_critical_range 0.05 $current_design
 
@@ -253,6 +257,19 @@ set write_hier 1        ;# generate hierarchy report
 if { $wrapper == 1 } {
     set designname [format "%s%s" $my_design "__*"]
     current_design $designname
+
+    # recreate clock below wrapper level or reporting doesn't work properly
+    set find_clock [ find port [list $my_clock_pin] ]
+    if {  $find_clock != [list] } {
+        echo "Found clock!"
+        set my_clk $my_clock_pin
+        create_clock -period $my_period $my_clk
+        set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
+    } else {
+        echo "Did not find clock! Design is probably combinational!"
+        set my_clk vclk
+        create_clock -period $my_period -name $my_clk
+    }
 } 
 
 # Report Constraint Violators