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Fixed first problem with the rv64i IROM.
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@ -42,6 +42,11 @@ module irom(
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rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
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rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
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if (`XLEN == 32) assign ReadData = ReadDataFull;
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if (`XLEN == 32) assign ReadData = ReadDataFull;
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else assign ReadData = Adr[OFFSET] ? ReadDataFull[63:32] : ReadDataFull[31:0];
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// have to delay Ardr[OFFSET-1] by 1 cycle
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else begin
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logic AdrD;
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flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
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assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0];
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end
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endmodule
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endmodule
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