From 77ba71be71fd540029f6efe2350f9968eee301b2 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 7 Mar 2023 06:31:40 -0800
Subject: [PATCH] editorconfig to specify tabs/spaces.  Fixed some tabs.  Turn
 off coverage to speed up simulation

---
 .editorconfig                       |  5 +++++
 sim/wally-batch.do                  | 12 +++++++++++-
 src/fpu/fdivsqrt/fdivsqrtexpcalc.sv |  2 +-
 src/fpu/fdivsqrt/fdivsqrtpreproc.sv |  2 +-
 src/mdu/mdu.sv                      | 10 +++++-----
 5 files changed, 23 insertions(+), 8 deletions(-)
 create mode 100644 .editorconfig

diff --git a/.editorconfig b/.editorconfig
new file mode 100644
index 000000000..2a9c5c8c5
--- /dev/null
+++ b/.editorconfig
@@ -0,0 +1,5 @@
+root = true
+
+[src/**.sv]
+indent_style = space
+indent_size = 2
\ No newline at end of file
diff --git a/sim/wally-batch.do b/sim/wally-batch.do
index 7e63de8ad..53ea2e004 100644
--- a/sim/wally-batch.do
+++ b/sim/wally-batch.do
@@ -32,6 +32,9 @@ if {$2 eq "ahb"} {
     }
     vlib wkdir/work_${1}_${2}
 }
+# Create directory for coverage data
+mkdir -p cov
+
 # compile source files
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
@@ -80,7 +83,8 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
     # start and run simulation
     # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
+    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf
+#    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829 -coverage
     vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
     # Adding coverage increases runtime from 2:00 to 4:29.  Can't run it all the time
     #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
@@ -91,6 +95,12 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     # power off -r /dut/core/*
 } 
 
+coverage save -instance /testbench/dut cov/${1}_${2}.ucdb
+#vcover merge -out cov/cov.ucdb cov/rv*.ucdb
+#vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log
+
+#vcover merge -out cov/cov.ucdb cov
+#vcover report cov/cov.ucdb > cov/rpt
 #coverage report -file wally-coverage.txt
 # These aren't doing anything helpful
 #coverage report -memory 
diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
index 07cffa268..b5b2ba335 100644
--- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
@@ -69,6 +69,6 @@ module fdivsqrtexpcalc(
   assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
   
   // correct exponent for subnormal input's normalization shifts
-  assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
+  assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}}; // *** why Xzero?  Is this a hack for postprocessor?
   assign Qe = Sqrt ? SExp : DExp;
 endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 0a96e1b1a..c5485c26f 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -151,7 +151,7 @@ module fdivsqrtpreproc (
   lzc #(`DIVb) lzcY (IFNormLenD, mE);
 
   // Normalization shift
-  assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); 
+  assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
   assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); 
 
   // append leading 1 (for normal inputs)
diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv
index b62add60d..21d4dd4bc 100644
--- a/src/mdu/mdu.sv
+++ b/src/mdu/mdu.sv
@@ -32,11 +32,11 @@ module mdu(
   input  logic 							clk, reset,
   input  logic 							StallM, StallW, 
   input  logic							FlushE, FlushM, FlushW,
-	input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
-	input  logic [2:0] 				Funct3E, Funct3M,									// type of MDU operation
-	input  logic 							IntDivE, W64E, 										// Integer division/remainder, and W-type instrutions
-	output logic [`XLEN-1:0] 	MDUResultW,												// multiply/divide result
-	output logic 							DivBusyE													// busy signal to stall pipeline in Execute stage
+  input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
+  input  logic [2:0] 				Funct3E, Funct3M,									// type of MDU operation
+  input  logic 							IntDivE, W64E, 										// Integer division/remainder, and W-type instrutions
+  output logic [`XLEN-1:0] 	MDUResultW,												// multiply/divide result
+  output logic 							DivBusyE													// busy signal to stall pipeline in Execute stage
 );
 
 	logic [`XLEN*2-1:0] 			ProdM; 														// double-width product from mul