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Fixed timing constraint issue.

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This commit is contained in:
Ross Thompson 2023-04-17 19:53:43 -05:00
parent b2b30936be
commit 777bec2e24
2 changed files with 2 additions and 2 deletions
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2
fpga/constraints/constraints-ArtyA7.xdc
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@ -213,7 +213,7 @@ set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
# **** may have to bring this one back
#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 15.000
#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK]

2
fpga/constraints/small-debug.xdc
View File

@ -17,7 +17,7 @@ set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_ddr3_infrastructure/CLK ]]
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]