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https://github.com/openhwgroup/cvw
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LSU no longer has ***.
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@ -351,11 +351,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
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.BusStall, .BusCommitted(BusCommittedM));
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.BusStall, .BusCommitted(BusCommittedM));
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// Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM
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// Uncache bus access may be smaller width than LLEN. Duplicate LLENPOVERAHBW times.
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// *** DTIMReadDataWordM should be increased to LLEN.
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// pma should generate exception for LLEN read to periph.
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mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
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mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
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.d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
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.d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
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.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
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.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
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@ -374,7 +369,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
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// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
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if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
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if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
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else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
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else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0];
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assign LSUHBURST = 3'b0;
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assign LSUHBURST = 3'b0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0;
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end
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end
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