From 7737b0f7093f276c5b7afdc4a10058742e076639 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 23 Feb 2021 09:08:57 -0500
Subject: [PATCH] Fixed fetch stall after jump in bus unit

---
 wally-pipelined/src/hazard/hazard.sv           |  6 +++++-
 wally-pipelined/src/privileged/csr.sv          |  4 +++-
 wally-pipelined/testbench/testbench-imperas.sv | 11 ++++-------
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
index c45fb47f4..a6cdd82cf 100644
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@@ -56,7 +56,11 @@ module hazard(
 
   assign BranchFlushDE = PCSrcE | RetM | TrapM;
 
-  assign StallFCause = /*InstrStall | */ CSRWritePendingDEM;  // stall at fetch if unable to get the instruction, 
+  // changed 2/22/21 harris to turn off stallF when RetM or TrapM
+  // changed 2/23/21 harris to BranchFlushDEM to solve bug in ECALL about JAL being ignored
+//  assign StallFCause = /*InstrStall | */ CSRWritePendingDEM;  // stall at fetch if unable to get the instruction, 
+//  assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(RetM | TrapM);  // stall at fetch if unable to get the instruction, 
+  assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(BranchFlushDE);  // stall at fetch if unable to get the instruction, 
                                                          // or if a CSR will be written and may change system behavior
   assign StallDCause = LoadStallD;                       // stall in decode if instruction is a load dependent on previous
   assign StallECause = 0;
diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index e1e76aa02..bee0ba86c 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -102,7 +102,9 @@ module csr (
 
       // merge CSR Reads
       assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; 
-      floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW);
+      // *** add W stall 2/22/21 dh to try fixing memory stalls
+//      floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW);
+      flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
 
       // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
       assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index fd49fee0a..491301cd6 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -75,8 +75,6 @@ string tests64iNOc[] = {
                      "rv64i/I-MISALIGN_JMP-01","2000"
   };
  string tests64i[] = '{                 
-                     "rv64i/I-ECALL-01", "2000",
-                     "rv64i/I-ENDIANESS-01", "2010",
                      "rv64i/I-ADD-01", "3000",
                      "rv64i/I-ADDI-01", "3000",
                      "rv64i/I-ADDIW-01", "3000",
@@ -91,8 +89,8 @@ string tests64iNOc[] = {
                      "rv64i/I-BLTU-01", "4000",
                      "rv64i/I-BNE-01", "4000",
                      "rv64i/I-DELAY_SLOTS-01", "2000",
-//                     "rv64i/I-EBREAK-01", "2000",
-//                     "rv64i/I-ECALL-01", "2000",
+                     "rv64i/I-EBREAK-01", "2000",
+                     "rv64i/I-ECALL-01", "2000",
                      "rv64i/I-ENDIANESS-01", "2010",
                      "rv64i/I-IO-01", "2050",
                      "rv64i/I-JAL-01", "3000",
@@ -105,7 +103,7 @@ string tests64iNOc[] = {
                      "rv64i/I-LUI-01", "2000",
                      "rv64i/I-LW-01", "4110",
                      "rv64i/I-LWU-01", "4110", 
-                     //"rv64i/I-MISALIGN_LDST-01", "2010",
+                     "rv64i/I-MISALIGN_LDST-01", "2010",
                      "rv64i/I-NOP-01", "2000",
                      "rv64i/I-OR-01", "3000",
                      "rv64i/I-ORI-01", "3000",
@@ -140,7 +138,6 @@ string tests64iNOc[] = {
                      "rv64i/WALLY-SUB", "4000"
   };
 string tests32ic[] = '{
-//                     "rv32ic/WALLY-C-ADHOC-01", "2000",
                      "rv32ic/I-C-ADD-01", "2000",
                      "rv32ic/I-C-ADDI-01", "2000",
                      "rv32ic/I-C-AND-01", "2000",
@@ -239,7 +236,7 @@ string tests32i[] = {
   initial 
     if (`XLEN == 64) begin // RV64
       tests = {tests64i};
-      if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic};
+      if (`C_SUPPORTED % 2 == 1) tests = {tests64ic, tests};
       else                       tests = {tests, tests64iNOc};
     end else begin // RV32
       tests = {tests32i};